ATF54143 HP | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
- High linearity performance
- Enhancement Mode Technology [1]
- Low noise figure
- Excellent uniformity in product specifications
- 800 micron gate width
- Low cost surface mount small plastic package SOT-343 (4 lead SC-70)
- Tape-and-Reel packaging option available Specifications 2 GHz; 3 V, 60 mA (Typ.)
- 36.2 dBm output 3 rd order intercept
- 20.4 dBm output power at 1 dB gain compression
- 0.5 dB noise figure
- 16.6 dB associated gain
Applications
- Low noise amplifier for cellular/ PCS base stations
- LNA for WLAN, WLL/RLL and MMDS applications
- General purpose discrete E-PHEMT for other ultra low noise applications Note: 1. Enhancement mode technology requires positive Vgs, thereby eliminating the need for the negative gate voltage associated with conventional depletion mode devices. Surface Mount Package SOT-343 Pin Connections and Package Marking SOURCE DRAIN GATE SOURCE 4Fx Note: T op View. Package marking provides orientation and identification “4F” = Device Code “x” = Date code character identifies month of manufacture.
Symbol Parameter and T est Condition Units Min. Typ. [2] Max.
- Measurements obtained using production test board described in Figure 5.
- T ypical values measured from a sample size of 450 parts from 9 wafers.
50 Ohm
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. Thi s circuit repre-
- F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of
16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate
within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 19. MSG/MAG and |S21|2 vs.
- F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of
16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate
within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 20. MSG/MAG and |S21|2 vs.
- F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of
16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate
within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 21. MSG/MAG and |S21|2 vs.
- F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of
16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate
within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 22. MSG/MAG and |S21|2 vs.
source for normal operation. typical bipolar junction transistor. covering specific applications). Figure 1. Typical ATF-54143 LNA with Passive improves low frequency stability. VDD is the power supply voltage. Ids is the desired drain current.
a bipolar junction transistor. Figure 2. Typical ATF-54143 LNA with base of a PNP transistor at Q2. supply for the drain current. junction of resistors R1 and R2.
G Num=1 C C=0.13 pF Port Num=2 SOURCE DRAIN Port Num=4 Port D Num=3 L L=0.175 nH R=0.001 C C=0.159 pF L L=0.746 nH R=0.001MSub TLINP TL4 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 TLINP TL10 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 TLINP TL3 Z=Z2 Ohm L=25 mil K=K A=0.000 F=1 GHz TanD=0.001 TLINP TL9 Z=Z2 Ohm L=10.0 mil K=K A=0.000 F=1 GHz TanD=0.001 VAR VAR1 K=5 Z2=85 Z1=30 Var Egn TLINP TL1 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL2 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL8 Z=Z1 Ohm L=15.0 mil K=1 A=0.0000 F=1 GHz TanD=0.001 TLINP TL7 Z=Z2/2 Ohm L=5.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL5 Z=Z2 Ohm L=26.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL6 Z=Z1 Ohm L=15.0 mil K=1 A=0.0000 F=1 GHz TanD=0.001 L L=0.477 nH R=0.001 L L=0.4 nH R=0.001 GaAsFET FET1 Mode1=MESFETM1 Mode=NonlinearMSUB MSub1 H=25.0 mil Er=9.6 Mur=1 Cond=1.0E+50 Hu=3.9e+034 mil T=0.15 mil TanD=0 Rough=0 mil NFET=yes PFET=no Vto=0.3 Beta=0.9 Lambda=82e-3 Alpha=13 Tau= Tnom=16.85 Idstc= Ucrit=-0.72 Vgexp=1.91 Gamds=1e-4 Vtotc= Betatce= Rgs=0.25 Ohm Rf= Gscap=2 Cgs=1.73 pF Cgd=0.255 pF Gdcap=2 Fc=0.65 Rgd=0.25 Ohm Rd=1.0125 Ohm Rg=1.0 Ohm Rs=0.3375 Ohm Ld= Lg=0.18 nH Ls= Cds=0.27 pF Rc=250 Ohm Crf=0.1 F Gsfwd= Gsrev= Gdfwd= Gdrev= R1= R2= Vbi=0.8 Vbr= Vjr= Is= Ir= Imax= Xti= Eg= Fnc=1 MHz R=0.08 P=0.2 C=0.1 Taumdl=no wVgfwd= wBvgs= wBvgd= wBvds= wldsmax= wPmax= AllParams= Advanced_Curtice2_Model MESFETM1 ATF-54143 Die Model ATF-54143 curtice ADS Model
Figure 3. Adding Vias to the ATF-54143 Non-Linear Model for Comparison to Measured S and Noise Parameters.
Noise Parameter Applications Information F min values at 2GHz and higher are based on measurements while the F mins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements, a true F min is calculated. Fmin repre- sents the true minimum noise figure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω , to an impedance represented by the reflection coefficient G o. The designer must design a matching network that will present G o to the device with minimal associ- ated circuit losses. The noise figure of the completed amplifier is equal to the noise figure of the device plus the losses of the matching network preceding the device. The noise figure of the device is equal to F min only when the device is presented with Go. If the reflection coefficient of the matching network is other than G o, then the noise figure of the device will be greater than Fmin based on the following equation. NF = Fmin + 4 Rn |Γs – Γo | 2 Where Rn/Zo is the normalized noise resistance, Γo is the opti- mum reflection coefficient required to produce F min and Γs is the reflection coefficient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. Γ o is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower Γ o as compared to narrower gate width devices. Typically for FETs, the higher Γ o usually infers that an impedance much higher than 50Ω is required for the device to produce Fmin. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Match- ing to such a high impedance requires very hi-Q components in order to minimize circuit losses. As an example at 900 MHz, when airwwound coils (Q >100) are used for matching networks, the loss can still be up to 0.25 dB which will add directly to the noise figure of the device. Using muiltilayer molded inductors with Qs in the 30 to 50 range results in additional loss over the airwound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB F min of the device creating an amplifier noise figure of nearly 0.65 dB. A discussion concerning calculated and measured circuit losses and their effect on ampli- fier noise figure is covered in Agilent Application 1085.
E D A A1b TYP e 1.30 (0.051) BSC 1.15 (.045) BSC θ h C TYPL DIMENSIONS ARE IN MILLIMETERS (INCHES) DIMENSIONS MIN. 0.80 (0.031) 0 (0) 0.25 (0.010) 0.10 (0.004) 1.90 (0.075) 2.00 (0.079) 0.55 (0.022) 0.450 TYP (0.018) 1.15 (0.045) 0.10 (0.004) MAX. 1.00 (0.039) 0.10 (0.004) 0.35 (0.014) 0.20 (0.008) 2.10 (0.083) 2.20 (0.087) 0.65 (0.025) 1.35 (0.053) 0.35 (0.014) SYMBOL A b C D E e h L θ 1.15 (.045) REF 1.30 (.051) REF 1.30 (.051) 2.60 (.102) Package Dimensions Outline 43 SOT-343 (SC70 4-lead)
Ordering Information
Part Number No. of Devices Container ATF-54143-TR1 3000 7 ” Reel ATF-54143-TR2 10000 13 ”Reel ATF-54143-BLK 100 antistatic bag
P F W C D 1 D E A 0 8° MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 5° MAX. B 0 K 0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A B 0 K 0 P D 1 2.24 ± 0.10 2.34 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.088 ± 0.004 0.092 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 + 0.010 CAVITY DIAMETER PITCH POSITION D P E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 ± 0.30 0.255 ± 0.013 0.315 ± 0.012 0.010 ± 0.0005 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 COVER TAPE Device Orientation T ape Dimensions For Outline 4T www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. Obsoletes 5988-0450EN May 31, 2001 5988-2722EN