ATF-531P8 HP | Alldatasheet

Document overview

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Technical content

Features

  • Single voltage operation
  • High linearity and gain
  • Low noise figure
  • Excellent uniformity in product specifications
  • Small package size: 2.0 x 2.0 x 0.75 mm
  • Point MTTF > 300 years [2]
  • MSL-1 and lead-free
  • Tape-and-reel packaging option available Specifications 2 GHz; 4V, 135 mA (Typ.)
  • 38 dBm output IP3
  • 0.6 dB noise figure
  • 20 dB gain
  • 10.7 dB LFOM[4]
  • 24.5 dBm output power at 1 dB gain compression

Applications

  • Front-end LNA Q1 and Q2 driver or pre-driver amplifier for Cellular/ PCS and WCDMA wireless infrastructure
  • Driver amplifier for WLAN, WLL/RLL and MMDS applications
  • General purpose discrete E-pHEMT for other high linearity applications Pin Connections and Package MarkingNote: Package marking provides orientation and identification: “3P” = Device Code “x” = Date code indicates the month of manufacture.Note: 1. Enhancement mode technology employs a single positive V gs, eliminating the need of negative gate voltage associated with conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data. 3. Conforms to JEDEC reference outline MO229 for DRP-N 4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power. Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source) Pin 8 Pin 7 (Drain) Pin 6 Pin 5 3Px Top View Pin 8 Source (Thermal/RF Gnd) Pin 7 (Drain) Pin 6 Pin 5 Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source) Bottom View

TA = 25°C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified. Symbol Parameter and T est Condition Units Min. Typ. Max.

  1. Measurements obtained using production test board described in Figure 6.

50 Ohm

Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.

Figure 7. Simplified schematic of production test board. Primary purpose is to show 15 Ohm series resistor placement in gate supply. Transmission line tapers, tee intersections, bias lines and parasitic values are not shown.

110 Ohm

15 Ohm

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 28. MSG/MAG & |S21|2

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 29. MSG/MAG & |S21|2

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 30. MSG/MAG & |S21|2

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 31. MSG/MAG & |S21|2

  1. F min values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of

16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements a true Fmin is calculated.

  1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the gate

lead. The output reference plane is at the end of the drain lead. Figure 32. MSG/MAG & |S21|2

2 x 2 LPCC (JEDEC DFP-N) Package Dimensions

Ordering Information

Part Number No. of Devices Container ATF-531P8-TR1 3000 7 ” Reel ATF-531P8-TR2 10000 13 ”Reel ATF-531P8-BLK 100 antistatic bag Device Models Refer to Agilent’s Web Site www.agilent.com/view/rf D E A P e pin1 R L b DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MIN. 0.70 0.225 1.9 0.65 1.9 1.45 0.20 0.35 NOM. 0.75 0.02

0.203 REF

0.25 2.0 0.80 2.0 1.6

0.50 BSC

0.25 0.40 MAX. 0.80 0.05 0.275 2.1 0.95 2.1 1.75 0.30 0.45 SYMBOL A b D E e P L pin1 3PX Top View End ViewSide View Bottom View A A1

PCB Land Pattern and Stencil Design 2.80 (110.24) 0.70 (27.56) 0.25 (9.84) 0.25 (9.84) 0.50 (19.68) 0.28 (10.83) 0.60 (23.62) φ0.20 (7.87) PIN 1 Soldermask RF transmission line 0.80 (31.50) 0.15 (5.91) 0.55 (21.65) 1.60 (62.99) 2.72 (107.09) 0.63 (24.80) 0.22 (8.86) 0.32 (12.79) 0.50 (19.68) 0.25 (9.74) 0.63 (24.80) Stencil Layout (top view)PCB Land Pattern (top view) 0.72 (28.35) PIN 1 1.54 (60.61) USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL 8 mm 4 mm 3PX3PX3PX3PX

F W E 10° Max DESCRIPTION SYMBOL SIZE (mm) SIZE (inches) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER P 2.30 ± 0.05 2.30 ± 0.05 1.00 ± 0.05 4.00 ± 0.10 1.00 + 0.25 0.091 ± 0.004 0.091 ± 0.004 0.039 ± 0.002 0.157 ± 0.004 0.039 + 0.002 CAVITY DIAMETER PITCH POSITION D E 1.50 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.060 ± 0.004 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 0.254 ± 0.02 0.315 ± 0.012 8.00 – 0.10 0.315 ± 0.004 0.010 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.0004 COVER TAPE D Tt 10° Max

www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788 6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. Obsoletes 5988-8407EN (12/02) July 31, 2003 5988-9990EN