ATF-34143 HP | Alldatasheet
Document overview
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Technical content
Features
- Low Noise Figure
- Excellent Uniformity in Product Specifications
- 800 micron Gate Width
- Low Cost Surface Mount Small Plastic Package SOT-343 (4 lead SC-70)
- Tape-and-Reel Packaging Option Available Specifications 1.9 GHz; 4 V, 60 mA (Typ.)
- 0.5 dB Noise Figure
- 17.5 dB Associated Gain
- 20 dBm Output Power at 1 dB Gain Compression
- 31.5 dBm Output 3rd Order Intercept
Applications
- Tower Mounted Amplifier and Low Noise Amplifier for GSM/TDMA/CDMA Base Stations
- LNA for Wireless LAN, WLL/ RLL and MMDS Applications
- General Purpose Discrete PHEMT for other Ultra Low Noise Applications Surface Mount Package SOT-343
Description
Agilent’s ATF-34143 is a high dynamic range, low noise PHEMT housed in a 4-lead SC-70 (SOT-343) surface mount plastic package. Based on its featured performance, ATF-34143 is ideal for the first stage of base station LNA due to the excellent combination of low noise figure and high linearity[1]. The device is also suitable for applications in Wireless LAN, WLL/RLL, MMDS, and other systems requiring super low noise figure with good intercept in the
450 MHz to 10 GHz frequency
range. Note: 1. From the same PHEMT FET family, the larger geometry ATF-33143 may also be considered either for the higher linearity performance or easier circuit design for stability in the lower frequency bands (800-900 MHz). Pin Connections and Package Marking Note: Top View. Package marking provides orientation and identification. “4P” = Device code “x” = Date code character. A new character is assigned for each month, year. GATE 4Px SOURCE DRAIN SOURCE
- Operation of this device above any one
- Assumes DC quiescent conditions.
- Source lead temperature is 25°C.
Derate 6 mW/°C for TL > 40°C.
- Thermal resistance measured using
- Under large signal conditions, VGS may
Figure 1. Typical/Pulsed I-V Curves[6]. Figure 2. OIP3 @ 2 GHz, 4 V, 60 mA.
9 Wafers
Figure 3. NF @ 2 GHz, 4 V, 60 mA. Figure 4. Gain @ 2 GHz, 4 V, 60 mA.
- Distribution data sample size is 450
samples taken from 9 different wafers. within the upper and lower spec limits.
- Measurements made on production
on production test requirements.
- Guaranteed at wafer probe level
- Typical value determined from a sample size of 450 parts from 9 wafers.
- Using production test board.
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measure- losses. Circuit losses have been de-embedded from actual measurements.
50 Ohm
Figure 23. MSG/MAG and |S21|2 vs.
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the
Figure 24. MSG/MAG and |S21|2 vs.
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the
Figure 25. MSG/MAG and |S21|2 vs.
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the
Figure 26. MSG/MAG and |S21|2 vs.
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the
Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements, a true Fmin is calculated. Fmin represents the true minimum noise figure of the device when the device is pre- sented with an impedance matching network that trans- forms the source impedance, typically 50Ω, to an impedance represented by the reflection coefficient Γo. The designer must design a matching network that will present Γo to the device with minimal associated circuit losses. The noise figure of the completed amplifier is equal to the noise figure of the device plus the losses of the matching network preceding the device. The noise figure of the device is equal to Fmin only when the device is presented with Γo. If the reflec- tion coefficient of the matching network is other than Γo, then the noise figure of the device will be greater than Fmin based on the following equation. NF = Fmin + 4 Rn |Γs – Γo | 2 Zo (|1 + Γo|2)(1 – Γs|2) Where Rn/Zo is the normalized noise resistance, Γo is the opti- mum reflection coefficient required to produce Fmin and Γs is the reflection coefficient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. Γo is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower Γo as compared to narrower gate width devices. Typically for FETs, the higher Γo usually infers that an impedance much higher than 50Ω is required for the device to produce Fmin. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high imped- ance requires very hi-Q compo- nents in order to minimize circuit losses. As an example at 900 MHz, when airwwound coils (Q>100) are used for matching networks, the loss can still be up to 0.25 dB which will add directly to the noise figure of the device. Using muiltilayer molded inductors with Qs in the 30 to 50 range results in additional loss over the airwound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB Fmin of the device creating an amplifier noise figure of nearly 0.65 dB. A discussion concerning calculated and measured circuit losses and their effect on ampli- fier noise figure is covered in Agilent Application 1085.
L=Lc L=Lb R=Rb L=Lb R=Rb L C C=Ca C C=Cb LOSSYL L=Lb R=Rb L=La*.5 L=Ld L L LOSSYL GATE_IN SOURCE DRAIN_OUT R EQUATION La=0.1 nH EQUATION Lb=0.1 nH EQUATION Lc=0.8 nH EQUATION Ld=0.6 nH EQUATION Rb=0.1 OH EQUATION Ca=0.15 pF EQUATION Cb=0.15 pF R=0.1 OH LOSSYL L=La L=Lb R=Rb L LOSSYL L=Lb R=Rb LOSSYL G S D SOURCE ATF-34143 SC-70 4 Lead, High Frequency Nonlinear Model Optimized for 0.1– 6.0 GHz This model can be used as a design tool. It has been tested on MDS for various specifications. However, for more precise and accurate design, please refer to the measured data in this data sheet. For future improvements Agilent reserves the right to change these models without prior notice. NFETMESFET G MODEL=FET W=800 µm XX D XX S S XX NFET=yes PFET= IDSMOD=3 VTO=–0.95 BETA= Beta LAMBDA=0.09 ALPHA=4.0 B=0.8 TNOM=27 IDSTC= VBI=.7 IDS model DELTA=.2 GSCAP=3 CGS=cgs pF GDCAP=3 GCD=Cgd pF Gate model RG=1 RD=Rd RS=Rs LG=Lg nH LD=Ld nH LS=Ls nH CDS=Cds pF CRF=.1 RC=Rc Parasitics GSFWD=1 GSREV=0 GDFWD=1 GDREV=0 VJR=1 IS=1 nA IR=1 nA IMAX=.1 XTI= EG= Breakdown FNC=01e+6 R=.17 P=.65 C=.2 Noise Model scal factors (W=FET width in microns) EQUATION Cds=0.01*W/200 EQUATION Beta=0.06*W/200 EQUATION Rd=200/W EQUATION Rs=.5*200/W EQUATION Cgs=0.2*W/200 EQUATION Cgd=0.04*W/200 EQUATION Lg=0.03*200/W EQUATION Ld=0.03*200/W EQUATION Ls=0.01*200/W EQUATION Rc=500*200/W * STATZ MESFET MODEL * MODEL = FET ATF-34143 Die Model
Part Number Ordering Information No. of Part Number Devices Container ATF-34143-TR1 3000 7" Reel ATF-34143-TR2 10000 13" Reel ATF-34143-BLK 100 antistatic bag Package Dimensions Outline 43 (SOT-343/SC-70 4 lead) E D A b TYP e 1.30 (0.051) BSC 1.15 (.045) BSC θ h C TYP L DIMENSIONS ARE IN MILLIMETERS (INCHES) DIMENSIONS MIN. 0.80 (0.031) 0 (0) 0.25 (0.010) 0.10 (0.004) 1.90 (0.075) 2.00 (0.079) 0.55 (0.022) 0.450 TYP (0.018) 1.15 (0.045) 0.10 (0.004) MAX. 1.00 (0.039) 0.10 (0.004) 0.35 (0.014) 0.20 (0.008) 2.10 (0.083) 2.20 (0.087) 0.65 (0.025) 1.35 (0.053) 0.35 (0.014) SYMBOL A b C D E e h L θ 1.15 (.045) REF 1.30 (.051) REF 1.30 (.051) 2.60 (.102) 0.55 (.021) TYP 0.85 (.033)
P F W C D E 8° MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 5° MAX. SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER P 2.24 ± 0.10 2.34 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.088 ± 0.004 0.092 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 + 0.010 CAVITY DIAMETER PITCH POSITION D E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 ± 0.30 0.255 ± 0.013 0.315 ± 0.012 0.010 ± 0.0005 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 COVER TAPE 4PX 4PX 4PX 4PX
www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. Obsoletes 5968-7938E October 26, 2001 5988-4210EN