ATECC608B-SSHDA-B

ATECC608B MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

Cryptographic Co-Processor with Secure Hardware-Based Key Storage: – Protected storage for up to 16 keys, certificates or data
Hardware Support for Asymmetric Sign, Verify, Key Agreement: – ECDSA: FIPS186-3 Elliptic Curve Digital Signature – ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman – NIST Standard P256 Elliptic Curve Support
Hardware Support for Symmetric Algorithms: – SHA-256 & HMAC Hash including off-chip context save/restore – AES-128: Encrypt/Decrypt, Galois Field Multiply for GCM
Networking Key Management Support: – Turnkey PRF/HKDF calculation for TLS 1.2 & 1.3 – Ephemeral key generation and key agreement in SRAM – Small message encryption with keys entirely protected
Secure Boot Support: – Full ECDSA code signature validation, optional stored digest/signature – Optional communication key disablement prior to secure boot – Encryption/Authentication for messages to prevent on-board attacks
Internal High-Quality NIST SP 800-90A/B/C Random Number Generator (RNG)
Two High-Endurance Monotonic Counters
Unique 72-Bit Serial Number
Two Interface Options Available: – High-Speed Single Wire Interface with One GPIO Pin – 1 MHz Standard I 2C Interface
1.8V to 5.5V IO Levels, 2.0V to 5.5V Supply Voltage
Two Temperature Ranges Available: – Standard Industrial Temperature Range: -40 ℃ to +85℃ – Extended Industrial Temperature Range: -40 ℃ to +100℃
<150 nA Sleep Current
Packaging Options – 8-pad UDFN, 8-lead SOIC and 3-Lead Contact Package Options – Die-on-Tape and Reel and WLCSP for Qualified Customers (Contact Microchip Sales)

Applications

IoT network endpoint key management & exchange
Encryption for small messages and PII data
Secure Boot and Protected Download
Ecosystem Control, Anti-cloning This is a summary document. A complete document is available under NDA. For more information, please contact your local Microchip sales office. © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 1

Table 1. Pin Configuration Figure 1. Package Types Note: The UDFN backside paddle is recommended to be connected to GND.

Introduction The ATECC608B is a member of the Microchip CryptoAuthentication™ family of high-security cryptographic devices, which combine world-class, hardware-based key storage with hardware cryptographic accelerators to implement various authentication and encryption protocols. The ATECC608B provides security enhancements over that of the ATECC608A, while providing complete backwards compatibility. All configuration settings, commands, packages and functionality of the ATECC608A are still available in the ATECC608B, making migration from the ATECC608A a simple process. For new designs, it is recommended that customers start directly with the ATECC608B device. For designs that are being upgraded and currently use the ATECC508A or the ATECC608A, it is recommended that they move to the ATECC608B. For designs not planned to be upgraded, it is recommended that customers review their designs to see if they would benefit from the enhanced security of the ATECC608B. For assistance with migrating a design to the ATECC608B, see the Migrations References section. For more information on compatibility with other Microchip CryptoAuthentication products, please see Section 3. Compatibility. Migration References: 1. AN3539: Provides guidance on migrating from the ATECC508A to the ATECC608B 2. AN2237: Provides guidance on migrating from the ATECC608A to the ATECC608B

1.1 Applications

The ATECC608B has a flexible command set that allows use in many applications, including the following:

Network/IoT Node Endpoint Security Manages node identity authentication and session key creation and management. Supports the entire ephemeral session key-generation flow for multiple protocols, including TLS 1.2 (and earlier) and TLS 1.3.
Secure Boot Supports the MCU host by validating code digests and optionally enabling communication keys on success. Various configurations to offer enhanced performance are available.
Small Message Encryption Contains a hardware AES engine to encrypt and/or decrypt small messages or data such as PII information. Supports the AES-ECB mode directly. Other modes can be implemented with the help of the host microcontroller. There is an additional GFM calculation function to support AES-GCM.
Key Generation for Software Download Supports local protected key generation for downloaded images. Both broadcast of one image to many systems, each with the same decryption key, or point-to-point download of unique images per system are supported.
Ecosystem Control and Anti-Counterfeiting Validates that a system or component is authentic and came from the OEM shown on the nameplate.

1.2 Device Features

The ATECC608B includes an EEPROM array which can be used for storage of up to 16 keys, certificates, miscellaneous read/write, read-only or secret data, consumption logging and security configurations. Access to the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent changes. Access to the device is made through a standard I2C Interface at speeds of up to 1 Mbps. The interface is compatible with standard Serial EEPROM I2C interface specifications. The device also supports a Single-Wire Interface (SWI), which can reduce the number of GPIOs required on the system processor, and/or reduce the number of pins on connectors. If the Single-Wire Interface is enabled, the remaining pin is available for use as a GPIO, an authenticated output or tamper input. Each ATECC608B ships with an ensured unique 72-bit serial number. Using the cryptographic protocols supported by the device, a host system or remote server can verify a signature of the serial number to prove that the serial ATECC608B Introduction © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 4

number is authentic and not a copy. Serial numbers are often stored in a standard Serial EEPROM; however, these can be easily copied with no way for the host to know if the serial number is authentic or if it is a clone. The ATECC608B features a wide array of defense mechanisms specifically designed to prevent physical attacks on the device itself, or logical attacks on the data transmitted between the device and the system. Hardware restrictions on the ways in which keys are used or generated provide further defense against certain styles of attack.

1.3 Cryptographic Operation

The ATECC608B implements a complete asymmetric (public/private) key cryptographic signature solution based upon Elliptic Curve Cryptography and the ECDSA signature protocol. The device features hardware acceleration for the NIST standard P256 prime curve and supports the complete key life cycle from high quality private key generation, to ECDSA signature generation, ECDH key agreement and ECDSA public key signature verification. The hardware accelerator can implement such asymmetric cryptographic operations from ten to one-thousand times faster than software running on standard microprocessors, without the usual high risk of key exposure that is endemic to standard microprocessors. The ATECC608B also implements AES-128, SHA256 and multiple SHA derivatives such as HMAC(SHA), PRF (the key derivation function in TLS) and HKDF in hardware. Support is included for the Galois Field Multiply (aka Ghash) to facilitate GCM encryption/decryption/authentication. The device is designed to securely store multiple private keys along with their associated public keys and certificates. The signature verification command can use any stored or an external ECC public key. Public keys stored within the device can be configured to require validation via a certificate chain to speed up subsequent device authentications. Random private key generation is supported internally within the device to ensure that the private key can never be known outside of the device. The public key corresponding to a stored private key is always returned when the key is generated and it may optionally be computed at a later time. The ATECC608B can generate high-quality random numbers using its internal random number generator. This sophisticated function includes runtime health testing designed to ensure that the values generated from the internal noise source contain sufficient entropy at the time of use. The random number generator is designed to meet the requirements documented in the NIST 800-90A, 800-90B and 800-90C documents. These random numbers can be employed for any purpose, including as part of the device’s cryptographic protocols. Because each random number is ensured to be essentially unique from all numbers ever generated on this or any other device, their inclusion in the protocol calculation ensures that replay attacks (i.e., re-transmitting a previously successful transaction) will always fail. The ATECC608B also supports a standard hash-based challenge-response protocol to allow its use across a wide variety of additional applications. In its most basic instantiation, the system sends a challenge to the device, which combines that challenge with a secret key via the MAC command and then sends the response back to the system. The device uses a SHA-256 cryptographic hash algorithm to make that combination so that an observer on the bus cannot derive the value of the secret key. At the same time, the recipient can verify that the response is correct by performing the same calculation with a stored copy of the secret on the recipient’s system. There are a wide variety of variations possible on this symmetric challenge/response theme. ATECC608B Introduction © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 5

Electrical Characteristics

2.1 Absolute Maximum Ratings

Operating Temperature -40°C to +100°C Storage Temperature -65°C to +150°C Maximum Operating Voltage 6.0V DC Output Current 5.0 mA Voltage on any pin -0.5V to (VCC + 0.5V) -0.5V to (VCC + 0.5V) ESD Ratings: Human Body Model(HBM) ESD >4kV Charge Device Model(CDM) ESD >1kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2.2 Reliability

The ATECC608B is fabricated with Microchip’s high reliability CMOS EEPROM manufacturing technology. Table 2-1. EEPROM Reliability Parameter Min. Typ. Max. Units Write Endurance at +85°C (Each Byte) 400,000 — — Write Cycles Data Retention at +55°C 10 — — Years Data Retention at +35°C 30 50 — Years Read Endurance Unlimited Read Cycles

2.3 AC Parameters: All I/O Interfaces

Figure 2-1. AC Timing Diagram: All Interfaces Data CommWake tLIGNORE tHIGNORE Noise Suppresion tWLO tWHI ATECC608B

Electrical Characteristics

Table 2-2. AC Parameters: All I/O Interfaces Parameter Sym. Direction Min. Typ. Max. Units Conditions Power-Up Delay(2) tPU To Crypto Device 100 — — µs Minimum time between VCC > VCC min prior to start of tWLO. Wake Low Duration tWLO To Crypto Device 60 — — µs Wake High Delay to Data Comm tWHI To Crypto Device 1500 — — µs SDA should be stable high for this entire duration unless polling is implemented. SelfTest is not enabled at power-up. Wake High Delay when SelfTest is Enabled tWHIST To Crypto Device 20 — — ms SDA should be stable high for this entire duration unless polling is implemented. High-Side Glitch Filter at Active tHIGNORE_A To Crypto Device 45(1) — — ns Pulses shorter than this in width will be ignored by the device, regardless of its state when active. Low-Side Glitch Filter at Active tLIGNORE_A To Crypto Device 45(1) — — ns Pulses shorter than this in width will be ignored by the device, regardless of its state when active. Low-Side Glitch Filter at Sleep tLIGNORE_S To Crypto Device 15(1) — — µs Pulses shorter than this in width will be ignored by the device when in Sleep mode. Watchdog Time-out tWATCHDOG To Crypto Device 0.7 1.3 1.7 s Time from wake until device is forced into Sleep mode if Config.ChipMode[2] is 0. Notes: 1. These parameters are characterized, but not production tested. 2. The power-up delay will be significantly longer if power-on self test is enabled in the Configuration zone.

2.3.1 AC Parameters: Single-Wire Interface

Figure 2-2. AC Timing Diagram: Single-Wire Interface tSTART tZHI tZLO Logic Ø tSTART tBIT Logic 1 tSTART tTURNAROUND tSTART SDA Table 2-3. AC Parameters: Single-Wire Interface Unless otherwise specified, applicable from TA = -40°C to +100°C, VCC = +2.0V to +5.5V, CL = 100 pF. ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 7

Parameter Symbol Direction Min. Typ. Max. Unit Conditions Start Pulse Duration tSTART To Crypto Device 4.10 4.34 4.56 µs — From Crypto Device 4.60 6 8.60 µs — Zero Transmission High Pulse tZHI To Crypto Device 4.10 4.34 4.56 µs — From Crypto Device 4.60 6 8.60 µs — Zero Transmission Low Pulse tZLO To Crypto Device 4.10 4.34 4.56 µs — From Crypto Device 4.60 6 8.60 µs — Bit Time(1) tBIT To Crypto Device 37 39 — µs If the bit time exceeds tTIMEOUT, ATECC608B may enter Sleep mode. From Crypto Device 41 54 78 µs — Turn Around Delay tTURNAROUND From Crypto Device 64 96 131 µs ATECC608B will initiate the first low going transition after this time interval following the initial falling edge of the start pulse of the last bit of the transmit flag. To Crypto Device 93 — — µs After ATECC608B transmits the last bit of a group, the system must wait this interval before sending the first bit of a flag. It is measured from the falling edge of the start pulse of the last bit transmitted by ATECC608B. IO Timeout tTIMEOUT To Crypto Device 45 65 85 ms ATECC608B may transition to the Sleep mode if the bus is inactive longer than this duration. Note: 1. t START, tZLO, tZHI and tBIT are designed to be compatible with a standard UART running at 230.4 kBaud for both transmit and receive. The UART must be set to seven data bits, no parity and one Stop bit. ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 8

2.3.2 AC Parameters: I2C Interface

Figure 2-3. I2C Synchronous Data Timing SCL SDA IN SDA OUT tF tHIGH tLOW tLOW tR tAA tDH tBUF Table 2-4. AC Characteristics of I2C Interface(2) Unless otherwise specified, applicable over recommended operating range from TA = -40°C to +100°C, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF. Parameter Sym. Min. Max. Units SCL Clock Frequency fSCL 0 1 MHz SCL High Time tHIGH 400 — ns SCL Low Time tLOW 400 — ns Start Setup Time tSU.STA 250 — ns Start Hold Time tHD.STA 250 — ns Stop Setup Time tSU.STO 250 — ns Data In Setup Time tSU.DAT 100 — ns Data In Hold Time tHD.DAT 0 — ns Input Rise Time1 tR — 300 ns Input Fall Time1 tF — 100 ns Clock Low to Data Out Valid tAA 50 550 ns Data Out Hold Time tDH 50 — ns SMBus Time-Out Delay tTIMEOUT 25 75 ms Time bus must be free before a new transmission can start1 tBUF 500 — ns Notes: 1. Values are based on characterization and are not tested. 2. AC measurement conditions: – R L (connects between SDA and VCC): 1.2 kΩ (for VCC = +2.0V to +5.0V) – Input pulse voltages: 0.3V CC to 0.7VCC – Input rise and fall times: ≤ 50 ns – Input and output timing reference voltage: 0.5V CC ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 9

2.4 DC Parameters: All I/O Interfaces

Table 2-5. DC Parameters on All I/O Interfaces Parameter Sym. Min. Typ. Max. Units Conditions Ambient Operating Temperature TA -40 — +85 °C Standard Industrial Temperature Range -40 — +100 °C Extended Industrial Temperature Range Power Supply Voltage VCC 2.0 — 5.5 V — Active Power Supply Current ICC — 2 3 mA Waiting for I/O during I/O transfers or execution of non-ECC commands. Independent of Clock Divider value. — — 14 mA During ECC command execution. Clock divider = 0x0 — — 6 mA During ECC command execution. Clock divider = 0x5 — — 3 mA During ECC command execution. Clock divider = 0xD Idle Power Supply Current IIDLE — 800 — µA When device is in Idle mode, VSDA and VSCL < 0.4V or > VCC – 0.4 Sleep Current ISLEEP — 30 150 nA When device is in Sleep mode, VCC ≤ 3.6V, VSDA and VSCL < 0.4V or > VCC – 0.4, TA ≤ +55°C — — 2 µA When device is in Sleep mode. Over full VCC and temperature range. Output Low Voltage VOL — — 0.4 V When device is in Active mode, VCC = 2.5 to 5.5V Output Low Current IOL — — 4 mA When device is in Active mode, VCC = 2.5 to 5.5V, VOL = 0.4V Theta JA ƟJA — 166 — °C/W SOIC (SSH) — 173 — °C/W UDFN (MAH) — 146 — °C/W RBH

2.4.1 VIH and VIL Specifications

The input levels of the device will vary dependent on the mode and voltage of the device. The input voltage thresholds when in Sleep or Idle mode are dependent on the VCC level as shown in Figure 2-4. When in Sleep or Idle mode the TTLenable bit has no effect. Table 2-6. VIL, VIH on All I/O Interfaces (TTLenable = 0) Parameter Sym. Min. Typ. Max. Units Conditions Input Low Voltage VIL -0.5 — 0.5 V When device is active and TTLenable bit in Configuration memory is zero; otherwise, see above. Input High Voltage VIH 1.5 — VCC + 0.5 V When device is active and TTLenable bit in Configuration memory is zero; otherwise, see above. ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 10

Compatibility

3.1 Microchip ATECC608A

The ATECC608B is designed to provide an enhanced security profile over that of the ATECC608A while maintaining backwards compatibility. The following details the changes and enhancements to the device. No configuration bit fields have changed. Configurations defined for the ATECC608A will be functionally identical with the ATECC608B device. Corrections, Enhancements The following items have been corrected or enhanced in the ATECC608B device:

Two temperature ranges are now available: – Standard Industrial Temperature Range: -40 ℃ to +85℃ – Standard Industrial Temperature Range: -40 ℃ to +100℃
Operating at a low I 2C Frequency with multiple devices on the bus will no longer create a bus contention issue.
Modifications to Command Timings for Verify, SecureBoot, Lock and Read commands.
New Packaging Options: 3-Lead Contact Package and WLCSP for qualified customers. (Contact Microchip Sales for the WLCSP Option.)

3.2 Microchip ATECC508A

The ATECC608B is designed to be fully compatible with the ATECC508A devices with the limited exception of the functions listed below. If the ATECC608B is properly configured, software written for the ATECC508A will work with the ATECC608B without any required changes, again with the exception of the functions listed below. Note: Most elements of the configuration zone in the ATECC608B are identical in both location and value with the ATECC508A. However, the initial values that had been stored in the LastKeyUse field may need to be changed to conform to the new definition of those bytes which can be found in this document. That field contained the initial count for the Slot 15 limited use function which is supported in the ATECC608B via the monotonic counters. CAUTIONThe execution times of commands have changed between the ATECC608B and the ATECC508A. These changes will not cause an issue if polling has been implemented. If fixed timing has been used, this must be evaluated and updated as required. New Features in ATECC608B vs. ATECC508A

Secure boot function with IO encryption and authentication
KDF command, supporting PRF, HKDF, AES
AES command, including encrypt/decrypt
GFM calculation function for GCM AEAD mode of AES
Updated NIST SP800-90 A/B/C Random Number Generator
Flexible SHA/HMAC command with context save/restore
SHA command execution time significantly reduced
Volatile Key Permitting to prevent device transfer
Transport Key Locking to protect programmed devices during delivery
Counter Limit Match function
Ephemeral key generation in SRAM, also supported with ECDH and KDF
Verify command output can be validated with a MAC
Encrypted output for ECDH ATECC608B Compatibility © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 12

Added self test command, optional automatic power-on self test
Unaligned public key for built-in X.509 cert key validation
Optional power reduction at increased execution time
Programmable I 2C address after data (secret) zone lock Features Eliminated in ATECC608B vs. ATECC508A
HMAC command removed, replaced via new more powerful SHA command
OTP consumption mode eliminated, now read only
Pause command eliminated along with related Selector function in UpdateExtra
Slot 15 special limited use eliminated, replaced with standard monotonic counter limited use
SHA command no longer uses TempKey during the digest calculation and the result in TempKey is unchanged throughout the SHA operation. TempKey can however still be used to initialize the SHA for the HMAC_Start or to store the final digest.

3.3 Microchip ATSHA204A, ATECC108A

The ATECC608B is generally compatible with all ATSHA204/A and ATECC108/A devices. If properly configured, it can be used in most situations where these devices are currently employed. For ATSHA204A and ATECC108A compatibility restrictions, see the ATECC508A data sheet. ATECC608B Compatibility © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 13

Package Marking Information As part of Microchip’s overall security features, the part marking for all crypto devices is intentionally vague. The marking on the top of the package does not provide any information as to the actual device type or the manufacturer of the device. The alphanumeric code on the package provides manufacturing information and will vary with assembly lot. The packaging mark should not be used as part of any incoming inspection procedure. ATECC608B Package Marking Information © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 14

Package Drawings 5.1 8-lead SOIC

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-SWB Rev E Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC] Atmel Legacy Global Package Code SWB © 2017 Microchip Technology Inc. R 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

Microchip Technology Drawing No. C04-057-SWB Rev E Sheet 2 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. R Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H. 8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC] Atmel Legacy Global Package Code SWB ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 16

Microchip Technology Drawing C04-2057-SWB Rev E 8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC] BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. R Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN Atmel Legacy Global Package Code SWB ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 17

5.2 8-pad UDFN BA 0.10C0.10C (DATUM B) (DATUM A) CSEATINGPLANE N 2XTOP VIEW SIDE VIEW NOTE 1 N 0.10CAB 0.10CAB 0.10C 0.08C Microchip Technology Drawing C04-21355-Q4B Rev B Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote:8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ © 2017 Microchip Technology Inc. D E E2K L 8X be 0.10CAB0.05C A(A3) BOTTOM VIEW ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 18

For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: © 2017 Microchip Technology Inc. Number of TerminalsOverall Height Terminal WidthOverall WidthTerminal LengthExposed Pad Width Terminal ThicknessPitchStandoff UnitsDimension Limits A1A bE2 A3e LE N 0.50 BSC0.152 REF 1.200.350.18 0.500.00 0.250.401.30 0.550.02

3.00 BSC

1.400.450.30 0.600.05 MAX K -0.20 -Terminal-to-Exposed-Pad Overall LengthExposed Pad LengthDD21.402.00 BSC1.501.60 Microchip Technology Drawing C04-21355-Q4B Rev B Sheet 2 of 2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 19

RECOMMENDED LAND PATTERNDimension LimitsUnitsOptional Center Pad WidthOptional Center Pad LengthContact PitchY2X2 1.401.60MILLIMETERS0.50 BSCMINE MAX Contact Pad Length (X8)Contact Pad Width (X8)Y1X1 0.850.30 NOM CContact Pad Spacing2.90Contact Pad to Center Pad (X8)G10.33Thermal Via DiameterVThermal Via PitchEV 0.301.00 For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: © 2017 Microchip Technology Inc.Microchip Technology Drawing C04-23355-Q4B Rev B 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ Y1SILK SCREENX1E C EVG2 ØV Contact Pad to Contact Pad (X6)G20.20 ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 20

5.3 3 Lead Contact BA 0.10 C 0.10 C

0.10 C A B

(DATUM B) (DATUM A) C SEATING PLANE NOTE 1 TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Microchip Technology Drawing C04-21303 Rev A Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 3-Lead Contact Package (LAB) - 6.54x2.5 mm Body [Contact] Atmel Legacy Global Package Code RHB © 2017 Microchip Technology Inc. D ENOTE 1 e 3X b 3X L (K) (K) A 123 g f ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 21

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2017 Microchip Technology Inc. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-21303 Rev A Sheet 2 of 2 3-Lead Contact Package (LAB) - 6.54x2.5 mm Body [Contact] Atmel Legacy Global Package Code RHB Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Pitch Standoff Units Dimension Limits A b e L E N

2.00 BSC

2.10 1.60 0.45 0.00 1.70 2.20 0.50 0.02

2.50 BSC

2.30 1.80 0.55 0.05 MAX K 0.30 REFTerminal-to-Terminal Spacing Overall Length D 6.50 BSC f 0.400.30 0.50Package Edge to Terminal Edge g 0.150.05 0.25Package Edge to Terminal Edge ATECC608B Package Drawings © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 22

Revision History Revision Date Description A July 2020 Original Release. Based on ATECC608A Summary Data Sheet Rev B. DS40001977B ATECC608B

Revision History

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Embedded Solutions Engineer (ESE)
Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 24

Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X XX -X Device Package Temp Range I/O Type Tape and Reel Device: ATECC608B: Cryptographic Co-processor with Secure Hardware-based Key Storage Package Options(3) SS 8-Lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) MA 8-Pad 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat NoLead Package (UDFN) RB 3RB, 3-Lead 2x5 x 6.5mm Body, 2.0mm pin pitch, Contact Package (Sawn) Temperature Range H Standard Industrial Temperature Range: -40 ℃ to 85 ℃ V Extended Industrial Temperature Range: -40 ℃ to 100 ℃ I/O Type CZ Single Wire Interface DA I2C Interface Tape and Reel Options B Tube T Large Reel (Size varies by package type) S Small Reel (Only available for MA Package Type) Device Ordering Codes Temperature Range

Description

Standard Industrial Extended Industrial ATECC608B-SSHCZ-T ATECC608B-SSVCZ-T 8-Lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC), Single-Wire, Tape and Reel, 4,000 per Reel ATECC608B-SSHCZ-B ATECC608B-SSVCZ-B 8-Lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC), Single-Wire, Tube, 100 per Tube ATECC608B-SSHDA-T ATECC608B-SSVDA-T 8-Lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC), I2C, Tape and Reel, 4,000 per Reel ATECC608B-SSHDA-B ATECC608B-SSVDA-B 8-Lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC), I2C, Tube, 100 per Tube ATECC608B-MAHCZ-T ATECC608B-MAVCZ-T 8-Pad 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat NoLead Package (UDFN), Single-Wire, Tape and Reel, 15,000 per Reel ATECC608B-MAHDA-T ATECC608B-MAVDA-T 8-Pad 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat NoLead Package (UDFN), I2C, Tape and Reel, 15,000 per Reel ATECC608B-MAHCZ-S ATECC608B-MAVCZ-S Pad 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat NoLead Package (UDFN), Single-Wire, Tape and Reel, 3,000 per Reel ATECC608B-MAHDA-S ATECC608B-MAVDA-S 8-Pad 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat NoLead Package (UDFN), I2C, Tape and Reel, 3,000 per Reel ATECC608B-RBHCZ-T ATECC608B-RBVCZ-T Single-Wire, Tape and Reel, 5,000 per Reel, 3-Lead Contact Package ATECC608B-RBHCZ-B ATECC608B-RBVCZ-B Single-Wire, Tube, 56 per Tube, 3-Lead Contact Package ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 25

Notes: 1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small- form factor package availability, or contact your local Sales Office. 3. Die-on-Tape and Reel and WLCSP packages are available for qualified customers. Ordering codes for these packages are not shown in this table. Please contact Microchip sales for more information on these package options. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 26

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-6314-6 Quality Management System For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ATECC608B © 2020 Microchip Technology Inc. Summary Datasheet DS40002239A-page 27

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Summary

CryptoAuthentication™ Device Summary Data Sheet July 2020 Revision A

Description

CryptoAuthentication™ Device Summary Data Sheet July 2020 Revision A

Source title ATECC608B-SSHDA-B Datasheet(PDF) - Microchip Technology

Read ATECC608B-SSHDA-B online.

ATECC608B MICROCHIP | Alldatasheet

Document overview

Technical content

Features

Applications

1.1 Applications

1.2 Device Features

1.3 Cryptographic Operation

2.1 Absolute Maximum Ratings

2.2 Reliability

2.3 AC Parameters: All I/O Interfaces

Electrical Characteristics

2.3.1 AC Parameters: Single-Wire Interface

2.3.2 AC Parameters: I2C Interface

2.4 DC Parameters: All I/O Interfaces

2.4.1 VIH and VIL Specifications

3.1 Microchip ATECC608A

3.2 Microchip ATECC508A

3.3 Microchip ATSHA204A, ATECC108A

0.25 C A–B D

0.10 C A–B

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

1.27 BSCePitch

1.27 BSC

3.00 BSC

0.10 C A B

2.00 BSC

2.50 BSC

Revision History

Description

ATECC608B-SSHDA-B specifications and overview.

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