A3G18H500-04SR3_V01 NXP | Alldatasheet

Document overview

  • Manufacturer or author: NXP Semiconductors
  • PDF pages: 18

Technical content

Features

 High terminal impedances for optimal broadband performance  Advanced high performance in- -package Doherty  Able to withstand extremely high output VSWR and broadband operating conditions Document Number: A3G18H500- -04S Rev. 1, 08/2020 NXP Semiconductors Technical Data 1805–2200 MHz, 107 W AVG., 48 V AIRFAST RF POWER GaN TRANSISTOR A3G18H500- -04SR3 NI- -780S- -4L Figure 1. Pin Connections

42 RFoutB/VDSB

Table 1. Maximum Ratings Table 2. Thermal Characteristics Table 3. ESD Protection Characteristics Table 4. Electrical Characteristics(TA =2 5C unless otherwise noted)

  1. Functional operation above 225C has not been characterized and is not implied. Operation at TMAX (275C) reduces median time to failure

by an order of magnitude; operation beyond TMAX could cause permanent damage.

  1. RJC (FEA) must be used for purposes related to reliability and limitations on maximum junction temperature. MTTF may be estimated by

the expression MTTF (hours) = 10[A + B/(T + 273)], whereT is the junction temperature in degrees Celsius,A = –10.3 andB = 8260.

  1. Each side of device measured separately.

Table 4. Electrical Characteristics(TA =2 5C unless otherwise noted)(continued) Table 5. Ordering Information

  1. Part internally input matched.
  2. Measurements made with device in an asymmetrical Doherty configuration.
  3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W- -CDMA single- -carrier input signal where

output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.

  1. Set gate voltage VGSA and VGSB to –5 V.
  2. Set drain voltage VDSA and VDSB to nominal supply voltage (+48 V).
  3. Increase VGSA (carrier side) until IDQA current is attained.
  4. Increase VGSB (peaking side) to target bias voltage.
  5. Apply RF input power to desired level.
  6. Adjust drain voltage VDSA and VDSB to 0 V. Allow adequate time

for drain voltage to reduce to 0 V from external drain capacitors.

Figure 2. A3G18H500- -04SR3 Test Circuit Component Layout Table 6. A3G18H500- -04SR3 Test Circuit Component Designations and Values

Pout, OUTPUT POWER (WATTS) AVG. Figure 6. Single- -Carrier W- -CDMA Power Gain, Drain Figure 7. Broadband Frequency Response

12 GAIN (dB)

1840 MHz 1880 MHz

1805 MHz

1840 MHz

1880 MHz1840 MHz

1880 MHz

3.84 MHz Channel Bandwidth

Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane. Table 8. Carrier Side Load Pull Performance — Maximum Efficiency Tuning (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. source = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane.

Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane. Table 10. Peaking Side Load Pull Performance — Maximum Efficiency Tuning (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. source = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane.

Table 11. Carrier Side Load Pull Performance — Maximum Power Tuning (1) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane. Table 12. Carrier Side Load Pull Performance — Maximum Efficiency Tuning (1) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane.

Table 13. Peaking Side Load Pull Performance — Maximum Power Tuning (1) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane. Table 14. Peaking Side Load Pull Performance — Maximum Efficiency Tuning (1) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output ofthe device at the package reference plane.

PACKAGE INFORMATION

PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS Refer to the following resources to aid your design process. Application Notes  AN1908: Solder Reflow Attach Method for High Power RF Devices in Air Cavity Packages  AN1955: Thermal Measurement Methodology of RF Power Amplifiers Software  .s2p File Development Tools  Printed Circuit Boards

REVISION HISTORY

The following table summarizes revisions to this document. Revision Date Description

0 May 2017  Initial release of data sheet

1 Aug. 2020  Changed upper frequency range from 1880 MHz to 2200 MHz to highlight part performance up to 2200 MHz, p. 1  Biasing sequence note: updated to reflect latest biasing sequence recommendations, p. 3  Tables 11–14, Load Pull Performance: added Carrier Side and Peaking Side load pull performance tables showing P3dB performance across the 1800- -2200 MHz band, pp. 13–14

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