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Technical content
Features
- ISO 26262 Functional Safety Ready
- Supply Voltage up to 40V
- Operating Voltage VVS =5 V t o 2 8 V
- Very Low Supply Current - Sleep mode: Typically 9 A - Fail-Safe mode: Typically 80 A - Normal mode: Typically 250 A
- Fully Compatible with 3.3V and 5V Devices
- LIN Physical Layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2
- Wake-Up Capability through LIN bus (100 s Dominant)
- External Wake Up through WKin pin (100 s Low Level)
- INH Output to Control an External Voltage Regulator or to Switch the Commander Pull-Up
- Wake-Up Source Recognition
- TXD Time-Out Timer
- Bus Pin is Overtemper ature and Short-Circuit Protected vs. GND and Battery
- Advanced EMC and ESD Performance
- Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.3”
- Interference and Damage Protection according to ISO7637
- Qualified according to AEC-Q100 and AEC-Q006
- Package: 8-Lead VDFN, 8-Lead SOIC, with Wettable Flanks (Moisture Sensitivity Level 1)
Description
The ATA663211 device is a fully integrated LIN transceiver designed in compliance with the LIN interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in convenience electronics, for example, in vehicles. Improved slope control at the LIN bus ensures data communication up to 20 Kbaud. Sleep mode guarantees minimal current consumption even in the case of a floating bus line or a short circuit on the LIN bus to GND. Package Types Note: The current LIN standards use the terminology "Master" and "Slave”. The LIN standard groups have decided that the terms "Commander" and "Responder" will be used in future. RXD EN WKin TXD INH VS GND LIN EP ATA663211 8-Lead VDFN ATA663211 8-Lead SOIC WKin EN TXD VS LIN
5 GND
*Includes Exposed Thermal Pad (EP); see Table 1-4. LIN Transceiver
DS20006191D-page 2 2019-2021 Microchip Technology Inc. ATA663211 Block Diagram 3WKin 4TXD 1RXD VS GND5 Short-circuit and overtemperature protection Control Unit with Mode Selection Sleep Mode Normal/ Fail-safe Mode RF-Filter INH LIN VS7 TXD Time-out Timer Slew rate control Wake-up bus timer ATA663211 Receiver VS Wake-up Timer EN
2019-2021 Microchip Technology Inc. DS20006191D-page 3 ATA663211
1.0 FUNCTIONAL DESCRIPTION
1.1 Physical Layer Compatibility
Since the LIN physical layer is independent of higher LIN layers (for example, LI N protocol layer), all nodes with a LIN physical layer acco rding to revision 2.x can be mixed with LIN physical layer nodes based on earlier versions (for instance, LIN 1.0, LIN 1.1,LIN 1.2, LIN 1.3) without any restrictions.
1.2 Operating Modes
FIGURE 1-1: ATA663211 OPERATING MODES TABLE 1-1: ATA663211 OPERATING MODES Operating Mode Transceiver INH LIN TXD RXD Fail-Safe OFF ON Recessive Signaling fail-safe sources (see Table 1-2) Normal ON ON TXD-dependent Follows data transmission Sleep/Unpowered OFF OFF Recessive Low High Ohmic Note 1: Condition f is valid for VS ramp up; at VS ramp down condition e is valid instead of f. EN = 1 Go to sleep command EN = 0 b (c + g) & f EN = 0 e a b & f Fail-safe Mode Communication: OFF Wake-up Signaling Undervoltage Signaling INH output switched ON Normal Mode Communication: ON INH output switched ON Sleep Mode Communication: OFF INH output switched OFF Unpowered Mode All circuitry OFF EN = 1 & f a: VVS > VVS_th_U_F_up (2.4V) b: VVS < VVS_th_U_)Bdown (1.9V) c: Bus wake-up event (LIN) d: - e: VVS < VVS_th_N_F_down (3.9V) f: VVS > VVS_th_F_N_up (4.9V) g: Local WAKE event (WKin) 7;' I
DS20006191D-page 4 2019-2021 Microchip Technology Inc.
1.2.1 NORMAL MODE
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x.
1.2.2 SLEEP MODE
A falling edge at EN switches the IC into Sleep mode. While in Sleep mode, the transmission path is disabled and the device is in Low- Power mode. Supply current from VBAT is typically 9 A. In Sleep mode the INH pin is switched off. The internal termination resistor between the LIN pin and VS pin is disabled. Only a weak pull-up current (typical 10 A) between the LIN pin and VS pin is present. Sleep mode can be activated independently from the actual level on the LIN or WKin pin. If the TXD pin is short-circuited to GND, it is possible to switch to Sleep mode though EN after t > t dom.
1.2.3 FAIL-SAFE MODE
The device automatically switches to Fail-Safe mode at system power-up or after a wake-up event. The INH output is switched on and the LIN transceiver is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal mode. During Fail-Safe mode the TXD pin is an output, and, together with the RXD output pin, signals the fail-safe source. If the device enters Fail-Safe mode coming from the Normal mode (EN = 1) due to a VS undervoltage condition (V VS <V VS_th_N_F_down), it is possible to switch into Sleep mode by a falling edge at the EN input. With this feature, the current consumption is further reduced. A wake-up event from Sleep mode is signaled to the microcontroller using the RX D pin and the TXD pin. A VS undervoltage condition is also signaled at these two pins. The coding is shown in Table 1-2.
1.3 Wake-Up Scenarios from Sleep
1.3.1 REMOTE WAKE UP THROUGH LIN
1.3.1.1 Remote Wake-up from Sleep Mode
A voltage lower than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin, followed by a dominant bus level maintained for a certain period of time (>t bus) and following a rising edge at the LIN pin result in a remote wake-up request and the device switches to Fail-Safe mode. The INH pin is activated (switches to VS) and the internal LIN termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD and interrupts the microcontroller.
1.3.2 LOCAL WAKE UP THROUGH WKIN
A falling edge at the WKin pin followed by a low level maintained for a certain period of time (>tWKin) result in a local wake-up request and the device switches to Fail-Safe mode. The INH pin is activated (switches to VS) and the internal LIN termination resistor is switched on. The local wake-up request is indicated by a low level at the TXD pin and a high level at the RXD pin, generating an interrupt for the microcontroller. Even when the WKin pin is low, it is possible to switch to Sleep mode via the EN pin. In this case, the wake-up signal has to be switched to high >10 s before the negative edge at WKin starts a new local wake-up request. TABLE 1-2: SIGNALING IN FAIL-SAFE MODE Fail-Safe Sources TXD RXD LIN wake-up (LIN pin) Low Low Local wake-up (WKin pin) Low High VSth (battery) undervoltage detection VVS <3 . 9 V High Low Note 1: Assuming an external pull-up resistor (typical 5 k) has been added on pin TXD to the power supply of the microcontroller.
DS20006191D-page 6 2019-2021 Microchip Technology Inc.
1.3.3 WAKE-UP SOUR CE RECOGNITION
The device can distinguish between different wake-up sources. The wake-up source can be read on the TXD and RXD pin in Fail-Safe mode according to Table 1-3, if an external pull-up resistor (typically 5 k) has been added on pin TXD to the power supply of the microcontroller. These flags are reset immediately if the microcontroller sets pin EN to high and the IC is in Normal mode.
1.4 Behavior under Low Supply
After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the block capacitor used in the application (see Figure “ATA663211 Block Diagram”). If V VS is higher than the minimum VS operation threshold VVS_th_U_F_up, the IC mode changes from Unpowered mode to Fail-Safe mode, the INH output is switched on and the LIN transceiver can be activated. If, during Sleep mode, the voltage level of V VS drops below the under-voltage detection threshold V VS_th_N_F_down (typically 4.3V), the operation mode is not changed and no wake up is possible. Only if the supply voltage on the VS pin drops below the VS operation threshold V VS_th_U_F_down (typically 2.05V), does the IC switch to Unpowered mode. If, during Normal mode, the voltage level on the VS pin drops below the VS undervoltage detection threshold V VS_th_N_F_down (typically 4.3V), the IC switches to Fail-Safe mode. This means that the LIN transceiver is disabled in order to avoid malfunctions or false bus messages. If the supply voltage V VS drops further below the VS operation threshold V VS_th_U_F_down (typically 2.05V), the IC switches to Unpowered mode and the INH output switches off. TABLE 1-3: SIGNALING IN FAIL-SAFE MODE Fail-Safe Sources TXD RXD LIN wake up (LIN pin) Low Low Local wake up (WKin pin) Low High VSth (battery) undervoltage detection (VVS < 3.9V) High Low Note 1: Assuming an external pull-up resistor (typical 5 k) has been added on pin TXD to the power supply of the microcontroller.
2019-2021 Microchip Technology Inc. DS20006191D-page 7 ATA663211
1.5 Pin Descriptions
The descriptions of the pins are listed in Table 1-4.
1.5.1 OUTING PIN (RXD)
In Normal mode, this pin re ports the state of the LIN bus to the microcontroller. LIN high (Recessive state) is indicated by a high level at RXD; LIN low (Dominant state) is indicated by a low level at RXD. The output is an open drain; it is compatible with a 3.3V or 5V power supply. The AC characteristics are defined by an external pull-up resistor of 4.7 k to 5V and a load capacitor of 20 pF. In Unpowered mode, RXD is switched off.
1.5.2 ENABLE INPUT PIN (EN)
The enable input pin controls the operating mode of the device. If EN is high, the circuit is in Normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. If EN is switched to low while TXD is still high, the device is forced to Sleep mode. This means that no data transmission is possible and current consumption is reduced to IVSsleep typical 9 A. The EN pin provides a pull-down resistor to force the transceiver into Recessive mode if EN is disconnected.
1.5.3 WKIN PIN
This pin is a high-voltage input used for waking up the device from Sleep mode. It is usually connected to an external switch in the application to generate a local wake up. A pull-up current source with typically 10 A is implemented. The voltage threshold for a wake-up signal is typically 2V below the V VS voltage. If a local wake up is not needed in the application, the WKin pin can be connected directly to the VS pin.
1.5.4 INPUT/OUTPUT (TXD)
In Normal mode, the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the Recessive state. If the TXD pin stays at GND level while switching into Normal mode, it must be pulled to high level longer than 10 s before the LIN driver can be activated. This feature prevents the bus line from being accidentally driven to Dominant state after Normal mode has been activated (also in case of a short circuit at TXD to GND). During Fail-Safe mode, this pin is used as output and signals the fail-safe source. The TXD pin provides a pull-down resistor in order to have a defined level if TXD is disconnected. An internal timer prevents the bus line from being driven permanently in the Dominant state. If TXD is forced to low longer than t dom > 20 ms, the LIN bus driver is switched to the Recessive state. Nevertheless, when switching to Sleep mode, the actual level at the TXD pin is relevant. To reactivate the LIN bus driver, switch TXD to high (>10 s).
1.5.5 GROUND PIN (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of VVS. TABLE 1-4: PIN FUNCTIONING TABLE Pin Symbol Function
1 RXD Receive data output
2 EN Enables Normal mode if the input is high
3 WKin High-voltage input for local wake-up requ est. If not needed, connect directly to VS
4 TXD Transmit data input
5 GND Ground, heat slug
6 LIN LIN bus line input/output
7 VS Supply voltage
8 INH Battery-related high-side switch output for controlling an external voltage regulator or to
switch off the LIN Commander pull-up resistor; switched on after a wake-up request Backside EP Heat slug, internally connected to the GND pin (only for the VDFN8 package)
DS20006191D-page 8 2019-2021 Microchip Technology Inc.
1.5.6 BUS PIN (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from -27V to +40V. This pin exhibits no reverse current from the LI N bus to VS, even in the event of a GND shift or V Bat disconnection. The LIN receiver thresholds comply with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled. During a short circuit at LIN to VBat, the output limits the output current to I BUS_LIM. Due to the power dissipation, the chip temperature exceeds Toff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During a short circuit from LIN to GND, the IC can be switched into Sleep mode and even in this case the current consumption is lower than 100 A. If the short circuit disappears, the IC starts with a remote wake up. The reverse current is <2 A at pin LIN during loss of VBat. This is optimal behavior for bus systems where some nodes are supplied from battery or ignition.
1.5.7 SUPPLY PIN (VS)
LIN operating voltage is VS = 5V to 28V. Undervoltage detection is implemented to disable transmission if VS falls below typical 4.5V, in order to avoid false bus messages. After switching on V VS, the IC starts in Fail-Safe mode and the INH output is switched on. The supply current in Sleep mode is typically 9 A.
1.5.8 INHIBIT OUTPUT PIN (INH)
This pin is used to control an external voltage regulator or to switch the LIN Commander pull-up resistor ON/OFF in case the device is used in a Commander node. The inhibit pin provides an internal switch toward the VS pin which is protected by temperature monitor- ing. If the device is in normal or Fail-Safe mode, the inhibit high-side switch is turned on. When the device is in Sleep mode, the inhibit switch is turned off, thus dis- abling the voltage regulator or other connected external devices. A wake-up event on the LIN bus or at the WKin pin switches the INH pin to t he VS level. After a system power-up (V VS rises from zero), the INH pin switches to the VVS level automatically.
1.6 Typical Applications
FIGURE 1-4: ATA663211 TYPICAL APPLICATION CIRCUIT ATA663211 DFN8 3 x 3 RXD EN (xternal wake- switch WKin TXD INH VCC Microcontroller VCC VBAT &RPPDQGHU node pull up VS LIN GND 100nFC2 220pF 10μF/50V 2.2μF 100nF LIN GND GND 12V 4.7kΩ 10kΩ 2.7kΩ 1kΩ
2019-2021 Microchip Technology Inc. DS20006191D-page 9 ATA663211
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings † Logic Pins: Voltage Levels (RXD, TXD, EN, NRES) (V LIN INH WKin voltage levels DC Voltage (V ESD according to IBEE LIN EMC; test specification 1.0 following IEC 61000-4-2 ESD HBM following STM5.1 with 1.5 k/100 pF Virtual Junction Temperature (T † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not in tended. Exposure to maximum rating conditions for extended periods may affect device reliability.
DS20006191D-page 10 2019-2021 Microchip Technology Inc.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise specified all values refer to GND pins, 5V < VVS < 28V, -40°C < TVJ < 150°C. No. Parameters Symbol Min. Typ. Max. Unit Conditions
1 VS Pin
1.1 Nominal DC
VVS 51 3 . 5 2 8 V 1.3 Supply Current in Sleep mode IVSsleep 39 1 5 A Sleep mode VLIN >V VS -0 . 5 V VVS < 14V, T = 27°C (Note 1) IVSsleep 31 1 1 8 A Sleep mode VLIN >V VS –0 . 5 V VVS < 14V IVSsleep_short 20 50 100 A Sleep mode, V LIN =0 V bus shorted to GND VV VS < 14V
1.4 Supply Current
IVSrec 150 250 320 A Bus recessive VVS < 14V 1.5 Supply Current in Normal Mode IVSdom 200 700 950 A Bus dominant (internal LIN pull-up resistor active) V VS < 14V
1.6 Supply Current
IVSfail 40 80 110 A Bus recessive VVS < 14V 1.7 VS Undervoltage Threshold (switching from Normal to Fail-Safe mode) VVS_th_N_F_down 3.9 4.3 4.7 V Decreasing supply voltage VVS_th_F_N_up 4.1 4.6 4.9 V Increasing supply voltage 1.8 VS Undervoltage Hysteresis VVS_hys_F_N 0.1 0.25 0.4 V 1.9 VS Operation Threshold (switching to Unpowered mode) VVS_th_U_F_down 1.9 2.05 2.3 V Switch to Unpowered mode VVS_th_U_F_up 2.0 2.25 2.4 V Switch from Unpowered to Fail-Safe mode 1.10 VS Undervoltage Hysteresis VVS_hys_U 0.1 0.2 0.3 V
2 RXD Output Pin (Open Drain)
2.1 Low-Level Output Sink Capability VRXDL — 0.2 0.4 V Normal mode, VLIN =0 V , IRXD =2m A 2.3 High-Level Leakage Current IRXDH -3 — +3 A Normal mode VLIN =V VS, VRXD =5 V
3 TXD Input/Output Pin
3.1 Low-Level Voltage
VTXDL -0.3 — +0.8 V 3.2 High-Level Voltage Input VTXDH 2— 5 . 5 V 3.5 Pull-Down Resistor R TXD 150 200 300 k VTXD =5 V 3.6 Low-level Leakage Current ITXD -3 — +3 AV TXD =0 V Note 1: 100% correlation tested. 2: Characterized on samples. 3: Design parameter.
2019-2021 Microchip Technology Inc. DS20006191D-page 11 ATA663211 3.7 Low-Level Output Sink Current at Wake-Up Request I TXD 2 2.5 8 mA Fail-Safe mode VTXD =0 . 4 V
4 EN Input Pin
4.1 Low-Level
VENL -0.3 — +0.8 V
4.2 High-Level
VENH 2— 5 . 5 V
4.3 Pull-Down Resistor R EN 50 125 200 k VEN =5 V
4.4 Low-Level
IEN -3 — +3 AV EN =0 V
6 WKin Input Pin
6.1 High-Level Input
VWKinH V VS –1 V — V VS +0 . 3 V V
6.2 Low-Level Input
VWKinL -1 — V VS – 3.3V V Initializes a wake-up signal
6.3 WKin Pull-Up Current I WKIN -30 -10 AV VS < 28V, VWKin =0 V
6.4 High-Level Leakage
IWKINL -5 — +5 AV VS = 28V, VWKin =2 8 V 6.5 Debounce Time of Low Pulse for Wake up via WKin tWKin 50 100 150 sV WKin =0 V
7 INH Output Pin
7.1 Switch on Resistance
RDSON,INH —1 22 5 Normal or Fail-Safe mode IINH = -15 mA
7.2 Leakage Current I LEAK,INH -3 — +3 A Transceiver in Sleep mode,
VINH = 0V/28V, VVS =2 8 V
7.3 High-Level Voltage V INH VVS –
0.375 —V VS V Normal or Fail-Safe mode IINH = -15 mA
10 LIN Bus Driver: Bus Load Conditions:
Load 1 (small): 1 nF, 1 k; Load 2 (large): 10 nF, 500; External Pull-up RRXD =4 . 7k ; CRXD =2 0p F , Load 3 (medium): 6.8 nF, 660 characterized on samples, 12.7 and 12.8 specifies the timing parameters for proper operation at 20 kb/s and 12.9 and 12.10 at 10.4 kb/s 10.1 Driver Recessive Output Voltage VBUSrec 0.9 * VVS —V VS V Load1/Load2 10.2 Driver Dominant Voltage V_LoSUP —— 1 . 2 V V VS =7 V Rload = 500 10.3 Driver Dominant Voltage V_HISUP —— 2 V V VS = 18V Rload = 500 10.4 Driver Dominant Voltage V_LoSUP_1k 0.6 — — V V VS =7 V Rload = 1000 10.5 Driver Dominant Voltage V_HISUP_1K 0.8 — — V V VS = 18V Rload = 1000 10.6 Pull-Up Resistor to VS R LIN 20 30 47 k The serial diode is mandatory ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified all values refer to GND pins, 5V < VVS < 28V, -40°C < TVJ < 150°C. No. Parameters Symbol Min. Typ. Max. Unit Conditions Note 1: 100% correlation tested. 2: Characterized on samples. 3: Design parameter.
DS20006191D-page 12 2019-2021 Microchip Technology Inc. 10.7 Voltage Drop at the Serial Diodes VSerDiode 0.4 — 1.0 V In pull-up path with R LIN ISerDiode =1 0m A (Note 3) 10.8 LIN Current Limitation VBUS =V BAT_MAX IBUS_LIM 40 120 200 mA 10.9 Input leakage current at the receiver including pull-up resistor as specified IBUS_PAS_dom -1 -0.35 — mA Input leakage current driver off VBUS=0 V VBAT = 12V 10.10 Leakage Current LIN Recessive IBUS_PAS_rec —1 02 0 AD r i v e r o f f 8V < VBAT< 18V 8V < VBUS < 18V VBUS ≥ VBAT 10.11 Leakage current when control unit is disconnected from ground. Loss of local ground must not affect communication in the residual network I BUS_NO_gnd -10 +0.5 +10 AG N D Device =V VS VBAT= 12V 0V < VBUS< 18V 10.12 Leakage current at disconnected battery. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition. I BUS_NO_bat —0 . 1 2 AV BAT disconnected VSUP_device =G N D 0V < VBUS < 18V 10.13 Capacitance on LIN pin to GND CLIN — — 20 pF ( Note 3)
11 LIN Bus Receiver
11.1 Center of Receiver Threshold VBUS_CNT 0.475 * VVS 0.5 * VS 0.525 * V VS VV BUS_CNT = (Vth_dom + Vth_rec)/2
11.2 Receiver Dominant
VBUSdom -27 — 0.4 * VS V V EN =5 V
11.3 Receiver Recessive
VBUSrec 0.6 * VVS —4 0 V V EN =5 V 11.4 Receiver Input Hysteresis VBUShys 0.028 * VVS 0.1 * VS 0.175 * V VS VV hys = Vth_rec -V th_dom 11.5 Pre-Wake Detection LIN High-Level Input Voltage VLINH VVS –2 V — V VS +0 . 3 V V 11.6 Pre-Wake Detection LIN Low-Level Input Voltage VLINL -27 — V VS – 3.3V V Activates the LIN receiver ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified all values refer to GND pins, 5V < VVS < 28V, -40°C < TVJ < 150°C. No. Parameters Symbol Min. Typ. Max. Unit Conditions Note 1: 100% correlation tested. 2: Characterized on samples. 3: Design parameter.
2019-2021 Microchip Technology Inc. DS20006191D-page 13 ATA663211
12 Internal timers
12.1 Dominant time for wake up via LIN bus tbus 50 100 150 s VLIN =0 V 12.2 Time delay for mode change from Fail-Safe into Normal mode via EN pin tnorm 51 5 2 0 s VEN =5 V 12.3 Time delay for mode change from Normal mode to Sleep mode via EN pin tsleep 51 5 2 0 s VEN =0 V 12.4 Time delay for mode change from Sleep mode to Normal mode via EN pin ts_n — 150 300 s VEN =5 V 12.5 TXD dominant time-out time tdom 20 40 60 ms VTXD =0 V 12.7 Duty Cycle 1 D1 0.396 — — — THRec(max) = 0.744 x VVS THDom(max) = 0.581 x VVS VVS =7 . 0 Vt o1 8 V tBit =5 0 s D1 = tbus_rec(min)/(2 x tBit) 12.8 Duty Cycle 2 D2 — — 0.581 — THRec(min) = 0.422 x VVS THDom(min) = 0.284 x V VS VVS =7 . 6 Vt o1 8 V tBit =5 0 s D2 = tbus_rec(max)/(2 x tBit) 12.9 Duty Cycle 3 D3 0.417 — — — THRec(max) = 0.778 x VVS THDom(max) = 0.616 x VVS VVS =7 . 0 Vt o1 8 V tBit =9 6µ s D3 = tbus_rec(min)/(2 x tBit) 12.10 Duty Cycle 4 D4 — — 0.590 — THRec(min) = 0.389 x VVS THDom(min) =0 . 2 5 1xVVS VVS =7 . 6 Vt o1 8 V tBit =9 6µ s D4 = tbus_rec(max)/(2 x tBit) 12.11 Slope time falling and rising edge at LIN tSLOPE_fall tSLOPE_rise 3.5 — 22.5 s VVS = 7.0V to 18V
13 Receiver electrical AC parameters of the LIN physical layer
LIN receiver, RXD load conditions: CRXD =2 0p F , RRXD =4 . 7k 13.1 Propagation delay of receiver trx_pd —— 5 s VVS = 7.0V to 18V trx_pd =m a x ( trx_pdr, trx_pdf) 13.2 Symmetry of receiver propagation delay rising edge minus falling edge trx_sym -2 — +2 s VVS = 7.0V to 18V trx_sym = trx_pdr -t rx_pdf ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified all values refer to GND pins, 5V < VVS < 28V, -40°C < TVJ < 150°C. No. Parameters Symbol Min. Typ. Max. Unit Conditions Note 1: 100% correlation tested. 2: Characterized on samples. 3: Design parameter.
DS20006191D-page 14 2019-2021 Microchip Technology Inc. FIGURE 2-1: DEFINITION OF BUS TIMING CHARACTERISTICS TEMPERATURE SPECIFICATIONS 8-LEAD VDFN Parameters Sym. Min. Typ. Max. Unit Thermal resistance virtual junction to exposed thermal pad RthvJC —1 0— K / W Thermal resistance virtual junction to ambient, where exposed thermal pad is soldered to the PCB, according to JEDEC RthvJA —5 0— K / W Thermal shutdown T off 150 165 180 °C Thermal shutdown hysteresis T hys —1 0—° C TEMPERATURE SPECIFICATIONS 8-LEAD SOIC Parameters Sym. Min. Typ. Max. Unit Thermal resistance virtual junction to ambient, with a heat sink at GND (pin 5) on PCB (fused lead frame to pin 5) RthvJA —8 0— K / W Thermal shutdown T off 150 165 180 °C Thermal shutdown hysteresis T hys 51 0 2 0 ° C TXD (Input to transmitting node) VS (Transceiver supply of transmitting node) RXD (Output of receiving node1) RXD (Output of receiving node2) LIN Bus Signal Thresholds of receiving node1 Thresholds of receiving node2 tBus_rec(max) trx_pdr(1) trx_pdf(2)trx_pdr(2) trx_pdf(1) tBus_dom(min) tBus_dom(max) THRec(max) THDom(max) THRec(min) THDom(min) tBus_rec(min) tBit tBittBit
2019-2021 Microchip Technology Inc. DS20006191D-page 15 ATA663211
3.0 PACKAGING INFORMATION
Package Marking Information XXXXXX 8-Lead VDFN (3x3 mm) PIN 1 NNN 663211 Example ATA663211 PIN 1 256 Atmel YWW 8-Lead SOIC (3.90 mm) XXXXXX YYWWNNN Atmel 841 Example ATA663211 663211 1841256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.
- , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) symbol may not be to scale.
DS20006191D-page 16 2019-2021 Microchip Technology Inc.
0.25 C A–B D
C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-OA Rev F Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b
0.10 C A–B
H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D
2019-2021 Microchip Technology Inc. DS20006191D-page 17 ATA663211 Microchip Technology Drawing No. C04-057-OA Rev F Sheet 2 of 2 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height
1.27 BSCePitch
protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.
DS20006191D-page 18 2019-2021 Microchip Technology Inc. RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-OA Rev F BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS
1.27 BSC
E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
2019-2021 Microchip Technology Inc. DS20006191D-page 19 ATA663211 BA 0.10 C 0.10 C
0.10 C A B
0.05 C (DATUM B) (DATUM A) C SEATING PLANE N TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Microchip Technology Drawing C04-21358 Rev C Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy YCL D E NOTE 1 (A3) A N NOTE 1 L K e 8X b A A
DS20006191D-page 20 2019-2021 Microchip Technology Inc. Microchip Technology Drawing C04-21358 Rev C Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N
0.65 BSC
0.203 REF
1.50 0.35 0.25 0.80 0.00 0.30 0.40 1.60 0.90 0.035
3.00 BSC
1.70 0.45 0.35 1.00 0.05 MAX K- 0.20 - REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Terminal-to-Exposed-Pad 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy YCL Overall Length Exposed Pad Length D D2 2.30 2.40 2.50 SECTION A–A PARTIALLY PLATED Wettable Flank Step Cut Depth A4 0.10 - 0.19 E3 --0 . 0 8 5Wettable Flank Step Cut Width
2019-2021 Microchip Technology Inc. DS20006191D-page 21 ATA663211 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 2.50 1.70 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.80 0.35 Microchip Technology Drawing C04-23358 Rev C NOM 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] CContact Pad Spacing 3.00 Contact Pad to Center Pad (X8) G1 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks C E EV ØV SILK SCREEN EVX2 Pin 1 Index Chamfer CH 0.20 Contact Pad to Contact Pad (X6) G2 0.20 CH
DS20006191D-page 22 2019-2021 Microchip Technology Inc. NOTES:
2019-2021 Microchip Technology Inc. DS20006191D-page 23 ATA663211 APPENDIX A: REVISION HISTORY Revision D (June 2021) The following is the list of modifications:
- The current LIN standards use the terminology "Master" and "Slave”. The LIN standard groups have decided that the terms "Commander" and "Responder" will be used in future.
- Updated the VDFN8 package drawing.
- Minor text updates. Revision C (July 2020)
- Parameter 13.1 in chapter 2.0 “Electrical Characteristics” updated
- Updated the marking information for the SOIC package in the “Package Marking Information” section Revision B (April 2020)
- “Package Marking Information” updated
- Minor editorial changes Revision A (April 2019)
- Original release of this document
- Minor text updates
- This document replaces Atmel – 9359D-AUTO-10/16
DS20006191D-page 24 2019-2021 Microchip Technology Inc. NOTES:
2019-2021 Microchip Technology Inc. DS20006191D-page 25 ATA663211 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX PackageDevice Device: ATA663211 Package: GA = 8-Lead SOIC GB = 8-Lead VDFN Tape and Reel Option: Q = 330 mm diameter Tape and Reel (1) Package Directives Classification: W = Package according to RoHS (1) Examples: a) ATA663211-GAQW 8-Lead SOIC, Tape and Reel package according to RoHS b) ATA663211-GBQW 8-Lead VDFN, Tape and Reel package according to RoHS Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: RoHS compliant; maximum concentration value of 0.09% (900 ppm) for Bromine (Br) and Chlorine (Cl) and less than 0.15% (1500 ppm) total Bromine (Br) and Chlorine (Cl) in any homogeneous material. Maximum concentration value of 0.09% (900 ppm) for Antimony (Sb) in any homogeneous material. X Tape and Reel Option – [X] Package Directives Classification
DS20006191D-page 26 2019-2021 Microchip Technology Inc. NOTES:
2019-2021 Microchip Technology Inc. DS20006191D-page 27 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ens ure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectu al property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP , SimpliPHY , SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019-2021, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-8328-1 Note the following details of the code protection feature on Microchip devices:
- Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secu re when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights.
- Microchip is willing to work with any customer who is concerned about the integrity of its code.
- Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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