ATA663201 MICROCHIP | Alldatasheet
Document overview
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Technical content
Features
- ISO 26262 Functional Safety Ready
- Supply Voltage up to 40V
- Operating Voltage VVS = 5V to 28V
- Supply Current - Sleep mode: typically 9 μA - Silent mode: typically 47 μA - Very low current consumption at low supply voltages (2V < VVS < 5.5V): typically 130 μA
- Linear Low-Drop Voltage Regulator, 85 mA Current Capability: - MLC (multi-layer ceramic) capacitor with 0 Ω ESR - Normal, Fail-Safe and Silent mode - ATA663254: V VCC =5 . 0 V , ± 2 % - ATA663231: V VCC =3 . 3 V , ± 2 %
- Sleep Mode: VCC is Switched Off
- A c t i v e M o d e : - ATA663203: V VCC =5 . 0 V , ± 2 % - ATA663201: V VCC =3 . 3 V , ± 2 %
- VCC Undervoltage Detection with Open Drain Reset Output (NRES, 4 ms Reset Time)
- Voltage Regulator is Short-Circuit and Overtemperature Protected
- LIN Physical Layer According to LIN 2.0, 2.1, 2.2, 2.2A, ISO 17987-4 and SAEJ2602-2
- Wake-Up Capability via LIN Bus (100 μs Dominant)
- Wake-Up Source Recognition
- TXD Time-Out Timer
- Bus Pin is Overtemperature and Short-Circuit Protected Versus GND and Battery
- Advanced EMC and ESD Performance
- Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.3”
- Interference and Damage Protection According to ISO7637
- AEC-Q100 and AEC-Q006 Qualified
- Packages: - 8-Lead 3 x 3 VDFN (all types) with wettable flanks (Moisture Sensitivity Level 1) - 8-Lead SOIC (only ATA663254)
Description
The ATA663201/03/31/54 device family includes two basic products: a LIN system basis chip (SBC) and a low-drop voltage regulator with compatible footprints. The ATA663231/54 (SBC) is a fully-integrated LIN transceiver, designed according to the LIN specification 2.0, 2.1, 2.2, 2.2A, ISO 17987-4 and SAEJ2602-2, with a low-drop voltage regulator (3.3V/ 5V/85 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple but powerful nodes in LIN bus systems. The ATA663231/54 is designed to handle the low- speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 Kbaud. The bus output is designed to withstand high voltage. Sleep mode and Silent mode ensure minimized current consumption even in the case of a floating or a short-circuited LIN bus. The ATA663201/03 (voltage regulator) is a fully integrated low-drop voltage regulator, with 3.3V/5V output voltage and 85 mA current capability. It is especially designed for the automotive environment. A key feature is that the current consumption is always below 170 μA (without load), even if the supply voltage is below the regulator’s nominal output voltage. Package Types Note: LIN SBC: LIN system basis chip including LIN transceiver and voltage regulator. Note: The current LIN standards use the terminology "Master" and "Slave”. The LIN standard groups have decided that the terms "Commander" and "Responder" will be used in future.NRES EN TXD VS LIN
5 GND
3 x 3 VDFN* NRES NC NC VS NC 3x3V D F N * SBC Voltage Regulator NRES EN TXD VS LIN *Includes Exposed Thermal Pad (EP); see Table 1-4. LIN Bus Device Family Including Voltage Regulator and LIN SBC with Compatible Footprint
DS20006075D-page 2 2018-2021 Microchip Technology Inc. Block Diagram LIN Transceiver with Integrated Voltage Regulator (SBC) TABLE 1: ATA663201/03/31/54 FAMILY MEMBERS Device Description ATA663231 LIN-SBC with 3.3V regulator ATA663254 LIN-SBC with 5V regulator ATA663201 Voltage regulator 3.3V ATA663203 Voltage regulator 5V 5GND 2EN 4TXD 1RXD VCC8 NRES3 Short-circuit and overtemperature protectionVoltage regulator Normal/Silent/ Fail-safe Mode 3.3V/5V Control unit Normal and Fail-safe Mode RF-filter LIN VS7 TXD Time-out timer Slew rate control Undervoltage reset Sleep mode VCC switched off Wake-up bus timer ATA663231/54 Receiver 9&& 9&& 9&&
2018-2021 Microchip Technology Inc. DS20006075D-page 3 ATA663201/03/31/54 Block Diagram Voltage Regulator PMOS Voltage Reference Undervoltage Reset 8V C C
3 NRES
DS20006075D-page 4 2018-2021 Microchip Technology Inc.
1.0 FUNCTIONAL DESCRIPTION
1.1 Physical Layer Compatibility
Since the LIN physical layer is independent of higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes based on earlier any restrictions.
1.2 Operating Modes
FIGURE 1-1: SBC OPERATING MODES Note 1: Condition f is valid for VS ramp up; at VS ramp down condition e is valid instead of f. a: V9S > VVS_th_U_F_up (2.4V) b: 996 < VVS_th_U_down (1.9V) c: Bus wake-up event (LIN) f: V9S > VVS_th_F_N_up (4.9V) d: V9CC < VVCC_th_uv_down (2.4V/4.2V) e: V9S < VVS_th_N_F_down (3.9V) EN = 0 Go to sleep command Go to silent command EN = 0 TXD = 0 bc & f EN = 0 TXD = 0 EN = 0 TXD = 1 EN = 1 & f TXD = 1 e b a b & f Fail-safe Mode VCC: ON VCC monitor active Communication: OFF Wake-up Signalling Undervoltage Signalling EN = 1 Normal Mode VCC: 21 VCC monitor active Communication: ON Sleep Mode VCC: OFF Communication: OFF Unpowered Mode All circuitry OFF Silent Mode VCC: 21 VCC monitor active Communication: OFF c & f, d EN = 1 & f & d & f (1)& f (1) TABLE 1-1: SBC (ATA663254, ATA663231) OPERATING MODES Operating Mode Transceiver V VCC (SBC Only) LIN TXD RXD Fail-Safe OFF 3.3V/5V Recessive Signaling fail-safe sources (see Table 1-2) Normal OFF 3.3V/5V TXD-dependent Follows data transmission Silent OFF 3.3V/5V Recessive High High Sleep/Unpowered OFF 0V Recessive Low Low
2018-2021 Microchip Technology Inc. DS20006075D-page 5 ATA663201/03/31/54 FIGURE 1-2: VOLTAGE REGULATOR OPERATING MODES
1.2.1 NORMAL MODE (SBC ONLY)
This is the Normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x. The VCC voltage regulator operates with a 3.3V/5V output voltage, with a low tolerance of ±2% and a maximum output current of 85 mA. If an undervoltage condition occurs, NRES switches to low and the IC changes its state to Fail-Safe mode.
1.2.2 SILENT MODE (SBC ONLY)
A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD signal has to be logic high during the mode select window. The transmission path is disabled in Silent mode. The voltage regulator is active. The overall supply current from V Bat is a combination of the I VSsilent =4 7 μA plus the VCC regulator output current IVCC. FIGURE 1-3: SWITCHING TO SILENT MODE In Silent mode, the internal termination resistor between the LIN pin and VS pin is disabled to minimize the current consumption in case the pin LIN is short- circuited to GND. Only a weak pull-up current (typically 10 μA) between the LIN pin and VS pin is present. Silent mode can be activated independently from the current level on pin LIN. If an undervoltage condition occurs, NRES is switched to low and the Microchip SBC changes its state to Fail- Safe mode. a b Active Mode VCC: ON VCC monitor active Unpowered Mode All circuitry OFF a: V9S > V VS_th_U_F_up (2.4V) b: V9S < VVS_th_U_down (1.9V) Delay time 6ilent mode td_silent = maximum 20 μs Mode select window LIN switches directly to 5ecessive mode td = 3.2μs LIN VCC NRES TXD EN Normal Mode Silent Mode
DS20006075D-page 6 2018-2021 Microchip Technology Inc.
1.2.3 SLEEP MODE (SBC ONLY)
A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD signal has to be logic low during the mode select window (Figure 1-6). FIGURE 1-4: SWITCHI NG TO SLEEP MODE In order to avoid any influence to the LIN pin when switching into Sleep mode, it is possible to switch EN up to 3.2 μs earlier to low than TXD. The easiest and best way to do this is by having two falling edges at TXD and EN at the same time. In Sleep mode, the transmission path is disabled. Supply current from V Bat is typically I VSsleep =9 μA. The VCC regulator is switched off; NRES and RXD are low. The internal termination resistor between the LIN pin and VS pin is disabled to minimize the current con- sumption in case the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 μA) between the LIN pin and the VS pin is present. The Sleep mode can be activated independently from the current level on the LIN pin. Voltage below the LIN pre-wake detection V LINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. If the TXD pin is short-circuited to GND, it is possible to switch to Sleep mode via EN after t > tdom.
1.2.4 FAIL-SAFE MODE (SBC ONLY)
The device automatically switches to Fail-Safe mode at system power-up. The voltage regulator is switched on. The NRES output remains low for t res =4m s a n d causes the microcontroller to be reset. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal mode. A low at NRES switches the IC into Fail-Safe mode directly. During Fail-Safe mode, the TXD pin is an output and, together with the RXD output pin, signals the Fail-Safe source. If the device enters the Fail-Safe mode coming from the Normal mode (EN = 1) due to a VS undervoltage condition (V VS <V VS_th_N_F_down), it is possible to switch into sleep or silent mode by a falling edge at the EN input. With this feature the current consumption can be further reduced. A wake-up event from either Silent or Sleep mode is signaled to the microcontroller using the RXD pin and the TXD pin. A VS undervoltage condition is also signaled at these two pins. The coding is shown in Table 1-2. A wake-up event switches the IC to Fail-Safe mode. Delay time 6leep mode td_sleep = maximum 20μs LIN switches directly to 5ecessive mode td = 3.2μs LIN VCC NRES TXD EN Sleep ModeNormal Mode Mode select window
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1.3 Wake-Up Scenarios from Silent
1.3.1 REMOTE WAKE-UP VIA LIN BUS
1.3.1.1 Remote Wake-Up from Silent Mode
(SBC only) A remote wake-up from Silent mode is only possible if TXD is high. A voltage less than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (>tbus) and the following rising edge at pin LIN (see Figure 1-5) result in a remote wake-up request. The device switches from Silent mode to Fail-Safe mode, the VCC voltage regulator remains activated and the internal LIN termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin and TXD pin (strong pull-down at TXD). EN high can be used to switch directly to Normal mode. FIGURE 1-5: LIN WAKE-UP FROM SILENT MODE
1.3.1.2 Remote Wake-Up from Sleep Mode
(SBC only) A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (>tbus) and a following rising edge at the LIN pin result in a remote wake-up request, causing the device to switch from Sleep mode to Fail-Safe mode. The VCC regulator is activated, and the internal LIN termination resistor is switched on. The remote wake- up request is indicated by a low level at RXD and TXD (strong pull-down at TXD) (see Figure 1-6). EN high can be used to switch directly from Sleep/ Silent mode to Fail-Safe mode. If EN is still high after VCC ramp-up and undervoltage reset time, the IC switches to Normal mode. TABLE 1-2: SIGNALING IN FAIL-SAFE MODE Fail-Safe Sources TXD RXD LIN wake-up (LIN pin) Low Low VSth (battery) undervoltage detection (VVS <3 . 9 V ) H i g h L o w Undervoltage detection active Silent mode 3.3V/5V Fail-6afe mode 3.3V/5V Normal mode Low Fail-6afe Mode Normal Mode EN High High NRES EN VCC RXD LIN bus Bus wake-up filtering time tbus HighTXD HighLow (strong pull-down)
DS20006075D-page 8 2018-2021 Microchip Technology Inc. FIGURE 1-6: LIN WAKE-UP FROM SLEEP MODE
1.3.2 WAKE-UP SOURCE RECOGNITION
(SBC ONLY) The device can distinguish between different wake-up sources. The wake-up source can be read on the TXD and RXD pin in Fail-Safe mode. These flags are immediately reset if the microcontroller sets the EN pin to high and the IC is in Normal mode.1.4 Behavior Under Low Supply Voltage Condition After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the block capacitor used in the application (see Figure 1-14). If V VS is higher than the minimum VS operation threshold V VS_th_U_F_up, the IC mode changes from unpowered mode to Fail-Safe mode. As soon as V VS exceeds the undervoltage threshold VVS_th_F_N_up, the LIN transceiver can be activated. The VCC output voltage reaches its nominal value after tVCC. This parameter depends on the externally applied VCC capacitor and the load. The NRES output is low for the reset time delay t reset. No mode change is possible during this time treset. The behavior of VCC, NRES and VS is shown in Figures 1-7 to Figure 1-10 (ramp-up and ramp-down). tVCC Off state On state Low Fail-6afe Mode Normal Mode EN High Microcontroller start-up time delay Reset time Low LowNRES EN VCC RXD LIN bus Bus wake-up filtering time tbus HighTXD Low (strong pull-down) High High TABLE 1-3: SIGNALING IN FAIL-SAFE MODE Fail-Safe Sources TXD RXD LIN wake-up (LIN pin) Low Low VSth (battery) undervoltage detection (VVS <3 . 9 V ) H i g h L o w
DS20006075D-page 10 2018-2021 Microchip Technology Inc. The current consumption of the SBC in Silent mode or in Fail-Safe mode and the one of the voltage regulator is always below 170 μA, even when the supply voltage VVS is lower than the regulator’s nominal output voltage VVCC.
1.5 Voltage Regulator
FIGURE 1-11: VOLTAGE REGULATOR: SU PPLY VOLTAGE RAMP-UP AND RAMP-DOWN The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommended to use a MLC capacitor with a minimum capacitance of 1.8 μF together with a 100 nF ceramic capacitor. Depending on the application, the values of these capacitors can be modified by the customer. During a short circuit at VCC, the output limits the output current to I VCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. If the chip temperature exceeds the value T VCCoff, the VCC output switches off. The chip cools down and, after a hysteresis of Thys, switches the output on again. When the ATA663201/03/31/54 in the 8-Lead VDFN package is being soldered onto the Printed Circuit Board (PCB) it is mandatory to connect the heat slug with a wide GND plate on the printed board to get a good heat sink. The main power dissipation of the IC is created from the VCC output current I VCC, which is needed for the application. Figure 1-12 shows the safe operating area of the ATA663201/03/31/54 in the 8-Lead VDFN package. VSV 12V 3.3V/5.0V VVCC_th_uv_up 3.3V/5.0V t VCC tVCC tReset 2.4V tres_f NRES t VVCC_th_uv_down
DS20006075D-page 12 2018-2021 Microchip Technology Inc.
1.6 Pin Descriptions
The descriptions of the pins are listed in Table 1-4.
1.6.1 OUTPUT PIN (RXD) (SBC ONLY)
In Normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a high level at RXD; LIN low (dominant state) is indicated by a low level at RXD. The output is a push-pull stage switching between VCC and GND. The AC characteristics are measured by an external load capacitor of 20 pF. In Silent mode, the RXD output switches to high.
1.6.2 ENABLE INPUT PIN (EN)
(SBC ONLY) The enable input pin controls the operating mode of the device. If EN is high, the circuit is in Normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent mode. No data transmission is then possible, and current consumption is reduced to I VSsilent typical 47 µA. The VCC regulator retains its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep mode. No data transmission is possible and the voltage regulator is switched off. The EN pin provides a pull-down resistor to force the transceiver into Recessive mode if EN is disconnected.
1.6.3 UNDERVOLTAGE RESET OUTPUT
(NRES) If the VCC voltage falls below the undervoltage detection threshold V VCC_th_uv_down, NRES switches to low after t res_f. The NRES stays low even if VVCC = 0V because NRES is internally driven from the VS voltage. If the VS voltage ramps down, NRES stays low until V VS < 1.5V and then becomes highly impedant. The implemented undervoltage delay keeps NRES low for tReset = 4 ms after VVCC reaches its nominal value. TABLE 1-4: PIN FUNCTION TABLE ATA663201 ATA663203 ATA663231 ATA663254 Symbol Description 3 x 3 VDFN 3 x 3 VDFN 3 x 3 VDFN 3x3 V D F N / SOIC — — 1 1 RXD Receive Data Output — — 2 2 EN Enables Normal Mode if the Input is High 3 3 3 3 NRES VCC Undervoltage Output, Open Drain, Low at Reset — — 4 4 TXD Transmit Data Input 5 5 5 5 GND Ground 6 6 6 6 LIN LIN Bus Line Input/Output — — 7 7 VS Supply Voltage 8 8 8 8 VCC Output Voltage Regulator 3.3V/5V/85 mA 1,2,4,6 1,2,4,6 — — NC Not Connected EP EP EP EP EP Exposed Thermal Pad, Internally Connected to the GND pin (Note 1) Note 1: Only for the VDFN package.
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1.6.4 INPUT/OUTPUT (TXD) (SBC ONLY)
In Normal mode, the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. If the TXD pin stays at GND level while switching into Normal mode, it must be pulled to high level longer than 10 µs before the LIN driver can be activated. This feature prevents the bus line from being accidentally driven to dominant state after the Normal mode has been activated (also in case of a short circuit at TXD to GND). During Fail-Safe mode, this pin is used as output and signals the fail- safe source. The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than t dom > 20 ms, the LIN bus driver is switched to the recessive state. Nevertheless, when switching to Sleep mode, the actual level at the TXD pin is relevant. To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
1.6.5 GROUND PIN (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of V VS.
1.6.6 BUS PIN (LIN) (SBC ONLY)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from -27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the event of a GND shift or V Bat disconnection. The LIN receiver thresholds comply with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled. During a short circuit at LIN to VBat, the output limits the output current to I BUS_LIM. Due to the power dissipation, the chip temperature exceeds T LINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. The VCC regulator works independently during LIN overtemperature switch-off. During a short circuit from LIN to GND, the IC can be switched into Sleep or Silent mode and even in this case the current consumption is lower than 100 µA in Sleep mode and lower than 120 µA in Silent mode. If the short-circuit disappears, the IC starts with a remote wake-up. The reverse current is <2 µA at pin LIN during loss of V Bat. This is optimal behavior for bus systems where some LIN nodes are supplied from battery or ignition.
1.6.7 SUPPLY PIN (VS)
LIN operating voltage is VVS = 5V to 28V. Undervoltage detection is implemented to disable transmission if VVS falls below typical 4.5V, thereby avoiding false bus messages. After switching on VVS, the IC starts in Fail- Safe mode and the voltage regulator is switched on. The supply current in Sleep mode is typically 9 µA and 47 µA in Silent mode.
1.6.8 VOLTAGE REGULATOR OUTPUT
PIN (VCC) The internal 3.3V/5V voltage regulator is capable of driving loads up to 85 mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shutdown. Furthermore, the output voltage is monitored and causes a reset signal at the NRES output pin if it drops below a defined threshold V VCC_th_uv_down.
DS20006075D-page 14 2018-2021 Microchip Technology Inc.
1.7 Typical Applications
FIGURE 1-14: TYPICAL APPLICATION CIRCUIT SBC FIGURE 1-15: TYPICAL APPLICAT ION CIRCUIT VOLTAGE REGULATOR Note: The exposed pad must always be connected to GND (for the 8-Lead VDFN package). ATA663254 ATA663231 9DFN/SOIC RXD EN NRES TXD VCC VCC Microcontroller VCC VBAT &RPPDQGHU node pull upVS LIN GND 100 nFC2 220 pF 10 μF/50V 2.2 μF 100 nF LIN GND GND 10 kΩ D2 1 kΩ Note: The exposed pad must always be connected to GND. ATA663201 ATA663203 9DFN 3 x 3NRES VCC VCC Microcontroller VCC VBAT VS GND 100nFC2 10μF/50V 2.2μF 100nF GND GND 10kΩ
2018-2021 Microchip Technology Inc. DS20006075D-page 15 ATA663201/03/31/54
2.0 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings†
Logic Pins: Voltage Level (RXD, TXD, EN, NRES) (V LIN: DC Voltage (V VCC: DC Voltage (V ESD according to IBEE LIN EMC; test specification 1.0 following IEC 61000-4-2 ESD HBM following STM5.1 with 1.5 kΩ/100 pF Virtual Junction Temperature (T †N O T I C E: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device, at those or any other conditions above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DS20006075D-page 16 2018-2021 Microchip Technology Inc.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
1 VS Pin
1.1 Nominal DC
VS 5 13.5 28 V
1.2 Supply Current in
IVSsleep 6 9 12 µA Sleep mode VLIN >V VS -0 . 5 V VVS < 14V, T = +27°C (Note 1) IVSsleep 3 10 15 µA Sleep mode VLIN >V VS -0 . 5 V VVS <1 4 V IVSsleep_short 20 50 100 µA Sleep mode, VLIN =0 V bus shorted to GND VVS <1 4 V
1.3 Supply Current in
Silent Mode (SBC) /Active Mode (Voltage Regulator) I VSsilent 30 47 58 µA Bus recessive 5.5V < VVS <1 4 V without load at VCC T=+ 2 7 ° C (Note 1) I VSsilent 30 50 64 µA Bus recessive 5.5V <VVS <1 4 V without load at VCC IVSsilent 50 130 170 µA Bus recessive 2.0V < VVS <5 . 5 V without load at VCC IVSsilent_short 50 80 120 µA Silent mode 5.5V < VVS <1 4 V bus shorted to GND without load at VCC
1.4 Supply Current in
IVSrec 150 230 300 µA Bus recessive VVS <1 4 V without load at VCC
1.5 Supply Current in
IVSdom 200 700 950 µA Bus dominant (internal LIN pull-up resistor active) VVS <1 4 V without load at VCC
1.6 Supply Current in
IVSfail 40 55 80 µA Bus recessive 5.5V < VVS <1 4 V without load at VCC IVSfail 50 130 170 µA Bus recessive 2.0V < VVS <5 . 5 V without load at VCC
1.7 VS Undervoltage
(Switching from Normal to Fail- Safe Mode) V VS_th_U_down 3.9 4.3 4.7 V Decreasing supply voltage VVS_th_U_up 4.1 4.6 4.9 V Increasing supply voltage
1.8 VS Undervoltage
VVS_hys_F_N 0.1 0.25 0.4 V
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1.9 VS Operation
(Switching to Unpowered Mode) VVS_th_U_down 1.9 2.05 2.3 V Switch to unpowered mode VVS_th_U_up 2.0 2.25 2.4 V Switch from unpowered to Fail- Safe mode
1.10 VS Undervoltage
V VS_hys_U 0.1 0.2 0.3 V
2 RXD Output Pin (only SBC)
2.1 Low-Level Output
VRXDL — 0.2 0.4 V Normal mode, VLIN =0 V , IRXD =2m A
2.2 High-Level Output
VRXDH VVCC -0 . 4 V VVCC -0 . 2 V — V N o r m a l m o d e VLIN =V VS, IRXD =- 2m A
3 TXD Input/Output Pin (only SBC)
3.1 Low-Level Voltage
VTXDL -0.3 — +0.8 V
3.2 High-Level
VTXDH 2— V VCC +0 . 3 V V
3.3 Pull-Up Resistor R TXD 40 70 100 k Ω VTXD =0 V
3.4 High-Level
ITXD -3 — +3 µA V TXD =V VCC
3.7 Low-Level Output
I TXD 1.5 2.5 8 mA Fail-Safe mode VLIN =V VS VTXD =0 . 4 V
4 EN Input Pin (only SBC)
4.1 Low-Level Voltage
VENL -0.3 — +0.8 V
4.2 High-Level
VENH 2— V VCC +0 . 3 V V
4.3 Pull-Down
REN 50 125 200 k Ω VEN =V VCC
4.4 Low-Level Input
IEN -3 — +3 µA V EN =0 V
5 NRES Open Drain Output Pin
5.1 Low-Level Output
VNRESL 0.2 0.4 V V VS ≥ 5.5V INRES =2m A
5.2 Undervoltage
tReset 246 m s V VS ≥ 5.5V CNRES =2 0p F
5.3 Reset Debounce
tres_f 0.5 — 10 µs V VS ≥ 5.5V CNRES =2 0p F
5.4 Switch Off
INRES_L -3 — +3 µA V NRES =5 . 5 V ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
DS20006075D-page 18 2018-2021 Microchip Technology Inc. 8 VCC Voltage Regulator (3.3V)
8.1 Output Voltage
VVCCnor 3.234 — 3.366 V 4V < V VS <1 8 V (0 mA to 50 mA) VVCCnor 3.234 — 3.366 V 4.5V < V VS <1 8 V (0 mA to 85 mA) (Note 2)
8.2 Output Voltage
VVCClow VVS -V D —3 . 3 6 6 V 3 V < V VS <4 V
8.3 Regulator Drop
VD1 — 100 150 mV V VS >3 V , IVCC =- 1 5m A
8.4 Regulator Drop
VD2 — 300 500 mV V VS >3 V , IVCC =- 5 0m A
8.5 Line Regulation
VCCline — 0.1 0.2 % 4V < V VS <1 8 V
8.6 Load Regulation
VCCload —0 . 1 0 . 5 % 5 m A < I VCC <5 0m A
8.7 Output Current
IVCClim — -180 -120 mA V VS >4 V 8.8 Load Capacity C load 1.8 2.2 — µF MLC capacitor (Note 3)
8.9 VCC Undervoltage
(NRES ON) V VCC_th_uv_down 2.3 2.5 2.8 V Referred to VCC VVS >4 V VCC Undervoltage Threshold (NRES OFF) V VCC_th_uv_up 2.5 2.6 2.9 V Referred to VCC VVS >4 V
8.10 Hysteresis of VCC
V VCC_hys_uv 100 200 300 mV Referred to VCC VVS >4 V
8.11 Ramp-Up Time
VVS >4 V t o VVCC =3 . 3 V tVCC —1 1 . 5 m s C VCC =2 . 2µ F Iload =- 5m A a t V C C
9 VCC Voltage Regulator (5V)
9.1 Output Voltage
VVCCnor 4.9 — 5.1 V 5.5V < V VS <1 8 V (0 mA to 50 mA) VVCCnor 4.9 — 5.1 V 6V < V VS <1 8 V (0 mA to 85 mA) (Note 2)
9.2 Output Voltage
V VCC at Low VVS VVCClow VVS -V D —5 . 1 V 4 V < V VS <5 . 5 V
9.3 Regulator Drop
VD1 — 100 200 mV V VS >4 V , IVCC =- 2 0m A
9.4 Regulator Drop
VD1 — 300 500 mV V VS >4 V , IVCC =- 5 0m A
9.5 Regulator Drop
VD3 —— 1 5 0 m V V VS >3 . 3 V , IVCC =- 1 5m A
9.6 Line Regulation
VCCline — 0.1 0.2 % 5.5V < V VS <1 8 V ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
2018-2021 Microchip Technology Inc. DS20006075D-page 19 ATA663201/03/31/54
9.7 Load Regulation
VCCload —0 . 1 0 . 5 % 5 m A < I VCC <5 0m A
9.8 Output Current
IVCClim — -180 -120 mA V VS >5 . 5 V 9.9 Load Capacity C load 1.8 2.2 — µF MLC capacitor (Note 3)
9.10 VCC Undervoltage
(NRES ON) VVCC_th_uv_down 4.2 4.4 4.6 V Referred to VCC VVS >4 V VCC Undervoltage Threshold (NRES OFF) VVCC_th_uv_up 4.3 4.6 4.8 V Referred to VCC VVS >4 V
9.11 Hysteresis of
VVCC_hys_uv 100 200 300 mV Referred to VCC VVS >5 . 5 V
9.12 Ramp-Up Time
VVS >5 . 5 V t o VVCC =5 V tVCC —1 1 . 5 m s C VCC =2 . 2µ F Iload =- 5m A a t V C C
10 LIN Bus Driver (only SBC): Bus Load Conditions:
Load 1 (small): 1 nF, 1 kΩ; Load 2 (large): 10 nF, 500; C RXD = 20 pF, Load 3 (medium): 6.8 nF, 660 characterized on samples 12.7 and 12.8 specifies the timing parameters for proper operation at 20 kb/s and 12.9 and 12.10 at 10.4 kb/s
10.1 Driver Recessive
VBUSrec 0.9 x VVS —V VS V Load1/Load2
10.2 Driver Dominant
V_LoSUP —— 1 . 2 V V VS =7 V Rload =5 0 0
10.3 Driver Dominant
V_HISUP —— 2 V V VS =1 8 V Rload =5 0 0
10.4 Driver Dominant
V_LoSUP_1k 0.6 — — V V VS =7 V Rload = 1000
10.5 Driver Dominant
V_HISUP_1K 0.8 — — V V VS =1 8 V Rload = 1000
10.6 Pull-Up Resistor to
RLIN 20 30 47 k Ω The serial diode is mandatory
10.7 Voltage Drop at
VSerDiode 0.4 — 1.0 V In pull-up path with RLIN ISerDiode =1 0m A (Note 3)
10.8 LIN Current
V BUS =V BAT_MAX IBUS_LIM 40 120 200 mA
10.9 Input Leakage
I BUS_PAS_dom -1 -0.35 — mA Input leakage current driver off V BUS =0 V VBAT =1 2 V ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
DS20006075D-page 20 2018-2021 Microchip Technology Inc.
10.10 Leakage Current
IBUS_PAS_rec — 10 20 µA Driver off 8V < VBAT < 18V 8V < VBUS <1 8 V VBUS ≥ VBAT
10.11 Leakage Current
ground. Loss of local ground must not affect communication in the residual network. I BUS_NO_gnd -10 +0.5 +10 µA GND Device =V VS VBat = 12V 0V < VBUS <1 8 V
10.12 Leakage current at
battery. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition. I BUS_NO_bat —0 . 1 2 µ A V Bat disconnected VSUP_Device =G N D 0V < VBUS <1 8 V
10.13 Capacitance on
CLIN — — 20 pF Note 3
11 LIN Bus Receiver (only SBC)
11.1 Center of Receiver
VBUS_CNT 0.475 x VVS 0.5 x VVS 0.525 x VVS VV BUS_CNT = (Vth_dom + Vth_rec)/2
11.2 Receiver
VBUSdom -27 — 0.4 x V VS VV EN = 5V/3.3V
11.3 Receiver
VBUSrec 0.6 x VVS —4 0 V V EN = 5V/3.3V
11.4 Receiver Input
VBUShys 0.028 x VVS 0.1 x VVS 0.175 x VVS VV hys = Vth_rec -V th_dom
11.5 Pre-Wake
V LINH VVS -2 V — V VS +0 . 3 V V
11.6 Pre-Wake
VLINL -27 — V VS - 3.3V V Activates the LIN receiver
12 Internal Timers (only SBC)
12.1 Dominant Time for
t bus 50 100 150 µs V LIN =0 V ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
2018-2021 Microchip Technology Inc. DS20006075D-page 21 ATA663201/03/31/54
12.2 Time Delay for
t norm 51 5 2 0 µ s V EN = 5V/3.3V
12.3 Time Delay for
t sleep 51 5 2 0 µ s V EN =0 V
12.5 TXD Dominant
tdom 20 40 60 ms V TXD =0 V
12.6 Time Delay for
t s_n 51 5 4 0 µ s V EN = 5V/3.3V 12.7 Duty Cycle 1 D1 0.396 — — — TH Rec(max) = 0.744 x VVS THDom(max) = 0.581 x VVS VVS = 7.0V to 18V tBit =5 0µ s D1 = tbus_rec(min)/ (2 x tBit) 12.8 Duty Cycle 2 D2 — — 0.581 — TH Rec(min) = 0.422 x VVS THDom(min) = 0.284 x VVS VVS = 7.6V to 18V tBit =5 0µ s D2 = tbus_rec(max)/ (2 x tBit) 12.9 Duty Cycle 3 D3 0.417 — — — TH Rec(max) = 0.778 x VVS THDom(max) = 0.616 x VVS VVS = 7.0V to 18V tBit =9 6µ s D3 = tbus_rec(min)/ (2 x tBit) 12.10 Duty Cycle 4 D4 — — 0.590 — TH Rec(min) = 0.389 x VVS THDom(min) = 0.251 x VVS VVS = 7.6V to 18V tBit =9 6µ s D4 = tbus_rec(max)/ (2 x tBit)
12.11 Slope Time Fall-
tSLOPE_fall tSLOPE_rise 3.5 — 22.5 µs V VS = 7.0V to 18V ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions
DS20006075D-page 22 2018-2021 Microchip Technology Inc. FIGURE 2-1: DEFINITION OF BUS TIMING CHARACTERISTICS
13 Receiver Electrical AC Parameters of the LIN Physical Layer (only SBC)
LIN Receiver, RXD Load Conditions: CRXD = 20 pF
13.1 Propagation Delay
trx_pd —— 6 µ s V VS =7 . 0 Vt o1 8 V trx_pd =m a x ( trx_pdr, trx_pdf)
13.2 Symmetry of
t rx_sym -2 — +2 µs V VS =7 . 0 Vt o1 8 V trx_sym = trx_pdr -t rx_pdf Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, all values are specified for 5V < VVS <2 8 V , -40°C < TvJ < +150°C and refer to the GND pin. No. Parameters Symbol Min. Typ. Max. Unit Conditions TXD (Input to transmitting node) VS (Transceiver supply of transmitting node) RXD (Output of receiving node1) RXD (Output of receiving node2) LIN Bus Signal Thresholds of receiving node1 Thresholds of receiving node2 tBus_rec(max) trx_pdr(1) trx_pdf(2)trx_pdr(2) trx_pdf(1) tBus_dom(min) tBus_dom(max) THRec(max) THDom(max) THRec(min) THDom(min) tBus_rec(min) tBit tBittBit
2018-2021 Microchip Technology Inc. DS20006075D-page 23 ATA663201/03/31/54 TEMPERATURE SPECIFICATIONS 8-LEAD VDFN Parameters Sym. Min. Typ. Max. Unit Thermal Resistance Virtual Junction to Exposed Thermal Pad R thvJC —1 0— K / W Thermal Resistance Virtual Junction to Ambient, where Exposed Thermal Pad is Soldered to PCB according to JEDEC RthvJA —5 0— K / W Thermal Shutdown of VCC Regulator T VCCoff +150 +165 +180 °C Thermal Shutdown of LIN Output T LINoff +150 +165 +180 °C Thermal Shutdown Hysteresis T hys —1 0— ° C TEMPERATURE SPECIFICATIONS 8-LEAD SOIC Parameters Sym. Min. Typ. Max. Unit Thermal Resistance Virtual Junction to Ambient with a Heat Sink at GND (pin 5) on PCB (fused lead frame to pin 5) RthvJA —8 0— K / W Thermal Shutdown of VCC Regulator T VCCoff +150 +165 +180 °C Thermal Shutdown of LIN Output T LINoff +150 +165 +180 °C Thermal Shutdown Hysteresis T hys —1 0— ° C
DS20006075D-page 24 2018-2021 Microchip Technology Inc.
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. NNN 6566 ZZZ 8-Lead SOIC (only ATA663254) 8-Lead 3 x 3 mm VDFN Example ATA663203 YWW ATA656 ZZZZZZZ 828 663254 1828256 663203 256 6566 ZZZ 663201 256 Example ATA663231 Example ATA663254 Example ATA663201 Example ATA663254 YWW XXXXXX YYWWNNN 6566 ZZZ 663231 256 6566 ZZZ 663254 256
2018-2021 Microchip Technology Inc. DS20006075D-page 25 ATA663201/03/31/54
0.25 C A–B D
C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-OA Rev D Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b
0.10 C A–B
H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D
DS20006075D-page 26 2018-2021 Microchip Technology Inc. Microchip Technology Drawing No. C04-057-OA Rev D Sheet 2 of 2 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75--AOverall Height
1.27 BSCePitch
protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.
2018-2021 Microchip Technology Inc. DS20006075D-page 27 ATA663201/03/31/54 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-OA Rev B 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm Body [SOIC] BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS
1.27 BSC
E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN
DS20006075D-page 28 2018-2021 Microchip Technology Inc. BA 0.10 C 0.10 C
0.10 C A B
0.05 C (DATUM B) (DATUM A) C SEATING PLANE N TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Microchip Technology Drawing C04-21358 Rev C Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy YCL D E NOTE 1 (A3) A N NOTE 1 L K e 8X b A A
2018-2021 Microchip Technology Inc. DS20006075D-page 29 ATA663201/03/31/54 Microchip Technology Drawing C04-21358 Rev C Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N
0.65 BSC
0.203 REF
1.50 0.35 0.25 0.80 0.00 0.30 0.40 1.60 0.90 0.035
3.00 BSC
1.70 0.45 0.35 1.00 0.05 MAX K- 0.20 - REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Terminal-to-Exposed-Pad 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy YCL Overall Length Exposed Pad Length D D2 2.30 2.40 2.50 SECTION A–A PARTIALLY PLATED Wettable Flank Step Cut Depth A4 0.10 - 0.19 E3 --0 . 0 8 5Wettable Flank Step Cut Width
DS20006075D-page 30 2018-2021 Microchip Technology Inc. RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 2.50 1.70 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.80 0.35 Microchip Technology Drawing C04-23358 Rev C NOM 8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] CContact Pad Spacing 3.00 Contact Pad to Center Pad (X8) G1 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks C E EV ØV SILK SCREEN EVX2 Pin 1 Index Chamfer CH 0.20 Contact Pad to Contact Pad (X6) G2 0.20 CH
2018-2021 Microchip Technology Inc. DS20006075D-page 31 ATA663201/03/31/54 APPENDIX A: REVISION HISTORY Revision D (April 2021) The following is the list of modifications:
- The current LIN standards use the terminology "Master" and "Slave”. The LIN standard groups have decided that the terms "Commander" and "Responder" will be used in future. Added the Note related to this on page 1.
- Updated Parameter 3.7 on page 17.
- Minor text updates. Revision C (January 2021) The following is the list of modifications:
- Updated the VDFN package drawing.
- Updated the Product Identification System sec- tion.
- Minor text updates. Revision B (January 2019) The following is the list of modifications:
- Updated Parameter 1.4 on page 16.
- Updated the dynamic maximum rating of the VS pin on page 15. Revision A (October 2018)
- Original release of this document.
- Minor text updates.
- This document replaces Atmel - 9337G-AUTO-09/16.
DS20006075D-page 32 2018-2021 Microchip Technology Inc. NOTES:
2018-2021 Microchip Technology Inc. DS20006075D-page 33 ATA663201/03/31/54 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office . Examples: a) ATA663201-GBQW: ATA663201, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified b) ATA663203-GBQW: ATA663203, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified c) ATA663231-GBQW: ATA663231, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified d) ATA663254-GAQW: ATA663254, 8-Lead SOIC, Tape and Reel, RoHS compliant package, Automotive Qualified e) ATA663254-GBQW: ATA663254, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified f) ATA663254-GAQW-VAO:ATA663254, 8-Lead SOIC, Tape and Reel, RoHS compliant package, Automotive Qualified g) ATA663254-GBQW-VAO:ATA663254, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified h) ATA663231-GBQW-VAO:ATA663231, 8-Lead VDFN, Tape and Reel, RoHS compliant package, Automotive Qualified PART NO. X Package DirectivesDevice Device: ATA663201: 3.3V Voltage Regulator ATA663203: 5V Voltage Regulator ATA663231: LIN System Basis Chip, including LIN Transceiver and 3.3V Voltage Regulator ATA663254: LIN System Basis Chip, including LIN Transceiver and 5V Voltage Regulator Package: GA = 8-Lead SOIC GB = 8-Lead VDFN Tape and Reel Option: Q = 330 mm diameter Tape and Reel (1) Package Directives Classification: W = Package is RoHS compliant (2) Qualification: VAO = Automotive blank= Automotive XX Package X Tape and Reel Option Classification Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: RoHS compliant; maximum concentration value of 0.09% (900 ppm) for Bromine (Br) and Chlorine (Cl) and less than 0.15% (1500 ppm) total Bromine (Br) and Chlorine (Cl) in any homogeneous material. Maximum concentration value of 0.09% (900 ppm) for Antimony (Sb) in any homogeneous material. – –XXX Qualification Note: All devices listed in this data sheet are Automotive qualified. Due to a new nomenclature, the automotive qualified devices will get the suffix -VAO in the future, but as regards the qualification, there is no difference between all the devices listed in this data sheet.
DS20006075D-page 34 2018-2021 Microchip Technology Inc. NOTES:
2018-2021 Microchip Technology Inc. DS20006075D-page 35 Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Infor- mation regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN- TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life sup- port and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashT ec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018-2021, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-8169-0 Note the following details of the code protection feature on Microchip devices:
- Microchip products meet the specifications cont ained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secu re when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods being used in at tempts to breach the code protection features of the Microchip devices . We believe that these methods require using the Micr ochip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach thes e code protection features, most likely, cannot be accomplish ed wit hout violating Microchip's intellectual property rights.
- Microchip is willing to work with any customer who is concerned about the integrity of its code.
- Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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