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ATA6562

Microchip Technology

High-Speed CAN Transceiver with Standby Mode 09/14/21

Manufacturer: Microchip Technology

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Features

Fully ISO 11898-2, ISO 11898-2: 2016 and SAE J2962-2 Compliant
CAN FD Ready
Communication Speed up to 5 Mbps
ISO 26262 Functional Safety Ready
Low Electromagnetic Emission (EME) and High Electromagnetic Immunity (EMI)
Differential Receiver with Wide Common-Mode Range
ATA6562: Silent Mode
Remote Wake-Up Capability via CAN Bus - Wake-Up on Pattern (WUP), as Specified in ISO 11898-2: 2016, 3.8 µs Activity Filter Time
Functional Behavior Predictable under All Supply Conditions
Transceiver Disengages from the Bus When Not Powered Up
RXD Recessive Clamping Detection
High Electrostatic Discharge (ESD) Handling Capability on the Bus Pins
Bus Pins Protected Against Transients in Automotive Environments
Transmit Data (TXD) Dominant Time-Out Function
Undervoltage Detection on VCC and VIO Pins
CANH/CANL Short-Circuit and Overtemperature Protected
Fulfills the OEM “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Appli- cations”, Rev. 1.3
AEC-Q100 and AEC-Q006 Qualified
Two Ambient Temperature Grades Available: - ATA6562-GAQW1, ATA6563-GAQW1, ATA6562-GBQW1 and ATA6563-GBQW1 up to Tamb = +125°C - ATA6562-GAQW0, ATA6563-GAQW0, ATA6562-GBQW0 and ATA6563-GBQW0 up to Tamb = +150°C
Packages: 8-pin SOIC, 8-pin VDFN with Wettable Flanks (Moisture Sensitivity Level 1)

Applications

Classical CAN and CAN FD networks in Automotive, Industrial, Aerospace, Medical and Consumer applications. General Description The ATA6562/3 is a high-speed CAN transceiver that provides an interface between a Controller Area Net- work (CAN) protocol controller and the physical Two-Wire CAN bus. The transceiver is designed for high-speed (up to 5 Mbps) CAN applications in the automotive industry, providing differential transmit and receive capability to (a microcontroller with) a CAN pro- tocol controller. It offers improved electromagnetic compatibility (EMC) and ESD performance as well as features such as:

Ideal passive behavior to the CAN bus when the supply voltage is off
Direct interfacing to microcontrollers with supply voltages from 3V to 5V (ATA6563) Three operating modes together with the dedicated fail-safe features make the ATA6562/3 an excellent choice for all types of high-speed CAN networks, espe- cially in nodes requiring Low-Power mode with wake-up capability via the CAN bus. Package Types *Includes Exposed Thermal Pad (EP); see Table 1-2. ATA6563 3 x 3 VDFN* with wettable flanks ATA6562 SOIC VCC GND RXD CANH CANL

5 NSIL

5 VIO

3 x 3 VDFN* with wettable flanks VCC GND RXD CANH CANL NSIL STBY TXD 1 VCC GND RXD CANH CANL VIO STBYTXD 1 High-Speed CAN Transceiver with Standby Mode

DS20005790E-page 2  2017-2021 Microchip Technology Inc. and its subsidiaries ATA6562/3 Family Members Device VIO Pin NSIL Grade 0 Grade 1 VDFN8 SOIC8 Description ATA6562-GAQW0 X X X Standby mode and Silent mode ATA6562-GAQW1 X X X Standby mode and Silent mode ATA6562-GBQW0 X X X Standby mode and Silent mode ATA6562-GBQW1 X X X Standby mode and Silent mode ATA6563-GAQW0 X X X Standby mode, VIO - pin for compatibility with 3.3V and 5V microcontroller ATA6563-GAQW1 X X X Standby mode, VIO - pin for compatibility with 3.3V and 5V microcontroller ATA6563-GBQW0 X X X Standby mode, VIO-pin for com- patibility with 3.3V and 5V micro- controller ATA6563-GBQW1 X X X Standby mode, VIO - pin for compatibility with 3.3V and 5V microcontroller Note: For ordering information, see the Product Identification System section.

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 3 ATA6562/3 Functional Block Diagram Notes: 1. Pin 5: ATA6563: VIO ATA6562: NSIL (the VIO line and the VCC line are internally connected) 2. HSC: High-Speed comparator 3. WUC: Wake-Up comparator Temperature Protection TXD Time-Out- Timer Control Unit MUX Slope Control and Driver Wake-up Filter CANH CANL TXD GND V&& RXD STBY V,2 NSIL VIO(1) VIO(1) VIO( VCC HSC(2) WUC(3) VIO(1) 35(1) 5(1)

DS20005790E-page 4  2017-2021 Microchip Technology Inc. and its subsidiaries

1.0 FUNCTIONAL DESCRIPTION

The ATA6562/3 is a stand-alone dual high-speed CAN transceiver compliant with the ISO 11898-2, ISO 11898-2: 2016, ISO 11898-5 and SAE J2962-2 CAN standards. It provides a very low current consumption in Standby mode and wake-up capability via the CAN bus. There are two versions available, only differing in the function of pin 5:

ATA6562: The pin 5 is the control input for Silent mode NSIL, allowing the ATA6562 to only receive data but not send data via the bus. The output driver stage is disabled. The VIO line and the VCC line are internally connected, this sets the signal levels of the TXD, RXD, STBY , and NSIL pins to levels compatible with 5V microcontrollers.
ATA6563: The pin 5 is the VIO pin and should be connected to the microcontroller supply voltage. This allows direct interfacing to microcontrollers with supply voltages down to 3V and adjusts the signal levels of the TXD, RXD, and STBY pins to the I/O levels of the microcontroller. The I/O ports are supplied by the VIO pin.

1.1 Operating Modes

Each of the transceivers supports three operating modes: Unpowered, Standby and Normal. The ATA6562 additionally has the Silent mode. These modes can be selected via the STBY and NSIL pin. See Figure 1-1 and Table 1-1 for a description of the operating modes. FIGURE 1-1: OPERATING MODES TABLE 1-1: OPERATING MODES Mode Inputs Outputs STBY NSIL Pin TXD CAN Driver Pin RXD Unpowered X(3) X(3) X(3) Recessive Recessive Standby HIGH X(3) X(3) Recessive Active (4) Silent (only for ATA6562) LOW LOW X(3) Recessive Active (1) Normal LOW HIGH(2) LOW Dominant LOW LOW HIGH(2) HIGH Recessive HIGH Note 1: LOW if the CAN bus is dominant, HIGH if the CAN bus is recessive. 2: Internally pulled up if not bonded out. 3: Irrelevant 4: Reflects the bus only for wake-up Note: For the ATA6563 NSIL is internally set to “1”. Unpowered Mode Standby Mode VCC < Vuvd(VCC)VCC < Vuvd(VCC) Silent Mode VCC > Vuvd(VCC)VCC < Vuvd(VCC) STBY = 1 STBY = 0 and (NSIL = 0 or TXD = 0) Normal Mode STBY = 0 and NSIL = 1 and TXD = 1 and Error = 0 STBY = 1 NSIL = 1 and TXD = 1 and Error = 0 NSIL = 0 or Error = 1 ATA6562 Unpowered Mode Standby Mode VCC <V uvd(VCC) or VIO <V uvd(VIO) Silent Mode * STBY = 1 STBY = 0 and TXD = 0 Normal Mode STBY = 0 and TXD = 1 and Error = 0 STBY = 1 TXD = 1 and Error = 0 Error = 1 ATA6563 VCC <V uvd(VCC) or VIO <V uvd(VIO) VCC <V uvd(VCC) or VIO <V uvd(VIO) VCC >V uvd(VCC) or VIO >V uvd(VIO) * Silent Pode is externally not accessible

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 5 ATA6562/3

1.1.1 NORMAL MODE

A low level on the STBY pin together with a high level on pin TXD selects the Normal mode. In this mode, the transceiver is able to transmit and receive data via the CANH and CANL bus lines (see Functional Block Diagram). The output driver stage is active and drives data from the TXD input to the CAN bus. The High-Speed Comparator (HSC) converts the analog data on the bus lines into digital data which is output to pin RXD. The bus biasing is set to V VCC/2 and the undervoltage monitoring of VCC is active. The slope of the output signals on the bus lines is controlled and optimized in a way that guarantees the lowest possible electromagnetic emission (EME). To switch the device in normal operating mode, set the STBY pin to low and the TXD pin to high (see Table 1-1 and Figure 1-2). The STBY pin provides a pull-up resistor to VIO, thus ensuring a defined level if the pin is open. Please note that the device cannot enter Normal mode as long as TXD is at ground level. The switching into Normal mode is depicted in the following two figures, Figure 1-2 and Figure 1-3. FIGURE 1-2: SWITCHING FROM STANDBY MODE TO NORMAL MODE (NSIL = HIGH) FIGURE 1-3: SWITCHING FROM SILENT MODE TO NORMAL MODE #$)! )-/ / )'*, "%// / .(/ '(-%#0 #-0%0 0 - $&) 0 0 0 /,0".0 0 %*"0%0

DS20005790E-page 6  2017-2021 Microchip Technology Inc. and its subsidiaries

1.1.2 SILENT MODE (ONLY WITH THE

ATA6562) A low level on the NSIL pin (available on Pin 5) and on the STBY pin selects Silent mode. This receive-only mode can be used to test the connection of the bus medium. In Silent mode, the ATA6562 can still receive data from the bus, but the transmitter is disabled and therefore no data can be sent to the CAN bus. The bus pins are released to recessive state. All other IC functions, including the high-speed comparator (HSC), continue to operate as they do in Normal mode. Silent mode can be used to prevent a faulty CAN controller from disrupting all network communications.

1.1.3 STANDBY MODE

A high level on the STBY pin selects Standby mode. In this mode, the transceiver is not able to transmit or correctly receive data via the bus lines. The transmitter and the high-speed comparator (HSC) are switched off to reduce current consumption. For ATA6562 only: In the event the NSIL input pin is set to low in Standby mode, the internal pull-up resistor causes an additional quiescent current from VIO to GND. Microchip recommends setting the NSIL pin to high in Standby mode.

1.1.3.1 Remote Wake-up via the CAN Bus

In Standby mode the bus lines are biased to ground to reduce current consumption to a minimum. The ATA6562/3 monitors the bus lines for a valid wake-up pattern as specified in the ISO 11898-2: 2016. This filtering helps to avoid spurious wake-up events, which would be triggered by scenarios such as a dominant clamped bus or by a dominant phase due to noise, spikes on the bus, automotive transients or EMI. The wake-up pattern consists of at least two consecutive dominant bus levels for a duration of at least t Filter, each separated by a recessive bus level with a duration of at least tFilter. Dominant or recessive bus levels shorter than tFilter are always being ignored. The complete dominant-recessive-dominant pattern (as shown in Figure 1-4) must be received within the bus wake-up time-out time tWake to be recognized as a valid wake-up pattern. Otherwise, the internal wake-up logic is reset and then the complete wake-up pattern must be retransmitted to trigger a wake-up event. Pin RXD remains at high level until a valid wake-up event has been detected. During Normal mode, at a VCC undervoltage condition or when the complete wake-up pattern is not received within tWake, no wake-up is signalled at the RXD pin. When a valid CAN wake-up pattern is detected on the bus, the RXD pin switches to low to signal a wake-up request. A transition to Normal mode is not triggered until the STBY pin is forced back to low by the micro - controller. FIGURE 1-4: TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE

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1.2 Fail-safe Features

1.2.1 TXD DOMINANT TIME-OUT

A TXD dominant time-out timer is started when the TXD pin is set to low. If the low state on the TXD pin persists for longer than t to(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state. This function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). The TXD dominant time-out timer is reset when the TXD pin is set to high. If the low state on the TXD pin was longer than tto(dom)TXD, then the TXD pin has to be set to high longer 4 µs in order to reset the TXD dominant time-out timer.

1.2.2 INTERNAL PULL-UP STRUCTURE

AT THE TXD AND STBY INPUT PINS The TXD and STBY pins have an internal pull-up resistor to VIO. This ensures a safe, defined state in case one or both pins are left floating. Pull-up currents flow in these pins in all states, meaning all pins should be in high state during Standby mode to minimize the current consumption.

1.2.3 UNDERVOLTAGE DETECTION ON

If VVCC or VVIO drops below its undervoltage detection levels (V uvd(VCC) and V uvd(VIO))(see Section 2.0, Electrical Characteristics), the transceiver switches off and disengages from the bus until VVCC and VVIO has recovered. The low-power wake-up comparator is only switched off during a VCC and VIO undervoltage. The logic state of the STBY pin is ignored until the V VCC voltage or VVIO voltage has recovered.

1.2.4 BUS WAKE UP ONLY AT

Due to the implementation of the wake-up filtering the ATA6562/3 does not wake-up when the bus is in a long dominant phase, it only wakes up at a dedicated wake-up pattern as specified in the ISO 11898-2: 2016. This means for a valid wake-up at least two consecutive dominant bus levels for a duration of at least t Filter, each separated by a recessive bus level with a duration of at least tFilter must be received via the bus. Dominant or recessive bus levels shorter than tFilter are always being ignored. The complete dominant-recessive-dominant pattern as shown in Figure 1-4, must be received within the bus wake-up time-out time tWake to be recognized as a valid wake-up pattern. This filtering leads to a higher robustness against EMI and transients and reduces therefore the risk of an unwanted bus wake- up significantly.

1.2.5 OVERTEMPERATURE

The output drivers are protected against overtemperature conditions. If the junction temperature exceeds the shutdown junction temperature, T Jsd, the output drivers are disabled until the junction temperature drops below T Jsd and pin TXD is at high level again. The TXD condition ensures that output driver oscillations due to temperature drift are avoided. See Figure 1-5.

1.2.6 SHORT-CIRCUIT PROTECTION OF

The CANH and CANL bus outputs are short-circuit protected, either against GND or a positive supply voltage. A current-limiting circuit protects the transceiver against damage. If the device is heating up due to a continuous short on CANH or CANL, the internal overtemperature protection switches off the bus transmitter.

1.2.7 RXD RECESSIVE CLAMPING

This fail-safe feature prevents the controller from sending data on the bus if its RXD line is clamped to HIGH (e.g., recessive). That is, if the RXD pin cannot signalize a dominant bus condition because it is e.g, shorted to VCC, the transmitter within ATA6562/3 is disabled to avoid possible data collisions on the bus. In Normal and Silent mode (only ATA6562), the device permanently compares the state of the high-speed comparator (HSC) with the state of the RXD pin. If the HSC indicates a dominant bus state for more than tRC_det without the RXD pin doing the same, a recessive clamping situation is detected and the transceiver is forced into Silent mode. This Fail-safe mode is released by either entering Standby or Unpowered mode or if the RXD pin is showing a dominant (e.g., low) level again. See Figure 1-6.

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 9 ATA6562/3

1.3 Pin Description

The descriptions of the pins are listed in Table 1-2. TABLE 1-2: PIN FUNCTION TABLE ATA6562 ATA6563 Pin Name Description SOIC8 VDFN8 SOIC8 VDFN8 1 1 1 1 TXD Transmit data input 2 2 2 2 GND Ground 3 3 3 3 VCC Supply voltage 4 4 4 4 RXD Receive data output; reads out data from the bus lines — — 5 5 VIO Supply voltage for I/O level adapter 5 5 — — NSIL Silent mode control input (low active); 6 6 6 6 CANL Low-level CAN bus line 7 7 7 7 CANH High-level CAN bus line 8 8 8 8 STBY Standby mode control input — 9 — 9 EP Exposed Thermal Pad: Heat slug, internally connected to the GND pin.

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1.4 Typical Application

Typical Application ATA6562 Typical Application ATA6563 Note: For VDFN8 package: EP (heatslug) must always be connected to GND. Microcontroller ATA6562 VDD GND GND NSIL STBY 87 TXD RXD CANH CANL CANH CANL BAT VCC 100 nF 22 µF(1) 12V+ GND (1) The size of this capacitor depends on the used external voltage regulator Note: For VDFN8 package: EP (heatslug) must always be connected to GND. Microcontroller ATA6563 VDD GND GND TXD RXD CANH CANL CANH CANL BAT VCC 100 nF 22 µF(1) 3.3V 12V GND (1) The size of this capacitor depends on the used external voltage regulator STBY 8 VIO 100 nF 12V

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 11 ATA6562/3

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†) † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ  170°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Symbol Min. Typ. Max. Units Conditions Supply, Pin VCC Supply Voltage VVCC 4.5 — 5.5 V Supply Current in Silent Mode I VCC_sil 1.9 2.5 3.2 mA Silent mode, V TXD = VVIO Supply Current in Normal Mode IVCC_rec 2 — 5 mA Recessive, V TXD = VVIO IVCC_dom 30 50 70 mA Dominant, V TXD = 0V IVCC_short — — 85 mA Short between CANH and CANL (Note 1) Supply Current in Standby Mode IVCC_STBY — — 12 µA VCC = VIO, VTXD = VNSIL = VVIO — 7 — µA T a = 25°C (Note 3) Undervoltage Detection Threshold on Pin VCC Vuvd(VCC) 2.75 — 4.5 V I/O Level Adapter Supply, Pin VIO (only with the ATA6563) Supply Voltage on Pin VIO V VIO 2.8 — 5.5 V Supply Current on Pin VIO IVIO_rec 10 80 250 µA Normal and Silent mode Recessive, VTXD = VVIO IVIO_dom 50 350 500 µA Normal and Silent mode Dominant, VTXD = 0V IVIO_STBY — — 1 µA Standby mode Undervoltage Detection Threshold on Pin VIO Vuvd(VIO) 1.3 — 2.7 V Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter

DS20005790E-page 12  2017-2021 Microchip Technology Inc. and its subsidiaries Mode Control Input, Pin NSIL and STBY High-Level Input Voltage VIH 0.7 VVIO — V VIO +0.3 V Low-Level Input Voltage VIL –0.3 — 0.3  VVIO V Pull-Up Resistor to VCC Rpu 75 125 175 kΩ V STBY = 0V, VNSIL = 0V High-Level Leakage Current I L –2 — +2 µA V STBY = VVIO, VNSIL = VVIO CAN Transmit Data Input, Pin TXD High-Level Input Voltage VIH 0.7 VVIO — VVIO +0.3 V Low-Level Input Voltage VIL –0.3 — 0.3 VVIO V Pull-Up Resistor to VCC RTXD 20 35 50 kΩ V TXD = 0V High-Level Leakage Current I TXD –2 — +2 µA Normal mode, V TXD = VVIO Input Capacitance CTXD — 5 10 pF Note 3 CAN Receive Data Output, Pin RXD High-Level Output Current I OH –8 — –1 mA Normal mode, VRXD = VVIO – 0.4V, VVIO = VVCC Low-Level Output Current, Bus Dominant IOL 2 — 12 mA Normal mode, VRXD = 0.4V, Bus Dominant Bus Lines, Pins CANH and CANL Single Ended Dominant Output Voltage VO(dom) 2.75 3.5 4.5 V VTXD = 0V, t < tto(dom)TXD RL = 50Ω to 65Ω pin CANH (Note 1) 0.5 1.5 2.25 V VTXD = 0V, t < tto(dom)TXD RL = 50Ω to 65Ω pin CANL (Note 1) Transmitter Voltage Symmetry V Sym 0.9 1.0 1.1 — VSym = (VCANH + VCANL) / VVCC, Split Termination, RL = 2 x 30, CSplit = 4.7 nF (Note 3) Bus Differential Output Voltage VDiff 1.5 — 3 V VTXD = 0V, t < tto(dom)TXD RL = 45Ω to 65Ω 1.5 — 3.3 V R L = 70Ω (Note 3) 1.5 — 5 V R L = 2240Ω (Note 3) –50 — +50 mV Normal and Silent mode: VVCC = 4.75V to 5.25V VTXD = VVIO, recessive, no load –200 — +200 mV Standby mode: VVCC = 4.75V to 5.25V VTXD = VVIO, recessive, no load ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ  170°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Symbol Min. Typ. Max. Units Conditions Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 13 ATA6562/3 Single Ended Recessive Output Voltage VO(rec) 2 0.5  VVCC

3 V Normal and Silent mode,

VTXD = VVIO, no load –0.1 — +0.1 V Standby mode, VTXD = VVIO, no load Differential Receiver Threshold Voltage Vth(RX)dif 0.5 0.7 0.9 V Normal and Silent mode (HSC), Vcm(CAN) = –27V to +27V 0.4 0.7 1.1 V Standby mode (WUC), Vcm(CAN) = –27V to +27V (Note 1) Differential Receiver Hysteresis Voltage Vhys(RX)dif 50 120 200 mV Normal and Silent mode (HSC), Vcm(CAN) = –27V to +27V (Note 1) Dominant Output Current I IO(dom) –75 — –35 mA VTXD = 0V, t < tto(dom)TXD, VVCC = 5V pin CANH, VCANH = –5V 35 — 75 mA VTXD = 0V, t < tto(dom)TXD, VVCC = 5V pin CANL, VCANL = +40V Recessive Output Current I IO(rec) –5 — +5 mA Normal and Silent mode, VTXD = VVIO, no load, VCANH = VCANL = –27V to +32V Leakage Current IIO(leak) –5 0 +5 µA VVCC = VVIO = 0V, VCANH = VCANL = 5V –5 0 +5 µA VCC = VIO connected to GND with R = 47kΩ VCANH = VCANL = 5V (Note 3) Input Resistance Ri 9 15 28 kΩ V CANH = VCANL = 4V 9 15 28 kΩ –2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3) Input Resistance Deviation ΔR i –1 0 +1 % Between CANH and CANL VCANH = VCANL = 4V (Note 1) –1 0 +1 % Between CANH and CANL –2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3) Differential Input Resistance R i(dif) 18 30 56 kΩ V CANH = VCANL = 4V (Note 1) 18 30 56 kΩ –2V ≤ VCANH ≤ +7V, –2V ≤ VCANL ≤ +7V (Note 3) Common-mode Input Capacitance Ci(cm) — — 20 pF f = 500 kHz, CANH and CANL referred to GND (Note 3) Differential Input Capacitance C i(dif) — — 10 pF f = 500kHz, between CANH and CANL (Note 3) ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ  170°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Symbol Min. Typ. Max. Units Conditions Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter

DS20005790E-page 14  2017-2021 Microchip Technology Inc. and its subsidiaries Differential Bus Voltage Range for RECESSIVE State Detection VDiff_rec –3 — +0.5 V Normal and Silent mode (HSC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3) –3 — +0.4 V Standby mode (WUC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V(Note 3) Differential Bus Voltage Range for DOMINANT State Detection VDiff_dom 0.9 — 8.0 V Normal and Silent mode (HSC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3) 1.15 — 8.0 V Standby mode (WUC) –27V ≤ VCANH ≤ +27V, –27V ≤ VCANL ≤ +27V (Note 3) Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3 Delay Time from TXD to Bus Dominant td(TXD-busdom) 40 — 130 ns Normal mode ( Note 2) Delay Time from TXD to Bus Recessive td(TXD-busrec) 40 — 130 ns Normal mode ( Note 2) Delay Time from Bus Dominant to RXD td(busdom-RXD) 20 — 100 ns Normal mode ( Note 2) Delay Time from Bus Recessive to RXD td(busrec-RXD) 20 — 100 ns Normal mode ( Note 2) Propagation Delay from TXD to RXD tPD(TXD-RXD) 40 — 210 ns Normal mode, Rising edge at pin TXD RL = 60Ω, CL = 100 pF 40 — 200 ns Normal mode, Falling edge at pin TXD RL = 60Ω, CL = 100 pF — — 300 ns Normal mode, Rising edge at pin TXD RL = 150Ω, CL = 100 pF (Note 3) — — 300 ns Normal mode, Falling edge at pin TXD RL = 150Ω, CL = 100pF (Note 3) TXD Dominant Time-Out Time t to(dom)TXD 0.8 — 3 ms V TXD = 0V, Normal mode Bus Wake-up Time-Out Time t Wake 0.8 — 3 ms Standby mode Min. Dominant/Recessive Bus Wake-up Time tFilter 0.5 3 3.8 µs Standby mode Delay Time for Standby Mode to Normal Mode Transition tdel(stby-norm) — — 47 µs Falling edge at pin STBY Delay Time for Normal Mode to Standby Mode Transition tdel(norm-stby) — — 5 µs Rising edge at pin STBY ( Note 3) Delay Time for Normal Mode to Silent Mode Transition tdel(norm-sil) — — 10 µs Falling edge at pin NSIL STBY = LOW (Note 3) Delay time for Silent Mode to Normal Mode Transition tdel(sil-norm) — — 10 µs Rising edge at pin NSIL STBY = LOW (Note 3) ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ  170°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Symbol Min. Typ. Max. Units Conditions Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 15 ATA6562/3 Delay Time for Silent Mode to Standby Mode Transition tdel(sil-stby) — — 5 µs Rising edge at pin STBY NSIL = LOW (Note 3) Delay Time for Standby Mode to Silent Mode Transition tdel(stby-sil) — — 47 µs Rising edge at pin STBY NSIL = LOW (Note 3) Debouncing Time for Recessive Clamping State Detection tRC_det — 90 — ns V(CANH-CANL) > 900mV RXD = high (Note 3) Transceiver Timing for higher Bit Rates, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3 Recessive Bit Time on Pin RXD tBit(RXD) 400 — 550 ns Normal mode, tBit(TXD) = 500 ns RL = 60, CL = 100 pF (Note 1) 120 — 220 ns Normal mode, tBit(TXD) = 200 ns RL = 60, CL = 100 pF Recessive Bit Time on the Bus tBit(Bus) 435 — 530 ns Normal mode, tBit(TXD) = 500 ns RL = 60, CL = 100 pF (Note 1) 155 — 210 ns Normal mode, tBit(TXD) = 200 ns RL = 60, CL = 100 pF Receiver Timing Symmetry Δt Rec –65 — +40 ns Normal mode, tBit(TXD) = 500 ns ΔtRec = tBit(RXD)–tBit(Bus) RL = 60, CL = 100 pF (Note 1) –45 — +15 ns Normal mode, tBit(TXD) = 200 ns ΔtRec = tBit(RXD)–tBit(Bus) RL = 60, CL = 100 pF ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers. Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ  170°C; VVCC = 4.5V to 5.5V; RL = 60Ω, CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Symbol Min. Typ. Max. Units Conditions Note 1: 100% correlation tested 2: Characterized on samples 3: Design parameter TABLE 2-1: TEMPERATURE SPECIFICATIONS Parameters Symbol Min. Typ. Max. Units Thermal Characteristics SOIC8 Package Thermal Resistance Virtual Junction to Ambient R thvJA — 145 — K/W Thermal Shutdown of the Bus Drivers for ATA6562-GAQW1, ATA6563-GAQW1 (Grade 1) TVJsd 150 — 195 °C Thermal Shutdown of the Bus Drivers for ATA6562-GAQW0, ATA6563-GAQW0 (Grade 0) TVJsd 170 — 195 °C Thermal Shutdown Hysteresis TvJsd_hys — 15 — °C Thermal Characteristics VDFN8 Package Thermal Resistance Virtual Junction to Heat Slug RthvJC — 10 — K/W Thermal Resistance Virtual Junction to Ambient, where Heat Slug is soldered to PCB according to JEDEC RthvJA — 50 — K/W Thermal Shutdown of the Bus Drivers for ATA6562-GBQW1, ATA6563-GBQW1 (Grade 1) TVJsd 150 — 195 °C Thermal Shutdown of the Bus Drivers ATA6562-GBQW0, ATA6563-GBQW0 (Grade 0) TVJsd 170 — 195 °C Thermal Shutdown Hysteresis TvJsd_hys — 15 — °C

DS20005790E-page 16  2017-2021 Microchip Technology Inc. and its subsidiaries FIGURE 2-1: TIMING TEST CIRCUIT FOR THE ATA6562/3 CAN TRANSCEIVER FIGURE 2-2: CAN TRANSCEIVER TIMING DIAGRAM 1 TXD CANH HIGH LOW HIGH recessive LOW dominant 0.9V 0.5V CANL RXD VDiff td(TXD-busdom) td(TXD-busrec) td(busdom-RXD) tPD(TXD-RXD) tPD(TXD-RXD) td(busrec-RXD)

0.7 VIO

0.3 V,2

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 17 ATA6562/3 FIGURE 2-3: CAN TRANSCEIVER TIMING DIAGRAM 2

DS20005790E-page 18  2017-2021 Microchip Technology Inc. and its subsidiaries NOTES:

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 19 ATA6562/3

3.0 PACKAGING INFORMATION

Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead SOIC Example ATA6562 Grade 0 721 ATA6562H 1729256 Example ATA6562 Grade 1 721 ATA6562 1729256 Example ATA6563 Grade 0 721 ATA6563H 1729256 Example ATA6563 Grade 1 721 ATA6563 1729256

DS20005790E-page 20  2017-2021 Microchip Technology Inc. and its subsidiaries Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead 3 X 3 mm VDFN Example ATA6562 Grade 0 6562H 256 Example ATA6562 Grade 1 6562 256 Example ATA6563 Grade 0 6563H 256 Example ATA6563 Grade 1 6563 256

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 21 ATA6562/3

0.25 C A–B D

C SEATING PLANE TOP VIEW SIDE VIEW VIEW A–A 0.10 C 0.10 C Microchip Technology Drawing No. C04-057-OA Rev F Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] 1 2 N h h A2A A B e D E E 2E1 NOTE 5 NOTE 5 NX b

0.10 C A–B

H 0.23 (L1) L R0.13 R0.13 VIEW C SEE VIEW C NOTE 1 D

DS20005790E-page 22  2017-2021 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing No. C04-057-OA Rev F Sheet 2 of 2 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Foot Angle 0° - 8° 15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top 0.51-0.31bLead Width 0.25-0.17cLead Thickness 1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10A1Standoff --1.25A2Molded Package Thickness 1.75-- AOverall Height

1.27 BSCePitch

protrusions shall not exceed 0.15mm per side. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 4. Dimensioning and tolerancing per ASME Y14.5M Notes: Footprint L1 1.04 REF 5. Datums A & B to be determined at Datum H.

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 23 ATA6562/3 RECOMMENDED LAND PATTERN Microchip Technology Drawing C04-2057-OA Rev F BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Dimension Limits Units CContact Pad Spacing Contact Pitch MILLIMETERS

1.27 BSC

E MAX 5.40 Contact Pad Length (X8) Contact Pad Width (X8) 1.55 0.60 NOM E C SILK SCREEN 8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

DS20005790E-page 24  2017-2021 Microchip Technology Inc. and its subsidiaries /g37/g36 /g19/g17/g20/g19/g38 /g19/g17/g20/g19/g38 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g19/g24/g38 /g11/g39/g36/g55/g56/g48/g3/g37/g12 /g11/g39/g36/g55/g56/g48/g3/g36/g12 /g38 /g54/g40/g36/g55/g44/g49/g42 /g51/g47/g36/g49/g40 /g20/g21 /g49 /g21/g59 /g55/g50/g51/g3/g57/g44/g40/g58 /g54/g44/g39/g40/g3/g57/g44/g40/g58 /g37/g50/g55/g55/g50/g48/g3/g57/g44/g40/g58 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38/g36/g37 /g19/g17/g20/g19/g38 /g19/g17/g19/g27/g38 /g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g55/g72/g70/g75/g81/g82/g79/g82/g74/g92/g3/g39/g85/g68/g90/g76/g81/g74/g3/g3/g38/g19/g23/g16/g21/g20/g22/g24/g27/g3/g53/g72/g89/g3/g39/g3/g54/g75/g72/g72/g87/g3/g20/g3/g82/g73/g3/g21 /g21/g59 /g27/g59 /g41/g82/g85/g3/g87/g75/g72/g3/g80/g82/g86/g87/g3/g70/g88/g85/g85/g72/g81/g87/g3/g83/g68/g70/g78/g68/g74/g72/g3/g71/g85/g68/g90/g76/g81/g74/g86/g15/g3/g83/g79/g72/g68/g86/g72/g3/g86/g72/g72/g3/g87/g75/g72/g3/g48/g76/g70/g85/g82/g70/g75/g76/g83/g3/g51/g68/g70/g78/g68/g74/g76/g81/g74/g3/g54/g83/g72/g70/g76/g73/g76/g70/g68/g87/g76/g82/g81/g3/g79/g82/g70/g68/g87/g72/g71/g3/g68/g87 /g75/g87/g87/g83/g29/g18/g18/g90/g90/g90/g17/g80/g76/g70/g85/g82/g70/g75/g76/g83/g17/g70/g82/g80/g18/g83/g68/g70/g78/g68/g74/g76/g81/g74 /g49/g82/g87/g72/g29 /g27/g16/g47/g72/g68/g71/g3/g57/g72/g85/g92/g3/g55/g75/g76/g81/g3/g51/g79/g68/g86/g87/g76/g70/g3/g39/g88/g68/g79/g3/g41/g79/g68/g87/g15/g3/g49/g82/g3/g47/g72/g68/g71/g3/g51/g68/g70/g78/g68/g74/g72/g3/g11/g52/g27/g37/g12/g3/g16/g3/g22/g91/g22/g91/g20/g3/g80/g80/g3/g37/g82/g71/g92/g3/g62/g57/g39/g41/g49/g64 /g58/g76/g87/g75/g3/g21/g17/g23/g19/g91/g20/g17/g25/g19/g3/g80/g80/g3/g40/g91/g83/g82/g86/g72/g71/g3/g51/g68/g71/g3/g68/g81/g71/g3/g54/g87/g72/g83/g83/g72/g71/g3/g58/g72/g87/g87/g68/g69/g79/g72/g3/g41/g79/g68/g81/g78/g86/g30/g3/g36/g87/g80/g72/g79/g3/g47/g72/g74/g68/g70/g92/g3/g60/g38/g47 /g39 /g40 /g49/g50/g55/g40/g3/g20 /g11/g36/g22/g12 /g36 /g36/g20 /g20/g21 /g49 /g39/g21 /g40/g21 /g49/g50/g55/g40/g3/g20 /g47 /g46 /g72 /g27/g59/g3/g69 /g36 /g36

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 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 27 ATA6562/3 APPENDIX A: REVISION HISTORY Revision E (December 2021) The following is the list of modifications:

Updated the SOIC and VDFN package drawings in Section 3.0 “Packaging Information”
Minor typographical edits Revision D (June 2020) The following is the list of modifications:
Updated parameter “Supply Current in Silent Mode” in Table : Electrical Characteristics
Added test conditions at several parameters in Table : Electrical Characteristics
Added parameter “Bus Differential Output Volt- age” in Standby mode in Table : Electrical Charac- teristics
Updated Package Marking Information Revision C (August 2019) The following is the list of modifications:
Updated Table 2-1: Temperature Specifications
Added test conditions at several parameters in Table : Electrical Characteristics Revision B (August 2017) The following is the list of modifications:
Added new devices ATA6562-GBQW0 and ATA6563-GBQW0 and updated the related infor- mation across the document
Updated Features section
Updated ATA6562/3 Family Members section
Updated Table 2-1: Temperature Specifications
Updated Package Marking Information
Updated Product Identification System section
Various typographical edits Revision A (June 2017)
Original release of this document
This document replaces Atmel – 9389C- 11/16ATA6562/3

DS20005790E-page 28  2017-2021 Microchip Technology Inc. and its subsidiaries NOTES:

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 29 ATA6562/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: a) ATA6562-GAQW0: ATA6562 , 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 0 b) ATA6562-GAQW1: ATA6562, 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 1 c) ATA6562-GBQW0: ATA6562, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 0 d) ATA6562-GBQW1: ATA6562, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 1 e) ATA6563-GAQW0: ATA6563 , 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 0 f) ATA6563-GAQW1: ATA6563, 8-Lead SOIC, Tape and Reel, Package according to RoHS, Temperature Grade 1 f) ATA6563-GBQW0: ATA6563, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 0 g ATA6563-GBQW1: ATA6563, 8-Lead VDFN, Tape and Reel, Package according to RoHS, Temperature Grade 1 PART NO. X Package directivesDevice Device: ATA6562: High-speed CAN Transceiver with Standby and Silent Mode CAN FD Ready ATA6563: High-speed CAN Transceiver with Standby Mode and VIO-pin CAN FD Ready Package: GA = 8-Lead SOIC GB = 8-Lead VDFN Tape and Reel Option: Q = 330 mm diameter Tape and Reel Package directives classification: W = Package according to RoHS (2) Temperature Range: 0 = Temperature Grade 0 (-40°C to +150°C) 1 = Temperature Grade 1 (-40°C to +125°C) XX Package X Temperature Range X Tape and Reel Option classification Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: RoHS compliant, Maximum concentration value of 0.09% (900 ppm) for Bromine (Br) and Chlorine (Cl) and less than 0.15% (1500 ppm) total Bromine (Br) and Chlorine (Cl) in any homogeneous material. Maximum concentration value of 0.09% (900 ppm) for Antimony (Sb) in any homogeneous material.

DS20005790E-page 30  2017-2021 Microchip Technology Inc. and its subsidiaries NOTES:

 2017-2021 Microchip Technology Inc. and its subsidiaries DS20005790E-page 31 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY , AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY , OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSE - QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY , THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017-2021, Microchip Technology Incorporated and its subsidiar- ies. All Rights Reserved. ISBN: 978-1-5224-9513-0 Note the following details of the code protection feature on Microchip products:

Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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Product Information

ATA6562 specifications and overview.

Summary

High-Speed CAN Transceiver with Standby Mode 09/14/21

Description

High-Speed CAN Transceiver with Standby Mode 09/14/21

Source title ATA6562 Datasheet(PDF) - Microchip Technology

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