Memory

AT28C010E-12UM

Microchip Technology

Military Grade 1-Mbit (131,072 x 8) Paged Parallel EEPROM 2020

Manufacturer: Microchip Technology

Document: 31 Pages / 524Kb

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Technical content

Features

Fast Read Access Time: 120 ns
Automatic Page Write Operation: – Internally organized as 131,072 x 8 (1 Mbit) – Internal address and data latches for 128 bytes – Internal control timer
Fast Write Cycle Time: – Page Write cycle time: 10 ms maximum – 1 to 128-byte Page Write operation
Low-Power Dissipation: – 80 mA active current – 300 µA CMOS standby current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology: – Endurance: 10,000 or 100,000 cycles – Data retention: 10 years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout Packages
32-Lead CERDIP, 32-Lead Flatpack, 32-Lead CLCC and 30-Pin PGA © 2020 Microchip Technology Inc. DS20006311A-page 1

Package Types (not to scale) NC A16 A15 A12 I/O0 I/O1 I/O2 GND VCC WE NC A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O5 32-Lead FLATPACK Top View NC A16 A15 A12 I/O0 I/O1 I/O2 GND VCC WE NC A14 A13 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 32-Lead CERDIP Top View I/O0 A14 A13 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A12 A15 A16 NC VCC WE NC 32-Lead CLCC Top View 30-Pin PGA Top View A14 A6 A7 WP A13 A5 A12 VCC A8 A3 A15 OE A11 A1 A2 A16 CE A10 I/O0 A0 GND I/O4 I/O7 I/O1 I/O2 I/O3 I/O5 I/O6 AT28C010 Package Types (not to scale) © 2020 Microchip Technology Inc. DS20006311A-page 4

Pin Descriptions The descriptions of the pins are listed in Table 2-1. Table 2-1. Pin Function Table Name 32‑ Lead CERDIP 32-Lead CLCC 32-Lead FLATPACK 30‑ Pin PGA Function NC 1 1 1 — No Connect A16 2 2 2 30 Address A15 3 3 3 29 Address A12 4 4 4 2 Address A7 5 5 5 3 Address A6 6 6 6 4 Address A5 7 7 7 5 Address A4 8 8 8 6 Address A3 9 9 9 7 Address A2 10 10 10 8 Address A1 11 11 11 9 Address A0 12 12 12 10 Address I/O0 13 13 13 11 Data Input/Output I/O1 14 14 14 12 Data Input/Output I/O2 15 15 15 13 Data Input/Output GND 16 16 16 14 Ground I/O3 17 17 17 15 Data Input/Output I/O4 18 18 18 16 Data Input/Output I/O5 19 19 19 17 Data Input/Output I/O6 20 20 20 18 Data Input/Output I/O7 21 21 21 19 Data Input/Output CE 22 22 22 20 Chip Enable A10 23 23 23 21 Address OE 24 24 24 22 Output Enable A11 25 25 25 23 Address A9 26 26 26 24 Address A8 27 27 27 25 Address A13 28 28 28 26 Address A14 29 29 29 1 Address NC 30 30 30 — No Connect WE 31 31 31 27 Write Enable VCC 32 32 32 28 Device Power Supply AT28C010 Pin Descriptions © 2020 Microchip Technology Inc. DS20006311A-page 5

Description The AT28C010 is a high‑ performance Electrically Erasable and Programmable Read‑ Only Memory (EEPROM). Its 1‑ Mb memory is organized as 131,072 words by 8 bits. Manufactured with Microchip’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300 µA. The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128‑ byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. The AT28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking.

3.1 Block Diagram

OE, CE and WE Logic GND OE WE CE I/O0-I/O7 AT28C010

Description

Electrical Characteristics

4.1 Absolute Maximum Ratings

Temperature under bias -55°C to +125°C Storage temperature -65°C to +150°C All input voltages (including NC pins) with respect to ground -0.6V to +6.25V All output voltages with respect to ground -0.6V to VCC + 0.6V Voltage on OE and A9 with respect to ground -0.6V to +13.5V Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range AT28C010‑ 12 AT28C010‑ 15 AT28C010‑ 20 AT28C010‑ 25 Operating Temperature (Case) Military -55°C to +125°C -55°C to +125°C -55°C to +125°C -55°C to +125°C VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

4.3 DC Characteristics

Table 4-2. DC Characteristics Parameter Symbol Minimum Maximum Units Test Conditions Input Load Current ILI — 10 μA VIN = 0V to VCC + 1V Output Leakage Current ILO — 10 μA VI/O = 0V to VCC VCC Standby Current CMOS ISB1 — 300 μA CE = VCC - 0.3V to VCC + 1V VCC Standby Current TTL ISB2 — 3 mA CE = 2.0V to VCC + 1V VCC Active Current ICC — 80 mA f = 5 MHz; IOUT = 0 mA Input Low Voltage VIL — 0.8 V Input High Voltage VIH 2.0 — V Output Low Voltage VOL — 0.45 V IOL = 2.1 mA Output High Voltage VOH1 2.4 — V IOH = -400 μA Output High Voltage CMOS VOH2 4.2 — V IOH = -100 μA; VCC = 4.5V AT28C010

Electrical Characteristics

4.4 Pin Capacitance

Table 4-3. Pin Capacitance(1,2) Symbol Typical Maximum Units Conditions CIN 4 10 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 1. This parameter is characterized but is not 100% tested in production. 2. f = 1 MHz, T A = 25°C AT28C010 © 2020 Microchip Technology Inc. DS20006311A-page 8

Device Operation READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high- impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write is started, it will automatically time itself to completion. Once a programming operation is initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7‑ A16 inputs. For each WE high‑ to‑ low transition during the page write operation, A7‑ A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling, the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Microchip incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C010 in the following ways:

V CC sense – if VCC is below 3.8V (typical), the write function is inhibited
V CC power‑ on delay – once VCC has reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a write
write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles
noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP) will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3‑ byte command sequence and after tWC, the entire AT28C010 will be protected against inadvertent write operations. It should be noted that, once protected, the host may still perform a byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3‑ byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during power‑ up and power‑ down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 9

After setting SDP, any attempt to write to the device without the 3‑ byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 128 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH, the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6‑ byte software code. See Software Chip Erase application note for details.

5.1 Operating Modes

Table 5-1. Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT Write(1) VIL VIH VIL DIN Standby/Write Inhibit VIH X(2) X High-Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High-Z Note: 1. Refer to AC Programming Waveforms. 2. X can be V IL or VIH.

5.2 AC Read Characteristics

Table 5-2. AC Read Characteristics Parameter Symbol AT28C010‑ 12 AT28C010‑ 15 AT28C010‑ 20 AT28C010‑ 25 Units Address to Output Delay tACC — 120 — 150 — 200 — 250 ns CE to Output Delay tCE(1) — 120 — 150 — 200 — 250 ns OE to Output Delay tOE(2) 0 50 0 55 0 55 0 55 ns CE or OE to Output Float tDF(3,4) 0 50 0 55 0 55 0 55 ns Output Hold from OE, CE or Address, whichever occurred first tOH 0 0 0 0 ns CE Pulse High Time tCEPH(5) 50 — 50 — 50 — 50 — ns AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 10

Note: 1. CE may be delayed up to tACC‑ tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE‑ tOE after the falling edge of CE without impact on tCE or by tACC‑ tOE after an address change without impact in tACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 5. If CE is de-asserted, it must remain de-asserted for at least 50 ns during read operations, otherwise incorrect data may be read.

5.3 AC Read Waveforms

5.4 Input Test Waveforms and Measurement Level

3.0V 0.0V 1.5V

5.5 Output Test Load

5.6 AC Write Characteristics

Table 5-3. AC Write Characteristics Parameter Symbol Minimum Maximum Units Write Cycle Time tWC — 10 ms Address Set-Up Time tAS 0 — ns Address Hold Time tAH 50 — ns Data Set-Up Time tDS 50 — ns Data Hold Time tDH 0 — ns Write Pulse Width tWP 100 — ns Byte Load Cycle Time tBLC — 150 µs Write Pulse Width High tWPH 50 — ns

5.7 AC Write Waveforms

5.7.1 WE Controlled

5.7.2 CE Controlled

5.8 Page Mode Characteristics

Table 5-4. Page Mode Characteristics Parameter Symbol Minimum Maximum Units Address, OE Set-Up Time tAS, tOES 0 — ns Address Hold Time tAH 50 — ns Chip Select Set-Up Time tCS 0 — ns Chip Select Hold Time tCH 0 — ns Write Pulse Width (WE or CE) tWP 100 — ns Data Set-Up Time tDS 50 — ns Data, OE Hold Time tDH, tOEH 0 — ns AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 13

5.9 Page Mode Write Waveforms(1,2)

BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 126 BYTE 127 Note: 1. A7 through A16 must specify the page address during each high-to-low transition of WE (or CE). 2. OE must be high only when WE and CE are both low.

5.10 Chip Erase Waveforms

(3) OE VIH VIH VIL WE tS (1) tW (2) tH Note: 1. t S = 5 msec (minimum) 2. t W = tH = 10 msec (minimum) 3. V H = 12.0V ± 0.5V AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 14

5.11 Software Data Protection Enable Algorithm(1)

ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE WRITES ENABLED(2) Note: 1. Data format: I/O7-I/O0 (Hex); Address format: A16-A0 (Hex). 2. Write-Protect state will be activated at end of write even if no other data is loaded. 3. 1 to 128 bytes of data are loaded. AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 15

5.12 Software Data Protection Disable Algorithm(1)

PROTECT STATE(2) LOAD DATA XX TO ANY ADDRESS(3) Note: 1. Data format: I/O7-I/O0 (Hex); Address format: A16-A0 (Hex). 2. Write-Protect state will be deactivated at end of write period even if no other data is loaded. 3. 1 to 128 bytes of data are loaded. AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 16

5.13 Software Protected Program Cycle Waveform(1,2,3)

Note: 1. A0-A16 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7‑ A16) must be the same for each high‑ to‑ low transition of WE (or CE). 3. OE must be high only when WE and CE are both low.

5.14 Data Polling Characteristics(1)

Table 5-5. Data Polling Characteristics Parameter Symbol Minimum Typical Maximum Units Data Hold Time tDH 10 — — ns OE Hold Time tOEH 10 — — ns OE to Output Delay(2) tOE — — — ns Write Recovery Time tWR 0 — — ns Note: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 17

5.15 Data Polling Waveforms

5.16 Toggle Bit Characteristics(1)

Table 5-6. Toggle Bit Characteristics Parameter Symbol Minimum Typical Maximum Units Data Hold Time tDH 10 — — ns OE Hold Time tOEH 10 — — ns OE to Output Delay(2) tOE — — — ns OE High Pulse(2) tOEHP 150 — — ns Write Recovery Time tWR 0 — — ns Note: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

5.17 Toggle Bit Waveforms

Note: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 19

Packaging Information

6.1 Package Marking Information

AT28C010: Package Marking Information (SMD devices) ## = Device Number %% = Access Time $ = Assembly Location 01: 250 ns 25: 250 ns F: Philippines 03: 200 ns 20: 200 ns N: Thailand 05: 150 ns 15: 150 ns 07: 120 ns 12: 120 ns Country of Assembly Lot Trace Code Seal Year and Work Week &&&&&&: Country of Assembly YWWNNN: Lot Trace Code YYWW: Seal Year and Work Week Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) YQyywwl: Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) 32-Pin CERDIP ##MXA C AT28C010 %%DM/883 YQyywwl 5962-38267 ATMEL YYWW YWWNNN-19506V Topside Backside 32-Pad LCC ##MUA YQyywwl AT28C010 %%EM/883 C 5962-38267 ATMEL YYWW 19506 YWWNNNV Topside Backside 32-Pin FLATPACK ##MZA C AT28C010 %%FM/883 YQyywwl 5962-38267 ATMEL YYWW YWWNNN-19506V Topside Backside 32-Pin PGA ##MTA YQyywwl AT28C010 %%UM/883 C 5962-38267 Topside Edges YQNNNN-19506V Δ Δ Δ Δ AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 20

AT28C010E: Package Marking Information (Non-SMD devices) %% = Access Time CAGE Code $ = Assembly Location 25: 250 ns 0HSW3 F: Philippines 20: 200 ns N: Thailand 15: 150 ns 12: 120 ns Country of Assembly Lot Trace Code Seal Year and Work Week &&&&&&: Country of Assembly YWWNNN: Lot Trace Code YYWW: Seal Year and Work Week Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) YQyywwl: Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) 32-Pin CERDIP %%DM/883 C 0HSW3 YQyywwl AT28C010E ATMEL YYWW YWWNNN-19506V Topside Backside 32-Pad LCC %%EM/883 C OHSW3 YQyywwl AT28C010E ATMEL YYWW 19506 YWWNNNV Topside Backside 32-Pin FLATPACK %%FM/883 C 0HSW3 YQyywwl AT28C010E ATMEL YYWW YWWNNN-19506V Topside Backside 32-Pin PGA %%UM/883 C 0HSW3 YQyywwl AT28C010E ATMEL YWWNNN-19506V Topside Edges Δ Δ Δ Δ 19506 YYWW AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 21

TITLE DRAWING NO. REV. 32D6, 32-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) B32D6 10/23/03 42.70(1.68) 41.70(1.64) PIN 15.50(0.610) 13.00(0.510) 2.49(0.098)MAX 0.127(0.005)MIN 1.52(0.060) 0.38(0.015) 0.58(0.023) 0.36(0.014) 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 17.80(0.700) MAX 0.381(0.015) 0.203(0.008) 2.54(0.100)BSC 5.08(0.200) 3.18(0.125) SEATING PLANE 5.72(0.225) MAX 38.10(1.500) REF 0º~ 15º REF Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-16 Config A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 22

TITLE DRAWING NO. REV. 32L1, 32-pad, Non-windowed, Combo Lid, Leadless Chip Carrier (LCC) B32L1 10/21/03 Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 14.22(0.560) 13.72(0.540) 2.29(0.090) 1.91(0.075) 1.91(0.075) 1.40(0.055) INDEX CORNER 0.635(0.025) 0.381(0.015) X 45° 0.305(0.012) 0.178(0.007)RADIUS 0.737(0.029) 0.533(0.021) 1.02(0.040) X 45° PIN 1 1.40(0.055) 1.91(0.075) 2.16(0.085) 1.27(0.050) TYP 10.16(0.400) BSC Note: For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 23

TITLE DRAWING NO. REV. 32F, 32-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) B32F 10/21/03 Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Outline MO-115 AA PIN #1 ID 9.40(0.370) 6.86(0.270) 0.51(0.020) 0.38(0.015) 1.27(0.050) BSC 1.14(0.045) MAX 3.05(0.120) 2.49(0.098) 1.14(0.045) 0.66(0.026) 1.83(0.072) 0.76(0.030) 10.36(0.408) 9.02(0.355) 0.18(0.007) 0.10(0.004) 12.40(0.488) 11.99(0.472) 21.08(0.830) 20.60(0.811) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 24

TITLE DRAWING NO. REV. 30U, 30-pin, Ceramic Pin Grid Array (PGA) B30U 10/21/03 Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 13.74(0.541) 13.36(0.526) 16.18(0.637) 15.82(0.623) 2.57(0.101) 2.06(0.081) 7.26(0.286) 6.50(0.256) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 12.70(0.500) TYP 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. AT28C010 Packaging Information © 2020 Microchip Technology Inc. DS20006311A-page 25

Revision History Revision A (March 2020) Updated to the Microchip template. Microchip DS20006311 replaces Atmel document 0010. Added updated Part Markings to include new trace code format. Atmel Document 0010 Revision I (June 2015) Added Revision History section. Updated AC Characteristics and ordering information. AT28C010

Revision History

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Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: http://www.microchip.com/support AT28C010 © 2020 Microchip Technology Inc. DS20006311A-page 27

Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. AT28 = Parallel EEPROM C = 4.5V to 5.5V /883 = MIL-STD-883 Class B Product M = -55°C to +125°C Military Temperature Grade, Sn63/Pb37 Terminal Finish AT28C010 (E)- 20 EM/883 010 = 1 Mbit Size E = 100K Extended Write Endurance Option 12 = 120 ns Speed 15 = 150 ns Speed 20 = 200 ns Speed 25 = 250 ns Speed WM = Die Sales (contact Microchip) DWFM = Wfer Sales (contact Microhip) D = 32-Lead, 600 mil Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) E = 32-Pad, Non-Windowed, Combo Lid, Leadless Chip Carrier (LCC) F = 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) U = 30-Pin, Ceramic Pin Grid Array (PGA) Blank = 10K Standard Write Endurance Examples Table 11-1. AT28C010 Ordering Information Ordering Code Standard Military Drawing Number (SMD#) Package Number tACC(ns) Operating Range AT28C010-12DM/883 5962-38267 07 MXA 32D6 120 Military/883C Class B, Fully Compliant (-55°C to 125°C) AT28C010-12EM/883 5962-38267 07 MUA 32L1 AT28C010-12FM/883 5962-38267 07 MZA 32F AT28C010-12UM/883 5962-38267 07 MTA 30U AT28C010-15DM/883 5962-38267 05 MXA 32D6 150 AT28C010-15EM/883 5962-38267 05 MUA 32L1 AT28C010-15FM/883 5962-38267 05 MZA 32F AT28C010-15UM/883 5962-38267 05 MTA 30U AT28C010-20DM/883 5962-38267 03 MXA 32D6 200 AT28C010-20EM/883 5962-38267 03 MUA 32L1 AT28C010-20FM/883 5962-38267 03 MZA 32F AT28C010-20UM/883 5962-38267 03 MTA 30U AT28C010-12DM/883 5962-38267 01 MXA 32D6 250 AT28C010-12FM/883 5962-38267 01 MZA 32F AT28C010-WM None Die Sales Note 1 AT28C010-DWFM None Wafer Sales Note 1 Note: 1. Contact Microchip Sales for Die and Wafer sales AT28C010 © 2020 Microchip Technology Inc. DS20006311A-page 28

Table 11-2. AT28C010E Ordering Information Ordering Code Standard Military Drawing Number (SMD#) Package Number tACC(ns) Operating Range AT28C010E-12DM/883 None 32D6

120 Military/883C Class B,

Fully Compliant (-55°C to 125°C) AT28C010E-12EM/883 None 32L1 AT28C010E-12FM/883 None 32F AT28C010E-12UM/883 None 30U AT28C010E-15DM/883 None 32D6 150 Package Types 32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L1 32-Pad, Non-Windowed, Combo Lid, Leadless Chip Carrier (LCC) 30U 30-Pin, Ceramic Pin Grid Array (PGA) WM Diced Die Military DWFM Die in Wafer Form Military Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time 10 ms E High Endurance Option: Endurance = 100K Write Cycles Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AT28C010 © 2020 Microchip Technology Inc. DS20006311A-page 29

INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-5748-0 AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Quality Management System For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality. AT28C010 © 2020 Microchip Technology Inc. DS20006311A-page 30

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Product Information

AT28C010E-12UM specifications and overview.

Summary

Military Grade 1-Mbit (131,072 x 8) Paged Parallel EEPROM 2020

Description

Military Grade 1-Mbit (131,072 x 8) Paged Parallel EEPROM 2020

Source title AT28C010E-12UM Datasheet(PDF) - Microchip Technology

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