ASX340AT_16 ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 54
Technical content
Features
- Low-Power CMOS Image Sensor with Integrated Image Flow Processor (IFP) and Video Encoder
- 1/4-inch Optical Format, VGA Resolution (640 H x 480 V)
- 2x Upscaling Zoom and Pan Control
- ±40 Additional Columns and ± 36 Additional Rows to Compensate for Lens Alignment Tolerances
- Option to Use Single 2.8 V Power Supply with Off-Chip Bypass Transistor
- Overlay Generator for Dynamic Bitmap Overlay
- Integrated Video Encoder for NTSC/PAL with Overlay Capability and 10-bit I-DAC
- Integrated Microcontroller for Flexibility
- On-Chip Image Flow Processor Performs Sophisticated Processing, Such as Color Recovery and Correction, Sharpening, Gamma, Lens Shading Correction, On-the-Fly Defect Correction, Auto White Balancing, and Auto Exposure www.onsemi.com See detailed ordering and shipping information on page 3 of this data sheet.
ORDERING INFORMATION
IBGA63 7.5 /C0121 7.5 CASE 503AE
- Auto Black-Level Calibration
- 10-Bit, On-Chip Analog-to-Digital Converter (ADC)
- Internal Master Clock Generated by On-Chip Phase-Locked Loop (PLL)
- Two-Wire Serial Programming Interface
- Interface to Low-Cost EEPROM and Flash through SPI Bus
- High-Level Host Command Interface
- Stand-Alone Operation Support
- Comprehensive Tool Support for Overlay Generation and Lens Correction Setup
- Development System with DevWare
Applications
- Automotive Rear View Camera and Side Mirror
- Blind Spot and Surround View
TABLE 1. KEY PARAMETERS
www.onsemi.com TABLE 1. KEY PARAMETERS (CONTINUED)
- Temperature sensor for dynamic feedback and sensor control
- Automatic 50 Hz/60 Hz flicker detection
- 2x upscaling zoom and pan/tilt control
- Independent control of colorburst parameters in the NTSC/PAL encoder
- Horizontal field of view adjustment between 700 and 720 pixels on the analog output
- Option to use single 2.8 V power supply with off-chip bypass transistor
- SPI EEPROM support for lower cost system design.
TABLE 2. AVAILABLE PART NUMBERS evaluation kits, please visit our web site at www.onsemi.com.
The system block diagram will depend on the application. with the ASX340AT through its two-wire serial bus. Optional components will vary by application. Figure 1. System Block Diagram
27.000 MHz
Figure 2. Internal Block Diagram temperature compensation is recommended. Figure 3. Using a Crystal Instead of an External Oscillator NOTE: Value of load capacitor is crystal dependent. Crystal with small load capacitor is recommended.
TABLE 3. PIN DESCRIPTION connected directly to a crystal. signal must be left unconnected. device will return all interfaces to their reset state. sequence. This signal has an internal pull-up resistor. ASX340AT to a fixed point in the frame. serial communication commands. this interface and processed externally. alternate (GPIO) function is enabled for these pins. This interface is disabled by default. The slew rate of these outputs is programmable. these outputs is programmable.
TABLE 3. PIN DESCRIPTION (CONTINUED) F5 DAC_POS Output Positive video DAC output in differential mode. a power-down state under software control. G5 DAC_NEG Output Negative video DAC output in differential mode. A4 DAC_REF Output External reference resistor for the video DAC. C4 TRST_N Input Connect to GND. C1 GPIO12 Input/Output Dedicated general-purpose input/output pin. A3 GPIO13 Input/Output Dedicated general-purpose input/output pin. G4 VREG_BASE Supply Voltage regulator control. Leave floating if not used. transistor or an external 1.8 V power supply. B2, B8, C8, E3, E8, G8, H8 VDD_IO Supply Supply for digital IOs: 2.8 V nominal. H5 VDD_DAC Supply Supply for video DAC: 2.8 V nominal. A8 VDD_PLL Supply Supply for PLL: 2.8 V nominal. B4, H6 VAA Supply Analog power: 2.8 V nominal. same voltage potential as VAA. H4 Reserved Leave floating for normal operation. B5, C5, D1, D5, H1 DGND Supply Digital ground. E5, F4 AGND Supply Analog ground.
to be identified by an additional marking. TABLE 4. PIN ASSIGNMENTS TABLE 5. RESET/DEFAULT STATE OF INTERFACES a pull-up resistor in the range of 1.5 to 4.7 kΩ. a pull-up resistor in the range of 1.5 to 4.7 kΩ. SPI_SCLK High impedance. Driven, logic 0 Output. Output enable is R0x0032[13]. SPI_SDI Internal pull-up enabled. Internal pull-up enabled Input. Internal pull-up is permanently enabled. SPI_SDO High impedance Driven, logic 0 Output enable is R0x0032[13]. SPI_CS_N High impedance Driven, logic 1 Output enable is R0x0032[13]. PIXCLK High impedance Driven, logic 0 Output. This interface disabled by default.
TABLE 5. RESET/DEFAULT STATE OF INTERFACES (CONTINUED) DOUT_LSB1 High impedance High impedance Input/Output. This interface disabled by default. left unconnected (floating). left unconnected (floating). left unconnected (floating). level. Must be driven to GND if not used. GPIO12 High impedance High impedance Input/Output. This interface disabled by default. GPIO13 High impedance High impedance Input/Output. This interface disabled by default. ATEST1 N/A N/A Must be driven to GND for normal operation. ATEST2 N/A N/A Must be driven to GND for normal operation.
- The reason for defining the default state as logic 0 rather than high impedance is this: when wired in a system (for example, on ON
level. No current drain should result from driving these to a valid logic level (unless there is a pull-up at the system level).
- These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they can be left floating but they will not
drive a valid logic level to an attached device.
and vertical blanking, shown in Figure 8. 640 to 720 pixels. The vertical size is 288 pixels per field. Figure 8. Spatial Illustration on Image Readout
Figure 9. Color Pipeline test patterns sufficient for basic testing of the pipeline.
Cb and Cr values for each bar are detailed in Tables 6 and 7. Figure 10. Color Pipeline TABLE 6. EIA COLOR BARS (NTSC) TABLE 7. EBU COLOR BARS (PAL) generated 656 data are summarized in Tables 8 and 9. TABLE 8. NTSC TABLE 9. PAL
TABLE 9. PAL (CONTINUED) the value of this pixel is set to 0. individual R, Gb, Gr., and B color signal. correction functions for each color channel. edge threshold can be set through register settings. correction can be defined through register settings. a brighter lighting condition and a darker lighting condition. interpolated version of the two tables. ordinates are programmable through registers.
Figure 11. Gamma Correction Curve color space to YUV color space. difference between their luminance and the threshold. is possible. A 3- or 5-tap filter can be selected for each signal. to an alternative YUV or RGB data format. TABLE 10. YCbCr OUTPUT DATA ORDERING TABLE 11. RGB ORDERING IN DEFAULT MODE
- Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least significant 2 bits of data.
- Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 12.
TABLE 12. 2-BYTE BAYER FORMAT Progressive format is used for raw Bayer output. YCbCr 4:2:2 data with embedded synchronization codes. standard video equipment or JPEG/MPEG compression. LINE_V ALID and FRAME_V ALID. RGB (444RGB). Refer to Table 23 and Table 24 for details. the on-chip video encoder output. output is used for raw Bayer output. support is limited to the VGA at either 60 fps or 50 fps. “width” of the TV output line, between 692 and 720 pixels. pixels width, and has to be an even number of pixels.
the data in various formats. Figure 18. External Signal Processing Block Diagram
27 MHz
Flash/EEPROM Config, Auto Config, and Host Config.
- Change-Config (commences streaming −
completes the System Configuration mode).
- If no device is detected, the firmware then samples the SPI_SDI pin state to determine the next mode: − If SPI_SDI = 0 then it enters the Host-Config mode. − If SPI_SDI = 1 then it enters the Auto-Config mode.
- If a device is detected, the firmware switches to the Flash-Config mode. In the Flash-Config phase, the firmware interrogates the device to determine if it contains valid configuration records:
- If no records are detected, then the firmware enters the Auto-Config mode.
- If records are detected, the firmware processes them. By default, when all Flash records are processed the firmware switches to the Host-Config mode. However, the records encoded into the Flash can optionally be used to instruct the firmware to proceed to one of the other mode (auto-config/change-config). The Auto-Config mode uses the FRAME_V ALID, LINE_V ALID, D OUT_LSB0 and D OUT_LSB1 pins to configure the operation of the device, such as video format and pedestal (refer to the Developer Guide for more details). After Auto-Config completes the firmware switches to the Change-Config mode. In the Host-Config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. The System Configuration phase is effectively complete and the SOC will take no actions until the host issues commands. In the Change-Config mode, the firmware performs a “Change-Config” operation. This applies the current configuration settings to the SOC, and commences streaming. This completes the System Configuration phase.
Figure 19. Power-Up Sequence – Configuration Options Flow Chart TABLE 13. SPI FLASH DEVICES
TABLE 14. SPI COMMANDS SUPPORTED TABLE 15. GPIO BIT DESCRIPTIONS command is written into the SOC and executed. ASX340A T Host Command Interface Specification.
Figure 20. Interface Structure
Figure 21. Interface Structure signals the Command Handler task to process the command. cleared before issuing a command. consult the Host Command Interface Specification. initiated in the form of a “Preset” follows.
and test the doorbell bit after issuing the command. before issuing the next command.
- System Manager
- Overlay
- GPIO
- Flash Manager
- Sequencer
- Patch Loader
- Miscellaneous
- Calibration Stats Following is a summary of the Host Interface commands. The description gives a quick orientation. The “Type” column shows if it is an asynchronous or synchronous command. For a complete list of all commands including parameters, consult the Host Command Interface Specification document.
TABLE 16. SYSTEM MANAGER COMMANDS TABLE 17. OVERLAY HOST COMMANDS
TABLE 17. OVERLAY HOST COMMANDS (CONTINUED) TABLE 18. GPIO HOST COMMANDS TABLE 19. FLASH MANAGER HOST COMMANDS TABLE 20. SEQUENCER HOST COMMANDS
TABLE 21. PATCH LOADER HOST COMMANDS TABLE 22. MISCELLANEOUS HOST COMMANDS TABLE 23. CALIBRATION STATS HOST COMMANDS access to control and status registers within the ASX340AT. protocols of the two-wire serial interface specification. is an input to the sensor and used to synchronize transfers. off-chip by a pull-up resistor in the range of 1.5 to 4.7 kΩ.
- a start or restart condition
- a slave address/data direction byte
- a 16-bit register address
- an acknowledge or a no-acknowledge bit
- data bytes
- a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0 x 90; if SADDR is HIGH, the slave address is 0 x BA. See Table 21.
TABLE 24. TWO-WIRE INTERFACE ID ADDRESS start” or “restart” condition.
must operate at a certain minimum speed. TABLE 25. TRANSFER TIME ESTIMATE
- The overlay statistics engine supports a windowed 8-bin luma histogram, either row-wise (vertical) or column-wise (horizontal).
- The calibration statistics can be used to perform an automatic successive-approximation search of a cross-hair target within the scene.
- On the first frame, the firmware performs a coarse horizontal search, followed by a coarse vertical search in the second frame.
- In subsequent frames, the firmware reduces the region-of-interest of the search to the histogram bins containing the greatest accumulator values, thereby refining the search.
- The resultant row and column location of the cross-hair target can be used to assign a calibration value to offset selected overlay graphic image positions within the output image.
- The calibration statistics patch also supports a manual mode, which allows the host to access the raw accumulator values directly.
Figure 30. Overlay Calibration
adjustable overlay graphics. memory to assist in this effort. for a character generator overlay string.
- 16 alphanumeric characters available
- 22 characters maximum per line
- 16 x 32 pixels with 1-bit color depth Any update to the character generator string requires the string to be passed in its entirety with the Host Command. Character strings have their own control properties aside from the Overlay bitmap properties. Overlay Layer0 Layer1 Layer2 Layer3 BT656 BT656 Timing control User Registers Data Bus DMA/CPU Register Bus ROM
Figure 31. Internal Block Diagram Overlay
Figure 32. Example of Character Descriptor 0 Stored in ROM TABLE 26. CHARACTER GENERATOR DETAILS
an 8-bit port through which to communicate this pixel data. Figure 37. Primary Clock Relationships
- SDATA–This pin is bidirectional and should not be floated
- FRAME_SYNC
- TRST_N
- SCLK
- SADDR
- ATEST1
- ATEST2 Output Data Ordering
TABLE 29. EIA COLOR BARS (NTSC)
- PIXCLK is 54 MHz when EXTCLK is 27 MHz.
TABLE 30. EIA COLOR BARS (NTSC)
- PIXCLK is 27 MHz when EXTCLK is 27 MHz.
TABLE 31. PARALLEL DIGITAL OUTPUT I/O TIMING TABLE 32. SLEW RATE FOR POXCLK AND DOUT Figure 42. Slew Rate Timing
TABLE 37. RESET_BAR DELAY PARAMETERS (CONTINUED) Figure 50. SPI Output Timing TABLE 38. SPI DATA SETUP AND HOLD TIMING conditions for extended periods may affect reliability. TABLE 39. ABSOLUTE MAXIMUM RATINGS
TABLE 39. ABSOLUTE MAXIMUM RATINGS (CONTINUED)
- “Rating” column gives the maximum and minimum values that the device can tolerate.
TABLE 40. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
- V AA and VAA−_PIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection
in the analog supplies if all three supplies are tied together.
- The imager operates in this temperature range, but image quality may degrade if it operates beyond the functional operating temperature
- Image quality is not guaranteed at temperatures equal to or greater than this range.
TABLE 41. VIDEO DAC ELECTRICAL CHARACTERISTICS–SINGLE-ENDED MODE
- DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output
an actual receiving end. Please refer to the Developer Guide for proper resistor loadings.
TABLE 42. VIDEO DAC ELECTRICAL CHARACTERISTICS–DIFFERENTIAL MODE
- DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output
with an actual receiving end. Please refer to the Developer Guide for proper resistor loadings. TABLE 43. DIGITAL I/O PARAMETERS (TA = Ambient = 25°C; All supplies at 2.8 V)
- All inputs are protected and may be active when all supplies (2.8 V and 1.8 V) are turned off.
TABLE 44. POWER CONSUMPTION – CONDITION 1
TABLE 44. POWER CONSUMPTION – CONDITION 1 (CONTINUED) TABLE 45. POWER CONSUMPTION – CONDITION 2 Analog output is disabled; parallel output is enabled. TABLE 46. KEY VIDEO SIGNAL PARAMETER TABLE
- Black and white levels are referenced to the blanking level.
- Reference to ITU −R BT.470−6
Figure 51. Video Timing TABLE 47. VIDEO TIMING: SPECIFICATION FROM REC. ITU-R BT.470-6
Figure 52. Equalizing Pulse TABLE 48. EQUALIZING PULSE: SPECIFICATION FROM REC. ITU-R BT.470−6
TABLE 50. TWO-WIRE SERIAL BUS CHARACTERISTICS
- This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.
- Two-wire control is I 2C-compatible.
- A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
- The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
- A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This
I2C-bus specification) before the SCLK line is released.
- Cb = total capacitance of one bus line in pF.
Figure 55. Quantum Efficiency (that is, without Anti-Reflective Glass (ARC) coating).
www.onsemi.com PACKAGE DIMENSIONS CASE 503AE ISSUE O IBGA63 7.5 x 7.5
www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 ASX340AT/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative