ASX340AT

ASX340AT ONSEMI | Alldatasheet

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Technical content

Features

ASX340AT/D Rev. H, 8/15 EN 1 ©Semiconductor Components Industries, LLC 2015, 1/4-Inch Color CMOS NTSC/PAL Digital Image SOC with Overlay Processor ASX340AT Datasheet, Rev. H For the latest datasheet, please visit www.onsemi.com

• Low-power CMOS image sensor with integrated image flow processor (IFP) and video encoder  1/4-inch optical format, VGA resolution (640H x 480V)  2x upscaling zoom and pan control ±40 additional columns and ± 36 additional rows to compensate for lens alignment tolerances  Option to use single 2.8 V power supply with off-chip bypass transistor  Overlay generator for dynamic bitmap overlay  Integrated video encoder for NTSC/PAL with overlay capability and 10-bit I-DAC  Integrated microcontroller for flexibility  On-chip image flow processor performs sophisticated processing, such as color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, auto white balancing, and auto exposure  Auto black-level calibration  10-bit, on-chip analog-to-digital converter (ADC)  Internal master clock generated by on-chip phase- locked loop (PLL)  Two-wire serial programming interface  Interface to low-cost EEPROM and Flash through SPI bus  High-level host command interface  Stand-alone operation support  Comprehensive tool support for overlay generation and lens correction setup  Development system with DevWare

Applications

 Automotive rear view camera and side mirror  Blind spot and surround view Key parameters are continued on next page. See “New Features” on page 3. See “Ordering Information” on page 3 Table 1: Key Parameters Parameter Typical Value Pixel size and type 5.6 m x 5.6 m active pinned- photodiode with high-sensitivity mode for low-light conditions Sensor clear pixels 728H x 560V (includes VGA active pixels, demosaic and lens alignment pixels) NTSC output 720H x 487V PAL output 720H x 576V Optical area (clear pixels) 4.077 mm x 3.136 mm Optical format ¼-inch Frame rate 50/60 fields/sec Sensor scan mode Progressive scan Color filter array RGB standard Bayer Chief ray angle (CRA) 0° Shutter type Electronic rolling shutter (ERS) Automatic Functions Exposure, white balance, black level offset correction, flicker detection and avoidance, color saturation control, on the-fly defect correction, aperture correction Programmable Controls Exposure, white balance, horizontal and vertical blanking, color, sharpness, gamma correction, lens shading correction, horizontal and vertical image flip, zoom, windowing, sampling rates, GPIO control

ASX340AT/D Rev. H, 8/15 EN 2 ©Semiconductor Components Industries, LLC,2015. ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Table 2: Key Parameters (continued) Parameter Typical Value Overlay Support Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the following features:

• Available in Analog output and BT656 Digital output
• Overlay Size 360 x 480 pixel rendered into 720 x 480 (NTSC) or 720 x 576 (PAL)
• Up to four (4) overlays may be blended simultaneously
• Selectable readout: Rotating order user-selected
• Dynamic scenes by loading pre-rendered frames from external memory
• Palette of 32 colors out of 64,000
• 8 colors per bitmap
• Blend factor dynamically-programmable for smooth transitions
• Fast update rate of up to 30 fps
• Every bitmap object has independent x/y position
• Statistic Engine to calibrate optical alignment
• Number Generator Windowing Programmable to any size Analog gain range 0.5–16x ADC 10-bit, on-chip Output interface Analog composite video out, single-end ed or differential; 8-, 10-bit parallel digital output Output data formats

1 Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB

Parallel: 27 MHz Pixel clock NTSC: 60 fields/sec PAL: 50 fields/sec Control interface Two-wire I/F for register interface plus high-level command exchange. SPI port to interface to external memory to load overlay data, register settings, or firmware extensions. Input clock for PLL 27 MHz SPI Clock Frequencies 1.6875 – 18 MHz, programmable Supply voltage Analog: 2.8V ± 5% Core: 1.8 V ± 5% (2.8V ± 5% power supply with off-chip bypass transistor generates a 1.70 - 1.95 V core voltage supply, which is acceptable for performance.) IO: 2.8 V ± 5% Power consumption Analog output only Full resolution at 60 fps: 291 mW Digital output only Full reso lution at 60 fps: 192 mW Package 63-BGA, 7.5 mm x 7.5 mm, 0.65mm pin pitch Ambient temperature Operating: -40 °C to 105 °C Functional: -40 °C to + 85 °C Storage: -50°C to + 150°C Dark Current < 200 e/s at 60 °C with a gain of 1 Fixed pattern noise Column < 2 % Row < 2 % Responsivity 16.5 V/lux-s at 550 nm Signal to noise ratio (S/N) 46 dB Pixel dynamic range 87 dB

ASX340AT/D Rev. H, 8/15 EN 3 ©Semiconductor Components Industries, LLC,2015. ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor New Features New Features  Temperature sensor for dynami c feedback and sensor control  Automatic 50Hz/60Hz flicker detection  2x upscaling zoom and pan/tilt control  Independent control of colorburst parameters in the NTSC/PAL encoder  Horizontal field of view adjustment betwee n 700 and 720 pixels on the analog output  Option to use single 2.8V power supp ly with off-chip bypass transistor  SPI EEPROM support for lower cost system design.

Ordering Information

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documenta- tion, including information on evaluation kits, please visit our web site at www.onsemi.com. Table 3: Available Part Numbers Part Number Product Description Orderable Product Attribute Description ASX340AT2C00XPED0-DPBR Rev2, Color, 0deg CRA, iBGA Pa ckage Drypack, Protective Film, Anti-Reflective Glass ASX340AT2C00XPED0-DRBR Rev2, Color, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass ASX340AT2C00XPED0-TPBR Rev2, Color, 0deg CRA, iBGA Pack age Tape & Reel, Protective Film, Anti-Reflective Glass ASX340AT2C00XPED0-TRBR Rev2, Color, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass ASX340AT2C00XPEDD3-GEVK Rev2, Color, Demo Kit ASX340AT2C00XPEDH3-GEVB Rev2, Color, Head Board ASX340AT3C00XPED0-DPBR Rev3, Color, 0deg CRA, iBGA Pa ckage Drypack, Protective Film, Anti-Reflective Glass ASX340AT3C00XPED0-DRBR Rev3, Color, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass ASX340AT3C00XPED0-TPBR Rev3, Color, 0deg CRA, iBGA Pack age Tape & Reel, Protective Film, Anti-Reflective Glass ASX340AT3C00XPED0-TRBR Rev3, Color, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass

ASX340AT/D Rev. H, 8/15 EN 4 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Table of Contents Table of Contents

ASX340AT/D Rev. H, 8/15 EN 6 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor List of Tables List of Tables

ASX340AT/D Rev. H, 8/15 EN 7 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor General Description General Description The ON Semiconductor ASX340AT is a VGA-format, single-chip CMOS active-pixel digital image sensor for automotive applications. It captures high-quality color images at VGA resolution and outputs NTSC or PAL interlaced composite video. The VGA CMOS image sensor features ON Semiconductor’ s breakthrough low-noise imaging technology that achieves superior image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and inte- gration advantages of ON Semiconductor's advanced active pixel CMOS process tech- nology. The ASX340AT is a complete camera-on-a-chip. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface or by an attached SPI EEPROM or Flash memory that contains setup information that may be loaded automatically at startup. The ASX340AT performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, 50Hz/60Hz flicker detection and avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect identification and correc- tion. The ASX340AT outputs interlaced-scan images at 60 or 50 fields per second, supporting both NTSC and PAL video formats. The image data can be output on one or two output ports:  Composite analog video (single-end ed and differential output support)  Parallel 8-, 10-bit digital Architecture Internal Block Diagram Figure 1: Internal Block Diagram Image Flow Processor Color & Gamma Correction Color Space Conversion Ed g e En h a n ce me n t Camera Control AWB AE ¼” VGA ROI @ 60 frames per sec. 640 x 480 Active Array SPI & 2W I/ F Interface SPI 4 2 2. 8V 1.8VTwo-Wire I/F Overlay Graphics Generation VideoEncoder DAC NTSC / PAL BT -656

ASX340AT/D Rev. H, 8/15 EN 8 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Architecture System Block Diagram The system block diagram will depend on the application. The system block diagram in Figure 2 shows all components; optional peripheral components are highlighted. Control information will be received by a microcontroller through the automotive bus to communicate with the ASX340AT through its two-wire serial bus. Optional components will vary by application. Figure 2: System Block Diagram SPI Serial Data EEPROM/Flash 1KB - 16MB LP Filter DAC _POS μC 2WIRE I/F Composite Video PAL / NTSC EXTCLK System Bus 2.35kΩ DAC_REF DAC _NEG Optional XTAL 37.5Ω RESET_BAR FRAME _SYNC PIXCLK FRAME_VALID LINE_VALID CCIR 656/ GPODOUT_LSB0, 1 DOUT[7:0] VDD (1 .8 V) VAA (2.8V) VAA _PIX (2.8V) 2.8V VDD_IO (2.8V). VDD_PLL (2.8V). VDD_DAC (2.8V) VREG_BASE 18pF -NPO

27.000 MHz

ASX340AT/D Rev. H, 8/15 EN 9 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Architecture Crystal Usage As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be connected between EXTCLK and XTAL. Two small loading capacitors of 10–22 pF of NPO dielectric should be added as shown in Figure 3. ON Semiconductor does not recommend using the crystal option for applications above °C. A crystal oscillator with temperature compensation is recommended. Figure 3: Using a Crystal Instead of an External Oscillator Note: Value of load capacitor is crystal dependent. Crystal with small load capacitor is recommended. EXTCLK XTAL 18pF -NPO

ASX340AT/D Rev. H, 8/15 EN 10 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Pin Descriptions and Assignments Table 4: Pin Descriptions Pin Number Pin Name Type Description Clock and Reset A2 EXTCLK Input Master input clock (27MHz): This ca n either be a square-wave generated from an oscillator (in which case the XTAL input must be left unconnected) or connected directly to a crystal. B1 XTAL Output If EXTCLK is connected to one pin of a crystal, this signal is connected to the other pin; otherwise this signal must be left unconnected. D2 RESET_BAR Input Asynchronous active-low reset: When asserted, the device will return all interfaces to their reset state. When released, the device will initiate the boot sequence. This signal has an internal pull-up resistor. E1 FRAME_SYNC Input This input can be used to set the ou tput timing of the ASX340AT to a fixed point in the frame. The input buffer associated with this input is permanently enabled. This signal must be connected to GND if not used. Register Interface F1 SCLK Input These two signals implement the serial communications protocol for access to the internal registers and variables.F2 S DATA Input/Output E2 S ADDR Input This signal controls the device ID that will respond to serial communication commands. Two-wire serial interface device ID selection: 0: 0x90 1: 0xBA SPI Interface D4 SPI_SCLK Output Clock ou tput for interfacing to an external SPI memory such as Flash/EEPROM. Tri-state when RESET_BAR is asserted. E4 SPI_SDI Input Data in from SPI device. This signal has an internal pull-up resistor. H3 SPI_SDO Output Data out to SPI device. Tri-state when RESET_BAR is asserted. H2 SPI_CS_N Output Chip selects to SPI device . Tri-state when RESET_BAR is asserted. (Parallel) Pixel Data Output F7 FRAME_VALID Input/Output Pixel data from the ASX340AT can be routed out on this interface and processed externally. To save power, these signals are driven to a constant logic level unless the parallel pixel data output or alternate (GPIO) function is enabled for these pins. This interface is disabled by default. The slew rate of these outputs is programmable. These signals can also be used as general purpose input/outputs. G7 LINE_VALID Input/Output E6 PIXCLK Output F8, D6, D7, C6, C7, B6, B7, A6 D OUT[7:0] Output B3 D OUT_LSB1 Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of output data per pixel. These two pins make the two LSB of pixel data available externally. Leave DOUT_LSB1and DOUT_LSB0 unconnected if not used. To save power, these signals are driven to a constant logic level unless the sensor core is running in bypass mode or the alternate function is enabled for these pins. The slew rate of these outputs is programmable. C2 D OUT_LSB0 Input/Output

ASX340AT/D Rev. H, 8/15 EN 11 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Composite Video Output F5 DAC_POS Output Positive video DAC output in differential mode. Video DAC output in single-ended mode. This interface is enabled by default using NTSC/PAL signaling. For applications where composite video output is not required, the video DAC can be placed in a power-down state under software control. G5 DAC_NEG Output Negative video DAC output in differential mode. A4 DAC_REF Output External reference resistor for the video DAC. Manufacturing Test Interface D3 TDI Input JTAG Test pin (Reserved for Test Mode) G2 TDO Output JTAG Test pin (Reserved for Test Mode) F3 TMS Input JTAG Test pin (Reserved for Test Mode) C3 TCK Input JTAG Test pin (Reserved for Test Mode) C4 TRST_N Input Connect to GND. G6 ATEST1 Input Analog test input. Connect to GND in normal operation. F6 ATEST2 Input Analog test input. Connect to GND in normal operation. GPIO C1 GPIO12 Input/Output Dedicated general-purpose input/output pin. A3 GPIO13 Input/Output Dedicated general-purpose input/output pin. Power G4 VREG_BASE Supply Voltage regulator control. Leave floating if not used. A5, A7, D8, E7, G1, G3 V DD Supply Supply for V DD core: 1.8V nominal. Can be connected to the output of the transistor of the off-chip bypass transistor or an external 1.8V power supply. B2, B8, C8, E3, E8, G8, VDD_IO Supply Supply for digital IOs: 2.8V nominal. H5 V DD_DAC Supply Supply for video DAC: 2.8V nominal. A8 V DD_PLL Supply Supply for PLL: 2.8V nominal. B4, H6 V AA Supply Analog power: 2.8V nominal. H7 V AA_PIX Supply Analog pixel array power: 2.8V nomina l. Must be at same voltage potential as VAA. H4 Reserved Leave floating for normal operation. B5, C5, D1, D5, H1 DGND Supply Digital ground. E5, F4 A GND Supply Analog ground. Table 4: Pin Descriptions (continued) Pin Number Pin Name Type Description

ASX340AT/D Rev. H, 8/15 EN 12 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Pin Assignments Pin 1 is not populated with a ball. That allows the device to be identified by an additional marking. Table 5: Pin Assignments 1 2 3 4 5 6 7 8 AE X T C L K GPIO13 DAC_REF V DD DOUT0V DD VDD_PLL BX T A L V DD_IO DOUT_LSB1 V AA GND D OUT2D OUT1V DD_IO CG P I O 1 2 D OUT_LSB0 TCK TRST_N GND D OUT4D OUT3V DD_IO DG N D R E S E T _ B A R TDI SPI_SCLK GND D OUT6D OUT5V DD EF R A M E _ S Y N C S ADDR VDD_IO SPI_SDI A GND PIXCLK V DD VDD_IO FS CLK SDATA TMS A GND DAC_POS ATEST2 FRAME_VALID D OUT7 GV DD TDO VDD VREG_BASE DAC_NEG ATEST1 LINE_VALID V DD_IO H GND SPI_CS_N SPI_SDO Reserved V DD_DAC V AA VAA_PIX V DD_IO Table 6: Reset/Default State of Interfaces Name Reset State Default State Notes EXTCLK Clock running or stopped Clock running Input XTAL N/A N/A Input RESET_BAR Asserted De-asserted Input SCLK N/A N/A Input. Must always be driven to high via a pull-up resistor in the range of 1.5 to 4.7 k. SDATA High impedance High impedance Input/Output. Must always be driven to high via a pull-up resistor in the range of 1.5 to 4.7 k. S ADDR N/A N/A Input. Must be permanently tied to VDD_IO or GND. SPI_SCLK High impedance. Driven, logic 0 Output. Output enable is R0x0032[13]. SPI_SDI Internal pull-up enab led. Internal pull-up enabled Input. Internal pull-up is permanently enabled. SPI_SDO High impedance Driven, logic 0 Output enable is R0x0032[13]. SPI_CS_N High impeda nce Driven, logic 1 Output enable is R0x0032[13]. FRAME_VALID High impedance High impedance Input/Output. This interface is disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating). After reset, these pins are powered up, sampled, then powered down again as part of the auto- configuration mechanism. See Note 2. LINE_VALID

ASX340AT/D Rev. H, 8/15 EN 13 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Notes: 1. The reason for defining the default state as lo gic 0 rather than high impedance is this: when wired in a system (for example, on ON Semiconductor’s demo boards), these outputs will be connected, and the inputs to which they are connected will want to see a valid logic level. No current drain should result from driving these to a valid logic level (unless there is a pull-up at the system level). 2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they can be left floating but they will not drive a valid logic level to an attached device. PIXCLK High impedance Driven, logic 0 Output. This interface disabled by default. See Note 1. DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 DOUT_LSB1 High impedance High impedance Input/Output. This interface disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating). After reset, these pins are powered-up, sampled, then powered down again as part of the auto- configuration mechanism. D OUT_LSB0 High impedance High impedance DAC_POS High impedance Driven Output. Interface disabled by hardware reset and enabled by default when the device starts streaming. DAC_NEG DAC_REF TDI Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TDO High impedance High impedance Output. Driven only during appropriate parts of the JTAG shifter sequence. TMS Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TCK Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TRST_N N/A N/A Input. Must always be driven to a valid logic level. Must be driven to GND for normal operation. FRAME_SYNC N/A N/A Input. Must always be driven to a valid logic level. Must be driven to GND if not used. GPIO12 High impedance High impedance Input/Output. This interface disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating) GPIO13 High impedance High impedance Input/Output. This interface disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating). ATEST1 N/A N/A Must be driven to GND for normal operation. ATEST2 N/A N/A Must be driven to GND for normal operation. Table 6: Reset/Default State of Interfaces (continued) Name Reset State Default State Notes

ASX340AT/D Rev. H, 8/15 EN 16 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Sensor Pixel Array The active pixel array is 640 x 480 pixels. In addition, there are 72 rows and 80 columns for lens alignment and 8 rows and 8 columns for demosaic. Figure 7: Pixel Color Pattern Detail (top right corner) Output Data Format The sensor core image data are read out in progressive scan order. Valid image data are surrounded by horizontal and vertical blanking, shown in Figure 8. For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of the image field. For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical size is 288 pixels per field. Black Pixels Column Readout Direction ... Row Readout Direction R G R G B G First Lens Alignment Pixel (64, 0) R G R G B G R G R G B G G B G G R G B G B G R G B G B G R G B G B B G B

ASX340AT/D Rev. H, 8/15 EN 17 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Figure 8: Spatial Illustration of Image Readout Valid Image Odd Field Horizontal Blanking Vertical Even Blanking Vertical/Horizontal Blanking Valid Image Even Field Horizontal Blanking Vertical Odd Blanking Vertical/Horizontal Blanking

ASX340AT/D Rev. H, 8/15 EN 18 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Image Flow Processor Image and color processing in the ASX340AT are implemented as an image flow processor (IFP) coded in hardware logic. During normal operation, the embedded microcontroller will automatically adjust the operation parameters. The IFP is broken down into different sections, as outlined in Figure 9. Figure 9: Color Pipeline Test Pattern Generator Black Level Subtraction Color Correction Aperture Correction Gamma Correction (12-to-8 Lookup) Statistics Engine Color Kill Output Formatting YUV to RGB Raw Data 10/12-Bit RGB RAW 10 8-bit RGB 8-bit YUV Parallel Output Output Interface RGB to YUV Digital Gain Control Lens Shading Correction Defect Correction, Noise Reduction, Color Interpolation MUX IFP Parallel Output Mux Pixel Array ADC Analog Output Mux NTSC/PAL Overlay Control

ASX340AT/D Rev. H, 8/15 EN 19 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Test Patterns During normal operation of the ASX340AT, a stream of raw image data from the sensor core is continuously fed into the color pipeline. For test purposes, this stream can be replaced with a fixed image generated by a special test module in the pipeline. The module provides a selection of test patterns sufficient for basic testing of the pipeline. NTSC/PAL Test Pattern Generation There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and color saturation characterization. Each pattern consists of seven color bars (white, yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are detailed in Tables 7 and 8. Figure 10: Color Bars CCIR-656 Format The color bar data is encoded in 656 data streams. The duration of the blanking and active video periods of the generated 656 data are summarized in Tables 9 and 10. Table 7: EIA Color Bars (NTSC) Nominal Range White Yellow Cyan Green Magenta Red Blue Y 16 to 235 180 162 131 112 84 65 35 Cb 16 to 240 128 44 156 72 184 100 212 Cr 16 to 240 128 142 44 58 198 212 114 Table 8: EBU Color Bars (PAL) Nominal Range White Yellow Cyan Green Magenta Red Blue Y 16 to 235 235 162 131 112 84 65 35 Cb 16 to 240 128 44 156 72 184 100 212 Cr 16 to 240 128 142 44 58 198 212 114 Table 9: NTSC Line Numbers Field Description 1-3 2 Blanking 4-19 1 Blanking

ASX340AT/D Rev. H, 8/15 EN 20 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Black Level Subtraction and Digital Gain Image stream processing starts with black level subtraction and multiplication of all pixel values by a programmable digital gain. Both operations can be independently set to separate values for each color channel (R, Gr., Gb, B). Independent color channel digital gain can be adjusted with registers. Independent color channel black level adjust- ments can also be made. If the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. Positional Gain Adjustments (PGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The ASX340AT has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr., and B color signal. The Correction Function The correction functions can then be applied to each pixel value to equalize the response across the image as follows: (EQ 1) where P is the pixel values and f is the color dependent correction functions for each color channel. 20-263 1 Active video 264-265 1 Blanking 266-282 2 Blanking 283-525 2 Active Video Table 10: PAL Line Numbers Field Description 1-22 1 Blanking 23-310 1 Active video 311-312 1 Blanking 313-335 2 Blanking 336-623 2 Active video 624-625 2 Blanking Table 9: NTSC (continued) Line Numbers Field Description Pcorrected(row,col)=P sensor(row,col)*f(row,col)

ASX340AT/D Rev. H, 8/15 EN 21 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Color Interpolation In the raw data stream fed by the sensor core to the IFP , each pixel is represented by a 10-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue, depending on the pixel's position under the color filter array. Initial data processing steps, up to and including the defect correction, preserve the one-color-per-pixel nature of the data stream, but after the defect correc- tion it must be converted to a three-colors-per-pixel stream appropriate for standard color processing. The conversion is done by an edge-sensitive color interpolation module. The module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. The algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. The edge threshold can be set through register settings. Color Correction and Aperture Correction To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. The three components of the resulting color vector are all sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12 bits per color (36 bits per pixel). The color correction matrix can be either programmed by the user or automatically selected by the auto white balance (AWB) algorithm implemented in the IFP . Color correction should ideally produce output colors that are corrected for the spectral sensitivity and color crosstalk characteristics of the image sensor. The optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. The color correction parameters can be adjusted through register settings. To increase image sharpness, a programmable 2D aperture correction (sharpening filter) is applied to color-corrected image data. The gain and threshold for 2D correction can be defined through register settings.

ASX340AT/D Rev. H, 8/15 EN 22 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Gamma Correction The ASX340AT includes a block for gamma correction that can adjust its shape based on brightness to enhance the performance under certain lighting conditions. Two custom gamma correction tables may be uploaded corresponding to a brighter lighting condi- tion and a darker lighting condition. At power-up, the IFP loads the two tables with default values. The final gamma correction table used depends on the brightness of the scene and takes the form of an interpolated version of the two tables. The gamma correction curve (as shown in Figure 11) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates are programmable through registers. Figure 11: Gamma Correction Curve RGB to YUV Conversion For further processing, the data is converted from RGB color space to YUV color space. Color Kill To remove high-or low-light color artifacts, a color kill circuit is included. It affects only pixels whose luminance exceeds a certain preprogrammed threshold. The U and V values of those pixels are attenuated proportionally to the difference between their lumi- nance and the threshold. YUV Color Filter As an optional processing step, noise suppression by one-dimensional low-pass filtering of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

ASX340AT/D Rev. H, 8/15 EN 23 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array YUV-to-RGB/YUV Conversion and Output Formatting The YUV data stream emerging from the colorpipe can either exit the color pipeline as-is or be converted before exit to an alternative YUV or RGB data format. Output Format and Timing YUV/RGB Data Ordering The ASX340AT supports swapping YCbCr mode, as illustrated in Table 11. The RGB output data ordering in default mode is shown in Table 12. The odd and even bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise swapped when chroma swap is enabled. Uncompressed 10-Bit Bypass Output Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:  Using 8 data output signals (D OUT[7:0]) and GPIO[1:0]. The GPIO signals are the least significant 2 bits of data.  Using only 8 signals (D OUT[7:0]) and a special 8 + 2 data format, shown in Table 13. Readout Formats Progressive format is used for raw Bayer output. Table 11: YCbCr Output Data Ordering Mode Data Sequence Default (no swap) Cb i Yi Cri Yi+1 Swapped CbCr Cr i Yi Cbi Yi+1 Swapped YC Y i Cbi Yi+1 Cri Swapped CbCr, YC Y i Cri Yi+1 Cbi Table 12: RGB Ordering in Default Mode Mode (Swap Disabled) Byte D7D6D5D4D3D2D1D0 565RGB Odd R 7R6R5R4R3G7G6G5 Even G 4G3G2B7B6B5B4B3 555RGB Odd 0 R 7R6R5R4R3G7G6 Even G 5G4G3B7B6B5B4B3 444xRGB Odd R 7R6R5R4G7G6G5G4 Even B 7B6B5B4 0 0 0 0 x444RGB Odd 0 0 0 0 R 7R6R5R4 Even G 7G6G5G4B7B6B5B4 Table 13: 2-Byte Bayer Format Byte Bits Used Bit Sequence Odd bytes 8 data bits D 9D8D7D6D5D4D3D2 Even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 D 1D0

ASX340AT/D Rev. H, 8/15 EN 24 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Output Formats ITU-R BT.656 and RGB Output TheASX340AT can output processed video as a standard ITU-R BT .656 (CCIR656) stream, an RGB stream, or as unprocessed Bayer data. The ITU-R BT .656 stream contains YCbCr 4:2:2 data with embedded synchronization codes. This output is typically suitable for subsequent display by standard video equipment or JPEG/MPEG compression. Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a variety of RGB formats in 640 by 480 progressive format in conjunction with LINE_VALID and FRAME_VALID. The ASX340AT can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB), and two types of 12-bit RGB (444RGB). Refer to Table 24 and Table 25 on page 50 for details. Bayer Output Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID, and PIXCLK to time the data. This mode is called sensor bypass mode. Output Ports Composite Video Output The composite video output DAC is external-resistor-programmable and supports both single-ended and differential output. The DAC is driven by the on-chip video encoder output. Parallel Output Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R BT .656 and RGB output. Ten-bit output is used for raw Bayer output. Zoom Support The ASX340AT supports zoom x1 and x2 modes, in interlaced and progressive scan modes. The progressive support is limited to the VGA at either 60 fps or 50 fps. In the zoom x2 modes, the sensor is configured for QVGA (320 x 240), and the zoom x2 window can be configured to pan around the VGA window. FOV Stretch Support The ASX340AT supports the ability to control the active 'width' of the TV output line, between 692 and 720 pixels. The hardware supports two margins, each a maximum of 14 pixels width, and has to be an even number of pixels.

ASX340AT/D Rev. H, 8/15 EN 25 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor System Configuration and Usage Modes System Configuration and Usage Modes How a camera based on the ASX340AT will be configured depends on what features are used. There are essentially three configuration modes for ASX340AT: Auto-Config Mode, Flash-Config Mode, and Host-Config Mode. Refer to System Configuration and Usage Modes in the Developer Guide document for details.

ASX340AT/D Rev. H, 8/15 EN 26 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Multicamera Support Multicamera Support Two or more ASX340AT sensors may be synchronized to a frame by asserting the FRAME_SYNC signal. At that point, the sensor and video encoder will reset without affecting any register settings. The ASX340AT may be triggered to be synchronized with another ASX340AT or an external event. Figure 12: Multicamera System Block Diagram Decoder/DSP Camera 1 Camera 2 CVBS CVBS System Bus μC ASX340 ASX340 F_SYNC OSC Dual Camera F_SYNC

ASX340AT/D Rev. H, 8/15 EN 27 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing External Signal Processing An external signal processor can take data from ITU656 or raw Bayer output format and post-process or compress the data in various formats. Figure 13: External Signal Processing Block Diagram SPI Serial EEPROM/Flash 1KB to 16MB

27 MHz

VIDEO_P CVBS PAL/NTSC EXTCLK VIDEO_N DOUT [7:0] PIXCLK Signal processor

ASX340AT/D Rev. H, 8/15 EN 28 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Device Configuration After power is applied and the device is out of reset by de-asserting the RESET_BAR pin, it will enter a boot sequence to configure its operating mode. There are essentially three three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. Figure 14: “Power-Up Sequence – Configuration Options Flow Chart,” on page 29 contains more details on the configuration options. The SOC firmware supports a System Configuration phase at start-up. This consists of five modes of execution: 1. Flash Detection 2. Flash-Config 3. Auto-Config 4. Host-Config 5. Change-Config (commences streaming - co mpletes the System Configuration mode). The System Configuration phase is entered immediately after the firmware initializes following SOC power-up or reset. By default, the firmware first enters the Flash Detec- tion mode. The Flash Detection mode attempts to detect the presence of an SPI Flash or EEPROM device:  If no device is detected, the firmware then samples the SPI_SDI pin state to determine the next mode: – If SPI_SDI == 0 then it enters the Host-Config mode. – If SPI_SDI == 1 then it enters the Auto-Config mode.  If a device is detected, the firmware switches to the Flash-Config mode. In the Flash-Config phase, the firmware interrogates the device to determine if it contains valid configuration records:  If no records are detected, then the firmware enters the Auto-Config mode.  If records are detected, the firmware processes them. By default, when all Flash records are processed the firmware switches to the Host-Config mode. However, the records encoded into the Flash can optionally be used to instruct the firmware to proceed to one of the other mode (auto-config/change-config). The Auto-Config mode uses the FRAME_VALID, LINE_VALID, D OUT_LSB0 and DOUT_LSB1 pins to configure the operation of the device, such as video format and pedestal (refer to the Developer Guide for more details). After Auto-Config completes the firmware switches to the Change-Config mode. In the Host-Config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. The System Configuration phase is effectively complete and the SOC will take no actions until the host issues commands. In the Change-Config mode, the firmware performs a 'Change-Config' operation. This applies the current configuration settings to the SOC, and commences streaming. This completes the System Configuration phase.

ASX340AT/D Rev. H, 8/15 EN 29 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Power Sequence In power-up, refer to the power-up sequence in Figure 39: “Power Up Sequence,” on page 59. In power down, refer to Figure 40: “Power Down Sequence,” on page 60 for details. Figure 14: Power-Up Sequence – Configuration Options Flow Chart DOUT _LSB 0 Power Up/ RESET Auto Configuration: FRAME _VALID LINE_VALID SPI _SDI = 0? Wait for Host Command Wait for Host Command Parse EEPROM/Flash Content Wait for Host Command yes noDisable Auto -Config Host Config DOUT _LSB 1 EEPROM/Flash contents valid? EEPROM/Flash device present? no Change Config (default) :(optional) Auto-Config Change-Config Auto-Config Change-Config no yes

ASX340AT/D Rev. H, 8/15 EN 30 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Supported NVM Devices The ASX340AT supports a variety of SPI non-volatile memory (NVM) devices. Refer to Flash/EEPROM Programming section in Developer Guide document for details.

ASX340AT/D Rev. H, 8/15 EN 31 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Host Command Interface ON Semiconductor sensors and SOCs contain numerous registers that are accessed through a two-wire interface with speeds up to 400 kHz. The ASX340AT in addition to writing or reading straight to/from registers or firmware variables, has a mechanism to write higher level commands, the Host Command Inter- face (HCI). Once a command has been written through the HCI, it will be executed by on-chip firmware and the results are reported back. In general, registers should not be accessed with the exception of registers that are marked for “User Access.” EEPROM or Flash memory is also available to store commands for later execution. Under DMA control, a command is written into the SOC and executed. For a complete description of host commands, refer to the ASX340AT Host Command Interface Specification. Figure 15: Interface Structure Host Command to FW Response from FW 15 0bit 0 command registerAddr 0x40 Addr 0xFC00 Addr 0xFC0E Addr 0xFC02 Addr 0xFC04 Addr 0xFC06 Addr 0xFC08 Addr 0xFC0A Addr 0xFC0C door bell 15 0bit Parameter 0 Parameter 7 cmd_handler_params_pool_0 cmd_handler_params_pool_1 cmd_handler_params_pool_2 cmd_handler_params_pool_3 cmd_handler_params_pool_4 cmd_handler_params_pool_5 cmd_handler_params_pool_6 cmd_handler_params_pool_7

ASX340AT/D Rev. H, 8/15 EN 32 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Host Command Process Flow Figure 16: Host Command Process Flow Read Com m and re g ister Door bel l bi t c l ear ? No Com m and has par am eter s? Ye s Wr i te par am eter s to Pa ra me te r Po o l Ye s Wr i te c om m and to Com m and r egi s ter No Issu e Com m and H o st co u ld in se rt a n opti onal del ay here Hos t c oul d i ns er t an opti onal del ay h e r e Wai t for a r es pons e ? R e a d C o mma n d re g iste r Door bel l bi t cle a r? Ye s No Com m and h a s response parameters ? Ye s Read r es pons e par am eter s fr om Pa ra me te r Po o l Ye s At thi s poi nt Com m and Regi s ter c ontai ns r es pons e c ode Done No No

ASX340AT/D Rev. H, 8/15 EN 33 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Command Flow The host issues a command by writing (through a two-wire interface bus) to the command register. All commands are encoded with bit 15 set, which automatically generates the host command (doorbell) interrupt to the microprocessor. Assuming initial conditions, the host first writes the command parameters (if any) to the parameters pool (in the command handler's logical page), then writes the command to command register. The firmware interrupt handler then signals the Command Handler task to process the command. If the host wishes to determine the outcome of the command, it must poll the command register waiting for the doorbell bit to be cleared. This indicates that the firmware completed processing the command. When the doorbell bit is cleared, the contents of the command register indicate the command's result status. If the command generated response parameters, the host can now retrieve these from the parameters pool. Note: The host must not write to the parameters pool, nor issue another command, until the previous command completes. This is true even if the host does not care about the result of the previous command. Therefore, the host must always poll the command register to determine the state of the doorbell bit, and ensure the bit is cleared before issuing a command. For a complete command list and further information consult the Host Command Inter- face Specification. An example of how (using DevWare) a command may be initiated in the form of a “Preset” follows. Issue the SYSMGR_SET_STATE Command All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after issuing the command. Therefore there is no need to check if the doorbell bit is clear before issuing the next command. # Set the desired next state in the parameters pool(SYS_STATE_ENTER_CON- FIG_CHANGE) REG= 0xFC00, 0x2800 // CMD_HANDLER_PARAMS_POOL_0 # Issue the HC_SYSMGR_SET_STATE command REG= 0x0040, 0x8100 // COMMAND_REGISTER # Wait for the FW to complete the command (clear the Doorbell bit) POLL_FIELD= COMMAND_REGISTER, DOORBELL,!=0, DELAY=10, TIMEOUT=100 # Check the command was successful ERROR_IF= COMMAND_REGISTER, HOST_COMMAND,!=0, "Set State command failed",

ASX340AT/D Rev. H, 8/15 EN 34 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Summary of Host Commands Table 14 on page 34 through Table 21 on page 36 show summaries of the host commands. The commands are divided into the following sections:  System Manager O v e r l a y G P I O  Flash Manager  Sequencer  Patch Loader M i s c e l l a n e o u s  Calibration Stats Following is a summary of the Host Interface commands. The description gives a quick orientation. The “Type” column shows if it is an asynchronous or synchronous command. For a complete list of all commands including parameters, consult the Host Command Interface Specification document. Table 14: System Manager Commands System Manager Host Command Value Type Description Set State 0x8100 Synchronous Reques t the system enter a new state Get State 0x8101 Synchronous Get the current state of the system Table 15: Overlay Host Commands Overlay Host Command Value Type Description Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem Get Overlay State 0x8201 Synchronous Retrieve the state of the overlay subsystem Set Calibration 0x8202 Synchronous Set the calibration offset Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap Set String Property 0x8205 Synchronous Set a property of a character string Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash) Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation Write Buffer 0x8208 Synchronous Write directly to an overlay buffer Read Buffer 0x8209 Synchronous Read directly from an overlay buffer Enable Layer 0x820A Synchronous Enable or disable an overlay layer Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer Set String 0x820C Synchronous Set the character string Get String 0x820D Synchronous Get the current character string Load String 0x820E Asynchronous Load a character string (from Flash)

ASX340AT/D Rev. H, 8/15 EN 35 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Table 16: GPIO Host Commands GPIO Host Command Value Type Description Set GPIO Property 0x8400 Synchronous Set a property of one or more GPIO pins Get GPIO Property 0x8401 Synchronous Retrieve a property of a GPIO pin Set GPO State 0x8402 Synchronous Set the state of a GPO pin or pins Get GPIO State 0x8403 Synchronous Ge t the state of a GPI pin or pins Set GPI Association 0x8404 Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash Get GPI Association 0x8405 Synchronous Retrieve an GPIO pin association Table 17: Flash Manager Host Commands Flash Manager Host Command Value Type Description Get Lock 0x8500 Asynchronous Request the Flash Manager access lock Lock Status 0x8501 Synchronous Retrieve th e status of the access lock request Release Lock 0x8502 Synchronous Release the Flash Manager access lock Config 0x8503 Synchronous Configure the Flash Manager and underlying SPI Flash subsystem Read 0x8504 Asynchronous Read data from the SPI Flash Write 0x8505 Asynchronous Write data to the SPI Flash Erase Block 0x8506 Asynchronous Erase a block of data from the SPI Flash Erase Device 0x8507 Asynchrono us Erase the SPI Flash device Query Device 0x8508 Asynchronous Query device-specific information Status 0x8509 Synchronous Obtain status of current asynchronous operation Config Device 0x850A Synchronous Confi gure the attached SPI NVM device Table 18: Sequencer Host Commands Sequencer Host Command Value Type Description Refresh 0x8606 Synchronous Refresh the automati c image processing algorithm configuration Refresh Status 0x8607 Synchronous Retrieve the status of the last Refresh operation Table 19: Patch Loader Host Commands Patch Loader Host Command Value Type Description Load Patch 0x8700 Asynchronous Load a patch from SPI Flash and automatically apply Status 0x8701 Synchronous Get stat us of an active Load Patch or Apply Patch request Apply Patch 0x8702 Asynchronous Apply a pa tch (already located in Patch RAM) Reserve RAM 0x8706 Synchronous Reserve RAM to contain a patch Table 20: Miscellaneous Host Commands Miscellaneous Host Command Value Type Description Invoke Command Seq 0x8900 Synchronous Invoke a sequence of commands stored in NVM Config Command Seq Processor 0x8901 Synchrono us Configures the Command Sequencer processor Wait For Event 0x8902 Synchronous Wait for a system event to be signalled

ASX340AT/D Rev. H, 8/15 EN 36 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Table 21: Calibration Stats Host Commands Calibration Stats Host Command Value Type Description Control 0x8B00 Asynchronous Start statistics gathering Read 0x8B01 Synchronous Read the results back

ASX340AT/D Rev. H, 8/15 EN 37 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface Slave Two-Wire Serial Interface The two-wire serial interface bus enables read/write access to control and status regis- ters within the ASX340AT . This interface is designed to be compatible with the MIPI Alli- ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical characteristics and transfer protocols of the two-wire serial interface specification. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7 k. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements, as follows:  a start or restart condition  a slave address/data direction byte  a 16-bit register address  an acknowledge or a no-acknowledge bit d a t a b y t e s  a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can gener- ate the start and stop conditions. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xBA. See Table 22. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is low and must be stable while SCLK is HIGH. Table 22: Two-Wire Interface ID Address Switching SADDR Two-Wire Interface Address ID 00 x 9 0 10 x B A

ASX340AT/D Rev. H, 8/15 EN 38 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default slave addresses used by the ASX340AT are 0x90 (write address) and 0x91 (read address). Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be selected by asserting the S ADDR input signal. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW . As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA low during the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi- nate a read sequence. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

ASX340AT/D Rev. H, 8/15 EN 41 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface Sequential WRITE, Start at Random Location This sequence (Figure 22) starts in the same way as the single WRITE to random location (Figure 21). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 22: Sequential WRITE, Start at Random Location Slave Address 0S A Reg Address[15:8] Write Da ta A Reg Addr ess[7 :0] A Write Data Previous Re g Addre ss, N Reg Address, M M+1 M+2 M+1 M+3 A AA Write Data Write Data M+L -2 M+L -1 M+L A A P Write Da ta (15:8 ) Write Da ta (7:0) Write Da ta (15:8 ) A Write Da ta (7:0)A AA A Write Da ta A Write Da ta (15:8) A Write Da ta (7:0) A Write Da taWrite Da ta (15:8) A Write Da ta (7:0)

ASX340AT/D Rev. H, 8/15 EN 44 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Adjustment Overlay Adjustment To ensure a correct position of the overlay to compensate for assembly deviation, the overlay can be adjusted with assistance from the overlay statistics engine:  The overlay statistics engine supports a windowed 8-bin luma histogram, either row- wise (vertical) or column-wise (horizontal).  The calibration statistics can be used to perform an automatic successive-approxima- tion search of a cross-hair target within the scene.  On the first frame, the firmware performs a coarse horizontal search, followed by a coarse vertical search in the second frame.  In subsequent frames, the firmware reduces th e region-of-interest of the search to the histogram bins containing the greatest accumulator values, thereby refining the search.  The resultant row and column location of the cross-hair target can be used to assign a calibration value to offset selected overlay graphic image positions within the output image.  The calibration statistics patch also suppo rts a manual mode, which allows the host to access the raw accumulator values directly.

ASX340AT/D Rev. H, 8/15 EN 45 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Character Generator Figure 25: Overlay Calibration The position of the target will be used to determine the calibration value that shifts the row and column position of adjustable overlay graphics. The overlay calibration is intended to be applied on a device by device basis “in system,” which means after the camera has been installed. ON Semiconductor provides basic programming scripts that may reside in the SPI Flash memory to assist in this effort. Overlay Character Generator In addition to the four overlay layers, a fifth layer exists for a character generator overlay string. There are a total of:  16 alphanumeric characters available  22 characters maximum per line  16 x 32 pixels with 1-bit color depth

ASX340AT/D Rev. H, 8/15 EN 46 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Character Generator Any update to the character generator string requires the string to be passed in its entirety with the Host Command. Character strings have their own control properties aside from the Overlay bitmap properties. Figure 26: Internal Block Diagram Overlay Overlay Layer0 Layer1 Layer2 Layer3 BT656 Number Generator BT656 Timing control User Registers Data Bus DMA/CPU Register Bus ROM

ASX340AT/D Rev. H, 8/15 EN 47 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Character Generator Character Generator The character generator can be seen as the fifth top layer, but instead of getting the source from RLE data in the memory buffers, it has 16 predefined characters stored in ROM. All the characters are 1-bit depth color and are sharing the same YCbCr look up table. Figure 27: Example of Character Descriptor 0 Stored in ROM It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when blended with the BT 656 data). R O M 1 51 41 31 21 11 0 9 8 7 6 5 4 3 2 1 0 0x00 0000000000000000 0x02 0000000000000000 0x04 0000001111000000 0x06 0000011111100000 0x08 0000111111110000 0x0a 0001111001111000 0x0c 0001110000111100 0x0e 0011110000011100 0x10 0011100000011100 0x12 0011100000011110 0x14 0111100000001110 0x16 0111000000001110 0x18 0111000000001110 0x1a 0111000000001110 0x1c 0111000000001110 0x1e 0111000000001110 0x20 0111000000001110 0x22 0111000000001110 0x24 0111000000001110 0x26 0111000000001110 0x28 0011100000001110 0x2a 0011100000011110 0x2c 0011100000011100 0x2e 0011110000011100 0x30 0001110000111000 0x32 0001111001111000 0x34 0000111111110000 0x36 0000011111100000 0x38 0000001111000000 0x3a 0000000000000000 0x3c 0000000000000000 0x3e 0000000000000000

ASX340AT/D Rev. H, 8/15 EN 51 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Figure 31: Typical CCIR656 Vertical Bl anking Intervals for 625/50 Video System Table 26: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System Line Number F V H (EAV) H (SAV) 1–22 0 1 1 0 23–310 0 0 1 0 311–312 0 1 1 0 313–335 1 1 1 0 336–623 1 0 1 0 624–625 1 1 1 0 Blanking Field 1 Active Vi deo Blanking Field 2 Active Vi deo Field 1 (F = 0) Odd Field 2 (F = 1) Even H = 1 EAV H = 0 SAV Blanking Line 1 (V = 1) Line 2 3 (V = 0) Line 311 (V = 1) Line 336 (V = 0) Line 625 (V = 1) Line 62 4 (V = 1)

ASX340AT/D Rev. H, 8/15 EN 52 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Reset and Clocks Reset Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW . In the reset state, all control registers are set to default values. See “Device Configura- tion” on page 28 for more details on Auto, Host, and Flash configurations. Soft reset is asserted or de-asserted by the two-wire serial interface. In soft-reset mode, the two-wire serial interface and the register bus are still running. All control registers are reset using default values. Clocks The ASX340AT has two primary clocks:  A master clock coming from the EXTCLK signal.  In default mode, a pixel clock (PIXCLK) ru nning at 2 * EXTCLK. In raw Bayer bypass mode, PIXCLK runs at the same frequency as EXTCLK. When the ASX340AT operates in raw Bayer bypass mode, the image flow pipeline clocks can be shut off to conserve power. The sensor core is a master in the system. The sensor core frame rate defines the overall image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline func- tions. The relationship of the primary clocks is depicted in Figure 32. The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr or 565RGB—but has only an 8-bit port through which to communicate this pixel data. To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock. Figure 32: Primary Clock Relationships 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (TYP) 0.5 pixel/clock Colorpipe Output Interface Sensor Pixel Clock Sensor Master Clock EXTCLK Sensor Core

ASX340AT/D Rev. H, 8/15 EN 53 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Floating Inputs The following ASX340AT pins cannot be floated: S DATA–This pin is bidirectional and should not be floated  FRAME_SYNC T R S T _ N CLK S ADDR A T E S T 1 A T E S T 2 Output Data Ordering Note: PIXCLK is 54 MHz wh en EXTCLK is 27 MHz. Note: PIXCLK is 27 MHz wh en EXTCLK is 27 MHz. Table 27: Output Data Ordering in D OUT RGB Mode Mode (Swap Disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0 565RGB F i r s t R 7R 6R 5R 4R 3G 7 G 6 G 5 Second G4 G3 G2 B7 B6 B5 B4 B3 555RGB First 0 R7 R6 R5 R4 R3 G7 G6 Second G5 G4 G3 B7 B6 B5 B4 B3 444xRGB F i r s t R 7R 6R 5R 4G 7 G 6 G 5 G 4 Second B7 B6 B5 B4 0 0 0 0 x444RGB F i r s t 0000 R 7 R 6 R 5 R 4 Second G7 G6 G5 G4 B7 B6 B5 B4 Table 28: Output Data Ordering in Sensor Stand-Alone Mode Mode D7 D6 D5 D4 D3 D2 D1 D0 DOUT_LSB1 DOUT_LSB0 10-bit Output B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ASX340AT/D Rev. H, 8/15 EN 56 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing I/O Timing Digital Output By default, the ASX340AT launches pixel data, FV , and LV synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FV , and LV using the rising edge of PIXCLK. The timing diagram is shown in Figure 36. As an option, the polarity of the PIXCLK can be inverted from the default by program- ming R0x0016[14]. Figure 36: Digital Output I/O Timing Note: PIXCLK can be inverted from the default by programming R0x0016[14]. Table 29: Parallel Digital Output I/O Timing fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate Signal Parameter Conditions Min Typ Max Unit EXTCLK fextclk 6 27 54 MHz textclk_period 18.52 37 166.67 ns Duty cycle 45 50 55 % PIXCLK1 fpixclk 6 27 54 MHz tpixclk_period 18.52 37.04 166.67 ns Duty cycle 45 50 55 % DATA[7:0] tpixclkf_dout 1.55 – 1.9 ns tdout_su 18 – 20 ns tdout_ho 18 – 20 ns FV/LV tpixclkf_fvlv 1.6 – 3.05 ns tfvlv_su 15 – 16 ns tfvlv_ho 20 – 21 ns EXT CL K PIXCLK D OUT [7 :0] FRAM E _VALID LINE_VALID tpixclkf _dout tpixclkf _fvlv Input Output Output Output tfvlv_su t fvlv_ho t dout_ho tdout_su textclk _period

ASX340AT/D Rev. H, 8/15 EN 57 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Slew Rate Figure 37: Slew Rate Timing Table 30: Slew Rate for PIXCLK and D OUT fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; V_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF PIXCLK DOUT[7:0] UnitR0x1E [10:8] Rise Time Fall Time R0x1E [2:0] Rise Time Fall Time 000 NA NA 000 15.0 13.5 ns 001 NA NA 001 9.0 8.5 ns 010 7.0 6.9 010 6.8 6.0 ns 011 5.2 5.0 011 5.2 4.8 ns 100 4.0 3.8 100 3.8 3.5 ns 101 3.0 2.8 101 3.3 3.3 ns 110 2.4 2.2 110 3.0 3.0 ns 111 1.9 1.7 111 2.8 2.8 ns 90% 10% tri se tfa ll PIXCLK D OUT tri se tfa ll 90 % 10 %

ASX340AT/D Rev. H, 8/15 EN 58 ©Semiconductor Components Industries, LLC, 2015. Table 31. These signals are sampled once by the on-chip firmware, which yields a long Note: Table data is based on EXTCLK = 27 MHz.

ASX340AT/D Rev. H, 8/15 EN 59 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Figure 39: Power Up Sequence Notes: 1. Delay between VDD and EXTCLK depends on custo mer devices, i.e. Xtal, Oscillator, and so on. There is no requirement on this from the sensor. 2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal. 3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied. Table 32: Power Up Sequence Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX t0 0 – – s VAA/VAA_PIX to VDD_IO t1 0 – – s VDD_IO to VDD t2 0 – – s Hard Reset t3 2 – – s Internal Initialization t4 14 – – ms VDD (1.8) VAA_PIX VAA (2.8) VDD_PLL VDD_DAC (2.8) EXTCLK RESET_BAR VDD_IO (2.8) t3 t4 t5 Hard Reset Internal Initialization Patch Config SPI or Host Streaming

ASX340AT/D Rev. H, 8/15 EN 62 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Electrical Specifications Figure 45: SPI Output Timing Caution Stresses greater than those listed in Table 37 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. Note: “Rating” column gives the maximum and minimum values that the device can tolerate. Table 36: SPI Data Setup and Hold Timing Parameter Description Min Typ Max Units fSPI_SCLK SPI_SCLK Frequency 1.6875 4.5 18 MHz tsu Setup time – – 110 ns tSCLK_SDO Hold time 110 ns tCS_SCLK Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK – 230 – ns Table 37: Absolute Maximum Ratings Symbol Parameter Rating UnitMin Max VDD Digital power (1.8V) -0.3 2.4 V VDD_IO I/O power (2.8v) -0.3 4 V VAA VAA analog power (2.8V) -0.3 4 V VAA_PIX Pixel array power (2.8v) -0.3 4 V VDD_PLL PLL power (2.8V) -0.3 4 V VDD_DAC DAC power (2.8V) -0.3 4 V VIN DC Input Voltage -0.3 V DD_IO+0.3 V VOUT DC Output Voltage -0.3 V DD_IO+0.3 V TSTG Storage temperature -50 150 °C t su SPI_CS_N SPI_SCLK SPI_SDI SPI_SDO tCS_SCLK tSCLK_SDO

ASX340AT/D Rev. H, 8/15 EN 63 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Notes: 1. V AA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 2. The imager operates in this temperature rang e, but image quality may degrade if it operates beyond the functional operating temperature range. 3. Image quality is not guaranteed at temperat ures equal to or greater than this range. Note: DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different from the loadings in a real single-ended or differential-ended video output system with an actual receiving end. Please refer to the Developer Guide for proper resistor loadings. Table 38: Electrical Characteristics and Operating Conditions Parameter1 Condition Min Typ Max Unit Core digital voltage (VDD) – 1.70 1.8 1.95 V IO digital voltage (VDD_IO) – 2.66 2.8 2.94 V Video DAC voltage (VDD_DAC) – 2.66 2.8 2.94 V PLL Voltage (VDD_PLL) – 2.66 2.8 2.94 V Analog voltage (VAA) – 2.66 2.8 2.94 V Pixel supply voltage (VAA_PIX) – 2.66 2.8 2.94 V Imager operating temperature2 – –40 +105 °C Functional operating temperature3 –40 +85 °C Storage temperature – –50 +150 °C Table 39: Video DAC Electrical Characteristics–Single-Ended Mode fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Condition Min Typ Max Unit Resolution – 10 - bits DNL – 0.2 0.4 bits INL – 0.7 3.5 bits Output local load Output pad (DAC_POS) – 37.5 -  Unused output (DAC_NEG) – 37.5 -  Output voltage Single-ended mode, code 000h – .021 - V Single-ended mode, code 3FFh – 1.392 - V Output current Single-ended mode, code 000h – 0.560 - mA Single-ended mode, code 3FFh – 37.120 - mA Supply current Estimate – - 25.0 mA DAC_REF DAC Reference – 1.200 - V R DAC_REF DAC Reference – 2.4 - K 

ASX340AT/D Rev. H, 8/15 EN 64 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Note: DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different from the loadings in a real single-ended or differential-ended video output system with an actual receiving end. Please refer to the Developer Guide for proper resistor loadings. Notes: 1. All inputs are protected and may be active when all supplies (2.8V and 1.8V) are turned off. Table 40: Video DAC Electrical Characteristics–Differential Mode fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Condition Min Typ Max Unit DNL – 0.2 0.4 Bits INL – 0.7 3.5 Bits Output local load Differential mode per pad (DAC_POS and DAC_NEG) – 37.5 –  Output voltage Differential mode, code 000h, pad dacp – .022 – V Differential mode, code 000h, pad dacn – 1.421 – V Differential mode, code 3FFh, pad dacp – 1.421 – V Differential mode, code 3FFH, pad dacn – .022 – V Output current Differential mode, code 000h, pad dacp – .587 – mA Differential mode, code 000h, pad dacn – 37.893 – mA Differential mode, code 3FFh, pad dacp – 37.893 – mA Differential mode, code 3FFH, pad dacn – .587 – mA Supply current Estimate – – 50 mA DAC_REF DAC Reference – 1.2 V R DAC_REF DAC Reference 2.4 K  Table 41: Digital I/O Parameters TA = Ambient = 25°C; All supplies at 2.8V Signal Parameter Definitions Condition Min Typ Max Unit All Outputs Load capacitance 5 – 30 pF VOH Output high voltage 0.7 * V DD_IO – V VOL Output low voltage – – 0.3* V DD_IO V IOH Output high current V OH = VDD_IO - 0.4V 20 – 35 mA IOL Output low current V OL = 0.4V 29 – 53 mA All Inputs VIH Input high voltage 0.7 * V DD_IO – V DD_IO + 0.5 V VIL Input low voltage –0.3 – 0.3 * V DD_IO V IIH Input high leakage current 0.02 – 0.26 A IIL Input low leakage current 0.01 – 0.05 A Signal CAP Input signal capacitance –6 . 5 – p F

ASX340AT/D Rev. H, 8/15 EN 65 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Power Consumption, Operating Mode Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = 37.5, DAC_Ref = 2.4k, parallel output is disabled. Analog output is disabled; parallel output is enabled. Table 42: Power Consumption – Condition 1 fEXTCLK = 27 MHz; T = 25ºC, dark condition (lens with cover) Power Plane Supply Condition 1 Typ Power Max Power Unit VDD 1.8 48.2 72 mW VDD_IO 2.8 Parallel off 2.2 10 mW VAA 2.8 96 140 mW VAA_PIX 2.8 2.2 5 mW VDD_DAC 2.8 Single 75  122.9 146 mW VDD_PLL 2.8 18.8 25 mW Total 290.3 398 mW Table 43: Power Consumption – Condition 2 fEXTCLK = 27 MHz; T = 25ºC, dark condition (lens with cover), CLOAD = 40pF Power Plane Supply Condition 2 Typ Power Max Power Unit VDD 1.8 47.5 72 mW VDD_IO 2.8 Parallel on 26.6 50 mW VAA 2.8 95.5 140 mW VAA_PIX 2.8 2.2 5 mW VDD_DAC 2.8 VDAC off 1.1 5 mW VDD_PLL 2.8 18.8 25 mW Total 191.7 297 mW

ASX340AT/D Rev. H, 8/15 EN 66 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications NTSC Signal Parameters Notes: 1. Black and white levels are referenced to the blanking level. 2. NTSC convention standardized by the IRE (1 IRE = 7.14mV). 3. Encoder contrast setting R0x3C0A[5:4] = 0. 4 . D A C r e f=2 . 8 k, load = 37.5 Table 44: NTSC Signal Parameters fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Conditions Min Typ Max Units Notes Line Frequency 15734.25 15734.27 15734.28 Hz Field Frequency 59.94 59.94 59.94 Hz Sync Rise Time 111 148 222 ns Sync Fall Time 111 148 222 ns Sync Width 4.6 4.74 4.8 s Sync Level 39 40 41 IRE 2, 4 Burst Level 36 40 44 IRE 2, 4 Sync to Setup (with pedestal off) 9.2 9.5 10.3 s Sync to Burst Start 4.71 5.3 5.71 s Front Porch 1.27 1.7 2.22 s Black Level 5 7.5 10 IRE 1, 2, 4 White Level 90 100 110 IRE 1, 2, 3, 4

ASX340AT/D Rev. H, 8/15 EN 67 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 46: Video Timing Table 45: Video Timing: Specification from Rec. ITU-R BT.470 Signal NTSC

27 MHz Units

A H Period 63.556 64.00 s B Hsync to burst 4.71 to 5.71 5.60 ± 0.10 s C burst 2.23 to 3.11 2.25 ± 0.23 s D Hsync to Signal 9.20 to 10.30 10.20 ± 0.30 s E Video Signal 52.655 ±0.20 52 +0, -0.3 s GH s y n c P e r i o d 4 . 7 0 ± 0.10 4.70 ± 0.20 s H Sync rising/falling edge  0.25 0.20 ±0.10 s H F A H DE B C G

ASX340AT/D Rev. H, 8/15 EN 68 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 47: Equalizing Pulse Table 46: Equalizing Pulse: Specification from Rec. ITU-R BT.470 Signal NTSC I H/2 Period 31.778 32.00 s J Pulse width 2.30 ± 0.10 2.35 ± 0.10 s K Pulse rising/falling edge 0.25 0.25 ± 0.05 s L Signal to pulse 1.50 ± -0.10 3.0 ± 2.0 s L J I K K

ASX340AT/D Rev. H, 8/15 EN 69 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 48: V Pulse Table 47: V Pulse: Specification from Rec. ITU-R BT.470 Signal NTSC M H/2 Period 31.778 32.00 s N Pulse width 27.10 (nominal) 27.30 ± 0.10 s O V pulse interval 4.70 ± 0.10 4.70 ± 0.10 s P Pulse rising/falling edge 0.25 0.25 ± 0.05 s N M O P P

ASX340AT/D Rev. H, 8/15 EN 71 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF.

ASX340AT/D Rev. H, 8/15 EN 72 ©Semiconductor Components Industries, LLC, 2015 ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 50: Quantum Efficiency Note: The measurements were done on packaged parts with regula r glass coating (that is, without Anti-Reflective Glass (ARC) coating). 350 450 550 650 750 850 950 1050 1150 Quantum Efficiency (%) Wavelength (nm) Red GreenR GreenB Blue

ASX340AT/D Rev. H, 8/15 EN 73 ©Semiconductor Components Industries, LLC, 2015 ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Spectral Characteristics Package and Die Dimensions Figure 51: 63-Ball iBGA Package Outline Drawing

ASX340AT/D Rev. H, 8/15 EN 74 ©Semiconductor Components Industries, LLC, 2015. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Revision History

 Updated “Ordering Information” on page 3  Updated “Ordering Information” on page 3  Updated “Ordering Information” on page 3  Removed Confidential marking  Applied ON Semiconductor template  Updated Table 2, “Key Parameters (continued),” on page 2  Updated Figure 2: “System Block Diagram,” on page 8  Updated note to Figure 3: “Using a Crysta l Instead of an External Oscillator,” on page 9  Updated Table 4, “Pin Descriptions,” on page 10  Updated “Pixel Array Structure” on page 15  Updated Figure 5: “Pixel Array Description,” on page 14  Updated “Power Sequence” on page 29  Updated “Host Command Interface” on page 31  Updated “Slave Two-Wire Serial Interface” on page 37  Updated “Overlay Capability” on page 42  Changed heading “Serial Memory Partition” to “NVM Partition” on page 43  Updated “External Memory Speed Requirement” on page 43  Updated “Overlay Adjustment” on page 44  Updated Figure 34: “NTSC Block,” on page 55  Updated Table 29, “Parallel Digital Output I/O Timing,” on page 56  Updated “Reset” on page 52  Updated “Clocks” on page 52  Updated Table 31, “Configuration Timing,” on page 58  Updated Table 32, “Power Up Sequence,” on page 59  Updated Figure 39: “Power Up Sequence,” on page 59  Updated Table 34, “FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters,” on page 60  Updated Table 35, “R ESET_BAR Delay Parameters,” on page 61  Updated Table 37, “ Absolute Maximum Ratings,” on page 62  Updated Table 39, “Video DAC Electrical Characteristics–Single-Ended Mode,” on page 63  Updated Table 40, “Video DAC Electrical Characteristics–Differential Mode,” on page 64  Updated Table 41, “Digital I/O Parameters,” on page 64  Updated Table 42, “Power Consumption – Condition 1,” on page 65  Updated Table 43, “Power Consumption – Condition 2,” on page 65  Updated Table 44, “NTSC Signal Parameters,” on page 66  Updated Figure 46: “Video Timing,” on page 67  Updated Figure 50: “Quantum Efficiency,” on page 72

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SC ILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the SCILLC prod uct could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such uninte nded or unauthorized application, Buyer shall indemnify and hol d SCILLC and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor ASX340AT/D Rev. H, 8/15 EN 75 ©Semiconductor Components Industries, LLC, 2015 .  Updated Figure 51: “63-Ball iBGA Package Outline Drawing,” on page 73  Updated Table 38, “Electrical Characteristics and Operating Conditions,” on page 63  Updated Table 39, “Video DAC Electrical Characteristics–Single-Ended Mode,” on page 63  Updated “Power Consumption, Operating Mode” on page 65  Updated Table 44, “NTSC Signal Parameters,” on page 66  Updated Table 45, “Video Timing: Specific ation from Rec. ITU-R BT .470,” on page 67  Updated Table 46, “Equalizing Pulse: Sp ecification from Rec. ITU-R BT.470,” on page 68  Updated Table 47, “V Pulse: Specification from Rec. ITU-R BT .470,” on page 69  Updated note for Figure 50: “Quantum Efficiency,” on page 72  Updated Figure 49: “Two-Wire Serial Bus Timing Parameters,” on page 70  Updated Table 41, “Digital I/O Parameters,” on page 64  Updated Table 48, “Two-Wire Serial Bus Characteristics,” on page 70  Updated to Production  Updated Table 1: “Key Parameters,” on page 1  Updated Table 6, “Reset/Default State of Interfaces,” on page 12  Updated “Pixel Array Structure” on page 15  Updated “FOV Stretch Support” on page 25  Updated Table 29, “Parallel Digital Output I/O Timing,” on page 56  Updated Table 30, “Slew Rate for PIXCLK and D OUT,” on page 57  Updated Table 32, “Power Up Sequence,” on page 59  Updated Table 33, “Power Down Sequence,” on page 60  Updated Table 34, “FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters,” on page 60  Updated Table 38, “Electrical Characteristics and Operating Conditions,” on page 63  Updated Figure 51: “63-Ball iBGA Package Outline Drawing,” on page 73 I n i t i a l r e l e a s e