ASP2100

ASP2100 ONSEMI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 40

Technical content

Features

• Vin Range 4.5 V to 21 V
• Startup into Pre−Charged Loads While Avoiding False OVP
• Digital Soft Start Ramp
• Adjustable VBOOT
• High Impedance Differential Amplifier for Accurate Output V oltage Sensing
• Dual VID Table Support to be Compatible with IMVP9.1
• Support for High Current Extensions
• Auto Phase Shedding
• Dynamic Reference Injection
• Programmable Output V oltage Slew Rates
• Dynamic VID Feed−Forward
• Differential Current Sense Amplifiers for Each Phase
• Programmable Adaptive V oltage Positioning (A VP)
• Current Mode Dual Edge Modulation for Fastest Initial Response to Transient Loading
• High Performance Operational Error Amplifier
• Accurate Total Summing Current Amplifier
• Thermal Monitor
• Adjustable Switching Frequency Range
• Digitally Stabilized Switching Frequency
• Ultrasonic Operation
• Support Acoustic Noise Mitigation Function
• PSYS Input Monitor (SVID address 0x0D)
• Support for VCCIN_AUX IMON Input
• Meets Intel’s IMVP9.1 Specifications
• I2C Control Interface Typical Applications
• Desktop Computers MARKING DIAGRAMS QFN56 CASE 485BT A = Assembly Site WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free 15 6 Device Package Shipping †

ORDERING INFORMATION

(Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. ASP2100RMNTXG QFN56 (Pb−Free) 2500 / Tape & Reel

Figure 1. Internal Block Diagram

ASP2100, ASP2100R www.onsemi.com

APPLICATION INFORMATION

Figure 2. Typical Application Circuit

Figure 3. Pinout (Top View)

1 SDA I2C bus serial data interface

2 SCL I2C bus clock

4 SDIO Serial VID data interface

5 ALERT# Serial VID ALERT#

6 SCLK Serial VID clock

7 VR_RDY VR_RDY indicates both rails are ready to accept SVID commands

11 VRSHDN VRSHDN output, pulled and latched low until power off if VR temp reaches programmed level

13 AUX_IN AUX IMON Input on 0x0Dh SVID domain. A resistor to ground scales this signal.

14 IOUTA Total output current monitor

15 VSNA Differential output voltage negative sense for regulator 2

16 VSPA Differential output voltage positive sense for regulator 2

ASP2100, ASP2100R www.onsemi.com PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionPin Name

17 DIFFA Output of the regulator 2 differential remote sense amplifier

18 FBA Error amplifier voltage feedback for regulator 2

19 COMPA Output of the error amplifier and the inverting inputs of the PWM comparators for regulator 2

20 CSCOMPA Output of total−current−sense amplifier for regulator 2

21 ILIMA Over−current threshold setting – programmed with a resistor to CSCOMPA for regulator 2

22 CSSUMA Inverting input of total−current−sense amplifier for regulator 2

23 CSREFA Total−current−sense amplifier reference voltage input for regulator 2

24 CSP1A Non−inverting input to current−balance amplifier for Phase 1 of regulator 2

25 CSP2A Non−inverting input to current−balance amplifier for Phase 2 of regulator 2

26 TSENSEA Temperature sense input for regulator 2

27 PWM1A/ICCMAXA PWM1 output for regulator 2. Pulldown on this pin programs ICCMAX for regulator 2 during startup

28 PWM2A/

I2C_ADDRESS PWM2 output for regulator 2. Pulldown on this pin programs I2C address during startup

29 DRON External FET driver enable for discrete driver or ONSemi DrMOS

30 PWM8 PWM8 output for regulator 1.

31 PWM7/

ICC*2_MAIN_RAIL PWM7 output for regulator 1/Pulldown resistor on this pin can be used to enable ICC*2_MAIN_RAIL function.

32 PWM6/

ICCMAX_AUXIN PWM6 output for regulator 1/Pulldown resistor on this pin programs ICCMAX for the AUX_IN monitoring rail

33 PWM5/ROSCA PWM5 output for regulator 1/Pulldown on this pin programs RoscA value for regulator 2

34 PWM4/ROSC PWM4 output for regulator 1/Pulldown on this pin programs Rosc value for regulator 1

35 PWM3/ICCMAX PWM3 output for regulator 1/Pulldown on this pin programs ICCMAX for regulator 1

36 PWM2/VBOOT PWM2 output for regulator 1/Pin−program for regulator 1 and regulator 2 Vboot

37 PWM1/

SV_ADDR_SR ASP2100: PWM1 output for regulator 1/Pulldown on this pin configures SVID address and slew rate. ASP2100R: PWM1 output for regulator 1 / Pulldown on this pin configures SVID address, slew rate and VR_Hot control for Fast V−Mode.

38 TSENSE Temperature sense input for regulator 1

39 CSP1 Differential current sense positive for Phase 1 of regulator 1

40 CSP2 Differential current sense positive for Phase 2 of regulator 1

41 CSP3 Differential current sense positive for Phase 3 of regulator 1

42 CSP4 Differential current sense positive for Phase 4 of regulator 1

43 CSP5 Differential current sense positive for Phase 5 of regulator 1

44 CSP6 Differential current sense positive for Phase 6 of regulator 1

45 CSP7 Differential current sense positive for Phase 7 of regulator 1

46 CSP8 Differential current sense positive for Phase 8 of regulator 1

47 CSREF Total−current−sense amplifier reference voltage input for regulator 1

48 CSSUM Inverting input of total−current−sense amplifier for regulator 1

49 ILIM Over−current threshold setting – programmed with a resistor to CSCOMP for regulator 1

50 CSCOMP Output of total−current−sense amplifier for regulator 1

51 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for regulator 1

52 FB Error amplifier voltage feedback for regulator 1

53 DIFF Output of the regulator 1 differential remote sense amplifier

54 VSP Differential output voltage sense positive for regulator 1

55 VSN Differential output voltage sense negative for regulator 1

56 IOUT Total output current monitor for regulator 1

1. “Regulator 1” is referred to as “Main” rail throughout the datasheet. “Main” is the primary rail with the highest phase count. 2. “Regulator 2” is referred to as “A” rail throughout the datasheet.

ASP2100, ASP2100R www.onsemi.com MAXIMUM RATINGS (Note 3) Pin Symbol VMAX VMIN ISOURCE ISINK COMP, COMPA VCC + 0.3 V −0.3 V 2 mA 2 mA CSCOMP, CSCOMPA VCC + 0.3 V −0.3 V 2 mA 2 mA PWMX VCC + 0.3 V −0.3 V − 1 mA VSN, VSNA GND + 0.3 V GND – 0.3 V 1 mA 2 mA DIFF, DIFFA VCC + 0.3 V −0.3 V 2 mA 2 mA VR_RDY VCC + 0.3 V −0.3 V 2 mA − VCC 6.0 V −0.3 V − − VRMP VCC + 0.3 V −0.3 V − − SCLK, SDIO 3.6 V −0.3 V − − All Other Pins VCC + 0.3 V −0.3 V − − Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. All signals referenced to GND unless noted otherwise ESD CAPABILITY Description Symbol Typ Unit ESD Capability, Human Body Model (Note 4) ESDHBM 2,000 V ESD Capability, Charged Device Model (Note 4) ESDCDM 750 V 4. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Charge Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) Latch−up Current Maximum Rating: ≤ 200 mA per JEDEC standard: JESD78. RECOMMENDED OPERATING CONDITIONS Description Symbol Min Max Unit VCC Voltage Range VCC 4.75 5.25 V Operating Junction Temperature Range (Note 5) TJ −10 125 °C Operating Ambient Temperature Range TA −10 100 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. JEDEC JESD 51 −7 with 0 LFM. THERMAL CHARACTERISTICS Description Symbol Value Unit Thermal Characteristic QFN Package RJA 65 °C/W Maximum Storage Temperature Range TSTG −40 to +150 °C Soldering Temperature 260 °C Junction−to−Ambient, Thermal Resistance (Note 6) /C0113JA 30 °C/W Junction−to−Case (Top), Thermal Resistance (Note 6) /C0113JC(TOP) 18 °C/W Junction−to−Board Heat Spreader, Thermal Resistance (Note 6) /C0113JB 1.0 °C/W Junction−to−Case (Top), Measurement Reference (Note 6) /C0089J−CT 1.1 °C/W Moisture Sensitivity Level QFN Package MSL 1 6. JEDEC JESD 51 −7 with 0 LFM

ASP2100, ASP2100R www.onsemi.com ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 /C0109F unless otherwise noted) Parameter Test Conditions Min Typ Max Unit BIAS SUPPLY VCC Voltage Range 4.75 − 5.25 V Quiescent Current PS0 − 31 − mA PS1 − 26 − mA PS2 − 21 − mA PS3 − 17 − mA PS4 − − 79 /C0109A Enable Low − − 64 /C0109A UVLO Threshold VCC Rising − − 4.5 V VCC Falling 4.1 − − V VCC UVLO Hysteresis − 100 − mV VRMP VIN Supply Range VRMP range prior to external voltage divider resistor network with 1/12 ratio 4.5 − 21 V UVLO Threshold VRMP Rising − − 0.355 V VRMP Falling 0.250 − − V ENABLE INPUT Upper Threshold Activation Level 0.8 − − V Lower Threshold Deactivation Level − − 0.3 V PHASE DETECTION CSP Pin Threshold Voltage VCC − 0.4 − − V Phase Detect Timer − 1.5 − ms IMVP9.1 DAC (PROTOCOL 0Eh) System Voltage Accuracy 0 V < DAC < 0.495 V (25°C only) −10 − 10 mV 0.5 V < DAC < 0.745 V (25°C only) −8 − 8 mV DAC SLEW RATE Soft Start Slew Rate − 1/4 fast − mV//C0109s Slew Rate Slow − 1/4 fast − mV//C0109s Slew Rate Fast Resistor Selectable (See Table 4) − >10 − mV//C0109s VOFS Slew Rate − 1/4 fast − mV//C0109s DRON Output High Voltage Sourcing 1 mA 3 − − V Output Low Voltage Sinking 1 mA − − 0.1 V TSENSE TSENSE Bias Current 115.5 120 124.5 /C0109A Alert# Assert Threshold − 486 − mV De−Assert Threshold − 548 − mV VR_HOT Assert Threshold − 448 − mV De−Assert Threshold − 511 − mV VRSHDN Assert Threshold − 185 − mV VR_RDY OUTPUT VR_RDY Rise Time 1 k/C0087 pull−up to 3.3 V CTOT = 45 pF − 110 150 ns VR_RDY Fall Time − 20 150 ns

ASP2100, ASP2100R www.onsemi.com ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 /C0109F unless otherwise noted) (continued) Parameter UnitMaxTypMinTest Conditions VR_RDY Output Voltage Low IVR_RDY = −4 mA − − 0.3 V SVID (SDIO and SCLK) SVID Voltage Low Level VIL (Note 7) − − 0.45 V SVID Voltage High Level VIH (Note 7) 0.65 − − V SVID Pull Down Resistance (Note 8) − 4 − /C0087 SDIO Output Low Voltage VOL − − 0.3 V SVID Clock to Data Delay TCO (Note 8) − − 12 ns SVID Setup Time (Note 8) 7 − − ns SVID Hold Time (Note 8) 14 − − ns Input Capacitance (Note 8) − 5 − pF ALERT# VOL (Output Low) − − 0.3 V OVP AND UVP Absolute Over Voltage Threshold 10 mV DAC step During Soft Start − CSREF Rising 3.3 3.44 3.6 V 5 mV DAC step During Soft Start − CSREF Rising 2.4 2.5 2.6 V Over Voltage Threshold Above DAC VSP−VSN−VID Rising 350 400 475 mV Over Voltage Delay VSP−VSN Rising to PWM Low 50 ns Under Voltage Threshold Below DAC−DROOP (VUVM) VSP−VSN−VID Falling −440 −400 −360 mV Under Voltage Delay − 5 − /C0109s PWM OUTPUT Output High Voltage Sourcing 500 /C0109A VCC − 0.2 − − V Output Mid Voltage No Load, Power State 2 1.7 1.8 1.9 V Output Low Voltage Sinking 500 /C0109A − − 0.7 V DIFFERENTIAL AMPLIFIER Input Bias Current VSP = 1.3 V 200 − 500 nA −3 dB Bandwidth CL = 20 pF, RL = 10 k/C0087 − 22.5 − MHz Closed Loop DC Gain VSP − VSN = 0.5 V to 1.3 V − 1 − V/V ERROR AMPLIFIER Input Bias Current Input = 1.3 V −400 − 400 nA DC Gain CL = 20 pF, RL = 10 k/C0087 − 80 − dB −3 dB Bandwidth CL = 20 pF, RL = 10 k/C0087 − 20 − MHz Slew Rate /C0068Vin = 100 mV, G = −10 V/V, /C0068Vout = 1.5 V to 2.5 V, CL = 20 pF, RL = 10 k/C0087 − 5 − V//C0109s OVER−CURRENT PROTECTION (ILIM) ILim Threshold Current Immediately, OCP_L/VRHOT# Asserts ICL0 − PS0 Operation 8 9 10 /C0109A ICL1 − PS1, PS2, PS3 Operation (Note 9) − 9/N − /C0109A ILim Threshold Current (Delayed OCP shutdown) ICLM0 − PS0 Operation 11 13 15 /C0109A ICLM1 − PS1, PS2, PS3 Operation (Note 9) − 13/N − /C0109A Shutdown Delay Immediate − 650 − ns Delayed − 20 − /C0109s

ASP2100, ASP2100R www.onsemi.com ELECTRICAL CHARACTERISTICS (−10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 /C0109F unless otherwise noted) (continued) Parameter UnitMaxTypMinTest Conditions IOUT OUTPUT Current Gain IOUT/ILIM (RLIM = 20 k/C0087, RIOUT = 5 k/C0087, Vout = 0.8 V, 1.25 V, 1.52 V) 9.5 10 10.5 A/A PWM GENERATOR PWM Minimum Pulse Width − 40 − ns 0% Duty Cycle Comp Voltage for PWM Held Low − 1.3 − V 100% Duty Cycle Comp Voltage for PWM Held High VIN at 4.5 V − 1.75 − V Comp Voltage for PWM Held High VIN at 21 V − 3.4 − CURRENT SUMMING AMPLIFIER (CSAMP) Offset Voltage −500 − 500 /C0109V Input Bias Current CSSUM = CSREF = 1.0 V −10 − 10 /C0109A Open Loop Gain − 80 − dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 k/C0087 to GND − 10 − MHz CURRENT BALANCE AMPLIFIER Differential Mode Input Voltage Range CSREF = 1.2 V −100 − 100 mV PSYS Full Scale Input Voltage − 2.5 − V Disable Threshold − VCC − 0.4 − V I2C (SDA AND SCL) High Input Voltage (VIH) VTT_I2C is the I2C (SDA & SCL) Termination Voltage, 1.71 V ≤ VTT_I2C ≤ 5.25 V (Note 10) 0.65 * VTT_I2C − − V Low Input Voltage (VIL) − − 0.35 * VTT_I2C V Hysteresis (Note 10) − 120 − mV Output Low Voltage IPULLUP = 3 mA − − 0.4 V Input Current −10 − − /C0109A Input Capacitance SDA and SCL − 5 − pF Clock Frequency − − 400 kHz SCL Falling Edge to SDA Valid Timing (Note 8) − − 1 /C0109s 7. Tested at 25 °C / 5 V VCC only. 8. Guaranteed by characterization, not production tested. 9. N is the phase configuration number in PS0. 10.Guaranteed by design, not production tested. Start Up Following the rise of VCC above the UVLO threshold, externally programmed configuration data is collected, and all PWM outputs are set to Mid −level to prepare the gate drivers of the power stages for activation. When the controller is enabled, DRON is asserted (high) to activate the external gate drivers. A digital counter steps the DAC up from zero to the target boot voltage based on the Soft Start Slew Rate in the spec table. As the DAC ramps, the PWM outputs of each rail will change from Mid −level to high when the first PWM pulse for that rail is produced. When the controller is disabled, the PWM signals return to Mid−level. The VR_RDY signal is asserted when the controller is ready to accept the first SVID command.

• SVID Address
• Slew Rate
• VBOOT
• Output V oltage Step SVID address and slew rate options are shown in Table 4. VBOOT and output voltage step options are shown in Table 6. ASP2100R Fast V−Mode VR_HOT assertion for Fast V−Mode on/off selection as shown in Table 5. Fast V −Mode is only supported on the ASP2100R. Switching Frequency Switching frequencies between 180 kHz and 1.17 MHz are programmed on power up with pulldown resistors on the Rosc and RoscA pins. Switching frequency options are shown in Table 9. The Main Rail follows the configuration number in PS0. The A rail follows 1 −phase switching frequency setting. ICCMAX The SVID interface provides the platform ICCMAX values for each rail, at register 21h. Resistors to ground on the PWM3/ICCMAX, PWM1A/ICCMAXA and PWM6/ICCMAX_AUXIN pins program these registers. On power up, 10 /C0109A is sourced from these pins to generate voltages on the program resistors. The values of the registers are set by the equation below. The resistor values should be no less than 10 k/C0087. ICCMAX21h /C0043 R /C003210 /C0109A /C0032255 2.5 V (eq. 1) ICCMAX Additional Capability IMVP9.1 adds an option to extend the current range of the main rail by scaling the LSB size of register ICCMAX21h by 2ICCMAX_ADD50h[1:0] amps (See Table 2). On the ASP2100 and ASP2100R, these register bits can be configured to 2 A per bit by enabling ICC*2_MAIN_RAIL mode. See Table 6 for details on how to enable this mode.

Table 2. ICCMAX CAPABILITY SCALING ICC*2_MAIN_RAIL mode is enabled or disabled.

**Table 3. RAIL SETTINGS FOR ICC*2_MAIN_RAIL MODE** frequency to stay above the audible range. (CCM) which uses the dual −edge control methodology. inductor value, and output capacitor value. loss of efficiency from negative inductor current. Table 4. ASP2100 SVID ADDRESS AND SLEW RATE

Table 5. ASP2100R SVID ADDRESS, SLEW RATE AND Table 6. VBOOT AND OUTPUT VOLTAGE STEP Table 7. POWER STATES The PSYS pin is an analog input to the VR controller. SVID interface at address 0Dh. input pin by a termination resistor, located at the controller. 2 A LSB step size. When off, the resolution is 1 A per LSB. reporting of over 255 A on the main rail only. Shedding (Enable by I2C) section and the I2C register maps.

**Table 8. PIN OF ICC*2_MAIN_RAIL CONFIGURATION**

10 OFF OFF OFF OFF

14 OFF OFF OFF ON

18.7 OFF OFF ON OFF

24.3 OFF OFF ON ON

30.9 OFF ON OFF OFF

38.3 OFF ON OFF ON

47.5 OFF ON ON OFF

59 OFF ON ON ON

71.5 ON OFF OFF OFF

86.6 ON OFF OFF ON

105 ON OFF ON OFF

127 ON OFF ON ON

154 ON ON OFF OFF

187 ON ON OFF ON

221 ON ON ON OFF

280 ON ON ON ON

Table 9. SWITCHING FREQUENCY

1 Phase~6 Phase 7 Phase 8 Phase

the desired output current limit. Table 10. OCP SETUP , CONTROL AND MONITORING generates a 2.5 V signal on IOUT.

2.5 V /C0032RLIMIT

main rail and 0x2E for the A rail.

Table 12. TSENSE & TSENSEA THRESHOLD VOLTAGES

1. Temperatures shown relate to an ideal temperature characteristic.

1.8 V/C0467/C0032140oC

trip point using Equation 16. Figure 13. TSENSE Network linear and proportional response to the step load.

over the I2C. The I2C interface consists of SDA and SCL. Table 13. I2C SLAVE ADDRESS CONFIGURATION can also be adjusted depend on output load.

Table 16. PHASE CONFIGURATION CSP8 connected to VCC through a 2 k/C0087 resistor. CSP7 connected to VCC through a 2 k/C0087 resistor. Use PWM7 for programming ICC*2_MAIN_RAIL only. CSP6 connected to VCC through a 2 k/C0087 resistor. Use PWM7 for programming ICC*2_MAIN_RAIL only. Use PWM6 for programming ICCMAX_AUXIN only. CSP5 connected to VCC through a 2 k/C0087 resistor. Float PWM8, CSP6, CSP7, and CSP8. Use PWM7 for programming ICC*2_MAIN_RAIL only. Use PWM6 for programming ICCMAX_AUXIN only. Use PWM5 for programming ROSCA only. CSP4 connected to VCC through a 2 k/C0087 resistor. Float PWM8, CSP5, CSP6, CSP7, and CSP8. Use PWM7 for programming ICC*2_MAIN_RAIL only. Use PWM6 for programming ICCMAX_AUXIN only. Use PWM5 for programming ROSCA only. Use PWM4 for programming ROSC only. CSP3 connected to VCC through a 2 k/C0087 resistor. Float PWM8, CSP4, CSP5, CSP6, CSP7, and CSP8. Use PWM7 for programming ICC*2_MAIN_RAIL only. Use PWM6 for programming ICCMAX_AUXIN only. Use PWM5 for programming ROSCA only. Use PWM4 for programming ROSC only. Use PWM3 for programming ICCMAX only. 8 + 1 CSP1 to CSP8 and CSP1A pins connected normally. CSP2A connected to VCC through a 2 k/C0087 resistor. Use PWM2A for programming I2C_ADDRESS only. 8 + 0 CSP1 to CSP8 pins connected normally. CSP1A connected to VCC through a 2 k/C0087 resistor. Use PWM2A for programming I2C_ADDRESS only. Table 17. PHASE SHEDDING CONFIGURATION

will trip – sending the VR_RDY signal low. without false triggering OVP. Figure 16. OVP Threshold Behavior

signal to the master that the Status Register should be read. Figure 19. SVID Timing Diagram Table 18. SLEW RATE

Table 19. I2C REGISTERS FOR MAIN RAIL 2 phases operate by PWM1 and PWM2. Offsets for I2C states LCS0 – LCS3 (5 mV/step). VOFS is 2’s compliment, Bit 7 is sign bit. Voltage change slew rate is SLOW. Refer to switching frequency configuration settings in Table 9. Adjustment CB_EN[7] = Enable/Disable current balance feature.

Refer to IMVP9.1 SVID table. Note: Read this register before reading VOUT_LSB (0x17). If 0x1E[6] = ”1”, VOUT = Sense Voltage, 3.9 mV/step. Note: Read VOUT_MSB (0x16) before reading this register.

gain is 6 so this corresponds to 83 mV across CSPx/CSREF. DVID slew rate. Range is from 8 mV//C0109s to 48 mV//C0109s.

this is independent of the watchdog timer). 0x20 VRSHDN_TH[7:4] Bit[7:4]: Main Rail VRSHDN Threshold Setting. Bit[5]: Total OCP threshold control when single phase operation. Temp Status bit (SVID reg 0x10 bit) is not set. ’1’ => VBOOT follows I2C setting. VDAC_STEP is the output voltage step size as shown in Table 6. 0x43 TM[7:0] I2C Thermal Monitor Value Reading. and 0.3 k/C0087 for series resistor.

Bit[5:4]: Boost cap low time. 12.Offset should only be changed or enabled/disabled when the controller is operating in PS0 mode. 13.This functionality will only be available if it is also enabled using the pin function resistor (See Table 8).

Table 20. I2C REGISTERS FOR A RAIL DVID slew rate. Range is from 8 mV//C0109s to 48 mV//C0109s. 0x21 SVRSHDN_TH[7:4] Bit[7:4]: A Rail VRSHDN Threshold Setting. Offsets for I2C states SLCS0 – SLCS1 (5 mV/step). SVOFS is 2’s compliment, Bit 7 is sign bit. Voltage change slew rate is SLOW. Note: 0x39[4] must be set to enable offset function. Refer to switching frequency configuration settings in Table 9. Adjustment SCB_EN [7] = Enable/Disable current balance feature. Refer to IMVP9.1 SVID table. Note: Read this register before reading SVOUT_LSB (0x35). Note: Read SVOUT_MSB (0x34) before reading this register.

Table 20. I2C REGISTERS FOR A RAIL (continued) Note: 0x39[3] must be set to enable Total Current OCP function. default gain is 6 so this corresponds to 83 mV across CSPxA/CSREFA.

Bit[5]: Total OCP threshold control when single phase operation. Temp Status bit (SVID reg 0x10 bit ) is not set. ’0’ => VBOOTA follows H/W resistor setting as per table 6. ’1’ => VBOOTA follows I2C setting. VDAC_STEP is the output voltage step size as shown in Table 6. 0x44 STM[7:0] I2C Thermal Monitor Value Reading.

Bit[5:4]: Boost cap low time. 14.This functionality will only be available if it is also enabled using the pin function resistor (See Table 8). 15.Offset should only be changed or enabled/disabled when the controller is operating in PS0 mode. Table 21. GENERAL REGISTERS

Table 22. SVID REGISTER MAP 00h VENDOR_ID Uniquely identifies the VR vendor. The vendor ID assigned by Intel to onsemi is 1Ah. 01h PROD_ID Uniquely identifies the VR product. The VR vendor assigns this number. The VR vendor assigns this data. Conveying the status of the VR. 11h STATUS2 Data register showing optional status_2 data. 0xFF when the output current is at Icc_Max. between VSP and VSN. LSB size is 15.625 mV. 17h VR_TEMP 8 bit binary word ADC of voltage. 18h POUT_H 8 bit binary word representative of output power. of 00h indicates this function is not supported.

Table 22. SVID REGISTER MAP (continued) point on the register is read only. supports and the level (No Suggestions) asserts. 24h SR_FAST Slew Rate for SetVID_fast commands. or 2 times slower than the SR_fast rate. move to a different voltage. output voltage beginning to ramp. supplying max current of the command PS state. controller being ready to accept SVID commands. gin, 1 = negative margin. Remaining 7 BITS are #.

to the PSYS critical comparator. the threshold level in 0x4B is changed. This register does not roll over when it reaches 0xFF. the threshold level in 0x4C is changed. This register does not roll over when it reaches 0xFF. the PSYS critical comparator.

Table 23. IVMP9.1 VID COMMAND Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries.

QFN56 7x7, 0.4P CASE 485BT ISSUE A DATE 02 DEC 2014 ÈÈÈ ÈÈÈ SCALE 2:1 NOTE 3 SEATING PLANE K 0.15 C (A3) A b 56 43 XXXXXXXXX XXXXXXXXX AWLYYWW- G GENERIC MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb −Free Package 56X L56X BOTTOM VIEW TOP VIEW SIDE VIEW 0.15 C D A B E PIN 1 LOCATION 0.08 C 0.10 C e 0.10 C 0.05 C A B C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.25 MM FROM TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. FOR DEVICE OPN CONTAINING W OPTION, DETAILS A AND B, ALTERNATE CONSTRUC- TION PERTAINING TO THE L1 DIMENSION, ARE NOT APPLICABLE. DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.15 0.25 D 7.00 BSC D2 5.60 5.80 E 7.00 BSC E2 5.60 5.80 e 0.40 BSC K L 0.30 0.50 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. 15 6 NOTE 4 DIMENSIONS: MILLIMETERS

0.40 PITCH

5.84 0.25 56X 7.30 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* DETAIL A 0.58 56X DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÇÇ ÇÇÉÉ ÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONS L1 0.05 0.15

0.25 REF

AM0.10 B C AM0.10 B C M M MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON56933EDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1QFN56 7X7, 0.40P © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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