ASP0800 ONSEMI | Alldatasheet
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Programmable Multi-Phase Synchronous Buck Converter with PMBus Preliminary Technical Data ASP0800 Rev. Pr H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ERY FEATURES Selectable 1-, 2-, 3-, 4-, 5-, 6, 7 or 8- phase operation at up to
1 MHz per phase
PMBus Interface - enables digital programmability of set points and readback of monitored values Logic-level PWM outputs for interface to external high power drivers Fast-Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable 0.375 V to 1.6 V output supports both VR11 and VR11.1 specifications Programmable Offset up to ±200mV Programmable short-circuit protection with programmable latch-off delay Supports PSI# – Power saving mode during light loads Over – Clocking Control
APPLICATIONS
CPU Power controllers for Servers, Workstations and high end Desktops. Next generation Intel® VRM modules POL Applications such as Memory FUNCTIONAL BLOCK DIAGRAM VCC PRECISION REFERENCE DELAY GND ASP0800 EN/VTT PWRGD RAMPADJ RT
28 SW3
VID2VID1 VID3 VID4 VID5 VID7VID6 COMP FBRTN VID DAC CURRENT MEASUREMENT AND LIMIT CROWBAR CURRENT LIMIT 4044454647 OD1 SW229 SW427 OSCILLATOR SW130 4143 42 11IREF VID0
10 IMON
PSI# SMBUS SCL SDA 5 4 BOOT VOLTAGE& SOFT START CONTROL ILIMITFS 20 VCC3 CONTROL – 850mV – CONTROL CSREF UVLO SHUTDOWN SHUNT REGULATOR 3.3V REGULATOR CLOCK CONTROL OC1 OC2 CONTROL
21 ODN
24 SW7
–CMP PWM633 PWM732 PWM831 –CMP –CMP –CMP –CMP –CM P –CMP –CM P PWM534 CURRENT BALANCING CIRCUIT 1- 8 PHASE DRIVER LOGIC ENSET RESET RESET RESET RESET RESET RESET RESET RESET EN FB FBRTN IMON MUX ALERT 3 COMPARATORS Figure 1. Functional Block Diagram design of High Efficiency and High Density solutions. used to set the output voltage between 0.375 V and 1.6 V . Thresholds and 4 OC Offsets value registers are supported. 1 Protected by U.S. Patent Number 6,683,441; other patents pending.
ASP0800 Preliminary Technical Data Rev. PrH | Page 2 of 38 TABLE OF CONTENTS Rev. P1 | Page 2 of 36 | www.onsemi.com
REVISION HISTORY
03/08—Rev P1: Conversion to ON Semiconductor
Preliminary Technical Data ASP0800 Rev. Pr H| Page 3 of 38 SPECIFICATIONS VCC = 5 V , FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1 Parameter Symbol Conditions Min Typ Max Unit REFERENCE CURRENT Reference Bias Voltage VIREF 1.75 1.8 1.85 V Reference Bias Current IIREF R IREF = 121 kΩ 15 uA ERROR AMPLIFIER Output Voltage Range2 V COMP 0 4.4 V Accuracy VFB Relative to nominal DAC output, referenced to FBRTN (see Figure 3) −10 +10 mV V FB(BOOT) In startup 1.09 1.1 1.11 V Load Line Positioning Accuracy −77 −80 −83 mV Load Line Range −350 0 mV Load Line Attenuation 0 100 % Differential Nonlinearity −1 +1 LSB Input Bias Current IFB I FB = IIREF 13.5 15 16.5 µA Offset Accuracy VR Offset Register = TBD, VID = 1.0V −200 mV VR Offset Register = TBD , VID = 1.0V 200 mV FBRTN Current IFBRTN 70 200 µA Output Current ICOMP FB forced to VOUT – 3% 500 µA Gain Bandwidth Product GBW(ERR) COMP = FB 20 MHz Slew Rate COMP = FB 25 V/µs BOOT Voltage Hold Time tBOOT Internal Timer 2 ms VID INPUTS Input Low Voltage VIL(VID) VID(X) 0.3 V Input High Voltage VIH(VID) VID(X) 0.8 V Input Current IIN(VID) −5 µA VID Transition Delay Time2 VID code change to FB change 400 ns No CPU Detection Turn-Off Delay Time2 VID code change to PWM going low 5 µs OSCILLATOR Frequency Range2 f OSC 0.25 9 MHz Frequency Variation fPHASE T A = 25°C, RT = 500 kΩ, 4-phase 170 195 225 kHz T A = 25°C, RT = 250 kΩ, 4-phase 375 kHz T A = 25°C, RT = 121 kΩ, 4-phase 750 kHz Output Voltage VRT R T = 500 kΩ to GND 1.9 2.0 2.1 V RAMPADJ Output Voltage VRAMPADJ RAMPADJ − FB, V FB = 1V, −50 +50 mV RAMPADJ Input Current Range I RAMPADJ 5 125 µA CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA) CSSUM − CSREF (see Figure 3) −1.0 +1.0 mV Input Bias Current, CSREF IBIAS(CSREF) CSREF = 1V −20 +20 µA Input Bias Current, CSSUM IBIAS(CSSUM) CSREF = 1V −10 +10 nA Gain Bandwidth Product GBW(CSA) CSSUM = CSCOMP 10 MHz Slew Rate CCSCOMP = 10 pF 10 V/µs Input Common-Mode Range CSSUM and CSREF 0 3.0 V Output Voltage Range 0.05 3.0 V Output Current ICSCOMP 500 µA Current Limit Latch off Delay Time Internal Timer 8 ms 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not tested in production. Rev. P1 | Page 3 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 4 of 38 Parameter Symbol Conditions Min Typ Max Unit PSI# Input Low Voltage 0.3 V Input High Voltage 0.8 V Input Current −5 µA Assertion Timing Fsw = 300kHz 3.3 µs Deassertion Timing Fsw = 300kHz 825 ns IMON OUTPUT Clamp Voltage 1.0 1.15 V Accuracy 10 × (CSREF − CSCOMP)/RILIM −3 3 % Output Current 800 µA Offset −3 3 mV CURRENT LIMIT COMPARITOR ILIM Bias Current ILIM CSREF − CSCOMP)/RILIM , (CSREF − CSCOMP)=150 mV, RILIMC=7.5 kΩ 20 µA Current Limit Threshold Current I CL 4/3 × IIREF 20 µA CURRENT BALANCE AMPLIFIER Common-Mode Range VSW(X)CM −600 +200 mV Input Resistance RSW(X) SW(X) = 0 V 14 19 25 kΩ Input Current ISW(X) SW(X) = 0 V 7 12 20 µA Input Current Matching 'ISW(X) SW(X) = 0 V −6 +6 % Phase Balance Adjustment Range Low Phase Bal Registers = 00000 -25 % Phase Balance Adjustment Range High Phase Bal Registers = 11111 +25 % DELAY TIMER Internal Timer Delay Time Register = 011 2 ms Timer Range Low Delay Time Register = 000 0.5 ms Timer Range High Delay Time Register = 111 4 ms SOFT START Internal Timer Soft Start Slope Register = 010 0.5 V/ms Timer Range Low Soft Start Slope Register = 000 0.1 V/ms Timer Range High Soft Start Slope Register = 111 1.5 V/ms ENABLE INPUT Input Low Voltage VIL(EN) 0.3 V Input High Voltage VIH(EN) 0.8 V Input Current IIN(EN) −1 µA Delay Time tDELAY(EN) EN > 0.8V , Internal Delay 2 ms ODN / OD1 OUTPUTS Output Low Voltage VOL(ODN/1, ) IOD(SINK) = −400 PA 160 500 mV Output High Voltage VOH(ODN/1) IOD(SOURCE) = 400 PA 4 5 V ODN / OD1 Pull-Down Resistor 60 kΩ OVER-CLOCKING OUTPUTS (OC1, OC2) Output Low Voltage VOL I OC(SINK) = -1 mA 160 500 mV POWER GOOD COMPARATOR Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output −600 −500 −400 mV Undervoltage Adjustment Range Low PWRGD_LO Register = 000 −500 mV Undervoltage Adjustment Range High PWRGD_LO Register = 111 −150 mV Overvoltage Threshold VPWRGD(OV) Relative to DAC output, PWRGD_Hi = 00 200 300 400 mV Overvoltage Adjustment Range Low PWRGD_Hi Register = 11 150 mV Overvoltage Adjustment Range High PWRGD_Hi Register = 00 300 mV Output Low Voltage VOL(PWRGD) I PWRGD(SINK) = −4 mA 150 300 mV Power Good Delay Time Rev. P1 | Page 4 of 36 | www.onsemi.com
Preliminary Technical Data ASP0800 Rev. Pr H| Page 5 of 38 Parameter Symbol Conditions Min Typ Max Unit During Soft Start2 Internal Timer 2 ms VID Code Changing 100 250 µs VID Code Static 200 ns Crowbar Trip Point VCROWBAR Relative to DAC output, PWRGD_Hi = 00 200 300 400 mV Overvoltage Adjustment Range Low PWRGD_Hi Register = 11 150 mV Overvoltage Adjustment Range High PWRGD_Hi Register = 00 300 mV Crowbar Reset Point Relative to FBRTN 250 300 350 mV Crowbar Delay Time tCROWBAR Overvoltage to PWM going low VID Code Changing 100 250 µs VID Code Static 400 ns PWM OUTPUTS Output Low Voltage VOL(PWM) I PWM(SINK) = −400 µA 160 500 mV Output High Voltage VOH(PWM) I PWM(SOURCE) = 400 µA 4 5 V PMBus Interface Logic High Input Voltage VIH(SDA, SCL) 2.1 V Logic Input Low Voltage VIL(SDA, SCL) 0.8 V Hysteresis 500 mV SDA Output Low Voltage VOL I SDA = −6mA 0.4 V Input Current IIH ; IIL −1 1 µA Input Capacitance CSCL, SDA 5 pF Clock Frequency fSCL 400 kHz SCL Falling Edge to SDA Valid Time 1 µs ALERT FAULT OUTPUTS Output Low Voltage VOL I OUT = -6mA 0.4 V Output High Leakage Current I OH V OH = 5V 1 uA ANALOG/DIGITAL CONVERTER Total Unadjusted Error (TUE) ±2 % Differential Non linearity (DNL) TBD Bits 1 LSB Conversion Time Averaging Enabled (32 averages) 80 ms SUPPLY VSYSTEM = 12 V, RSHUNT = 340 Ω VCC2 VCC 4.70 5 5.45 V DC Supply Current IVCC VSYSTEM = 13.2 V, RSHUNT = 340 Ω 21 26 mA UVLO Turn-On Current 6.5 11 mA UVLO Threshold Voltage VUVLO VCC rising 9 V UVLO Turn-Off Voltage VCC falling 4.1 V VCC3 Output Voltage VCC3 I VCC3 = 1mA 3.0 3.3 3.6 V Rev. P1 | Page 5 of 36 | www.onsemi.com
8 BIT
Figure 2. Closed-Loop Output Voltage Accuracy
soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Figure 5. Pin Configuration Table 4. Pin Function Descriptions 1 VCC3 3.3V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3V LDO. configured for Comparator Mode or Interrupt Mode. 4 SDA Digital Input / Output. PMBus serial data bidirectional pin. Requires PMBus pull up. 5 SCL Digital Input. PMBus serial bus clock open drain input. Requires PMBus pull up. 6 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 8 OC1 Over Clocking Bit 1 Output. The pin is connected to the clock control chip to set the over-clocking state. 9 OC2 Over Clocking Bit 2 Output. The pin is connected to the clock control chip to set the over-clocking state. 10 IMON Total Current Output Pin. 11 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, and IILIMFS. 13 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp . 14 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. 15 COMP Error Amplifier Outp ut and Compensation Point. pin and the output voltage sets the no load offset point. currents together to measure the total output current. current sense amplifier and the positioning loop response time. sensing signal for current-limit and IMON. This value can be over-written using the PMBus interface. functions in the same way as OD1. UVLO threshold to signal to the Driver IC that the driver high-side and low-side outputs should go low.
Preliminary Technical Data ASP0800 Rev. Pr H| Page 9 of 38 Pin No. Mnemonic Description 23 to SW8 to SW1 Current Balance Inputs. Inputs for measuring the cu rrent level in each phase. The SW pins of unused phases should be left open. 31 to PWM8 to PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3121. Connecting the PWM8, PWM7, PWM6, PWM5, PWM4, PWM3 and PWM2 outputs to VCC causes that phase to turn off, allowing the ASP0800 to operate as a 1, 2-, 3-, 4-, 5-, 6, 7 or 8-phase controller. 39 VCC Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. 40 to VID7 to VID0 Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 48 PSI Power State Indicator. Pulling this pin low places the controller in lower power state operation. Rev. P1 | Page 9 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 10 of 38 TYPICAL PERFORMANCE CHARACTERISTICS TBD Figure 6 Rev. P1 | Page 10 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 12 of 38 VCC, the 100 µA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving fast response external gate drivers such as the ADP3121 and ADP3122. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ASP0800 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 6. If 4 phases are in use divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ASP0800 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error ampli- fier. This maintains a worst-case specification of ±10 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB is connected through a resistor, R B, to the regulation point, usually the remote sense pin of the microprocessor. FBRTN is connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 70 µA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ASP0800 provides a dedicated current-sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current, for the IMON output and for current-limit detection. Sensing the load current at the output gives the total real time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system, as follows: x Output inductor DCR sensing without a thermistor for lowest cost. x Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature. x Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the average output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. This difference signal is used internally to offset the VID DAC for voltage positioning. This different signal can be adjusted between 50%-150% of the external value using the PMBus Loadline Calibration (0xDE) and Loadline Set (0xDF) commands. The difference between CSREF and CSCOMP is then used as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate. The CPU current can also be monitored over the PMBus. The current limit and the load line can be programmed over PMBus. OUTPUT CURRENT MONITOR IMON is an analog output from the ASP0800 representing the total current being delivered to the load. It outputs an accurate current that is directly proportional to the current set by the ILIMFS resistor. The current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage as per the VR11.1 specification. The size of the resistor is used to set the IMON scaling. If the IMON and the OCP need to be changed based on the TDC of the CPU, then the ILIMFS resistor is the only component that needs to be changed. If the IMON scaling is the only change needed then changing the IMON resistor accomplishes this. The IMON pin also includes an active clamp to limit the IMON voltage to 1.15V MAX while maintaining 900mV MIN full scale accurate reporting. ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function of output current, the CSA gain and load line programming can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed-forward response. Rev. P1 | Page 12 of 36 | www.onsemi.com
the PMBus Phase Bal SW(x) commands (TBD to TBD). in temperature due to layout and airflow considerations. the user first needs to program the required VID Code.
- Program the required VID Code to the
- Set the VID_EN bit (Bit 3) in the VR Config 1A (0xD2)
and on the VR Config 1B (0xD3). termination voltage for the internal PWM ramps. the feedback network between FB and COMP. negative offset is applied when Bit 4 = 1. Table 5. Offset Codes code to the finish code. This change can be positive or negative. VID change resets the internal timer.
provides the transition rate values. Table 6. Transition Rate Codes number of phases to ramp up the output current. The IREF pin is used to set an internal current reference. programs the current based on the 1.8 V output. Typically, RIREF is set to 121 k to program IREF = 15 µA. limit timer is set to 4 times the delay timer. Table 7. Delay Codes the Ton_Rise (0xD5) command code.
Table 9. Current Limit programmed value by using the serial interface. can return to normal operation. EN pin low for a short time. continue to operate in current limit indefinitely. Figure 9. Overcurrent Latch-off Waveforms during the time the output is changing. programmed using the serial interface. protecting the microprocessor from being destroyed. the output capacitors through the inductors. then the system is in OC State TBD and Offset TBD is applied. the control of a master controller. PMBus address and also a suitable resistor value. protecting the microprocessor from being destroyed. the output capacitors through the inductors. then the system is in OC State TBD and Offset TBD is applied. the control of a master controller. PMBus address and also a suitable resistor value.
ASP0800 Preliminary Technical Data Rev. PrH | Page 18 of 38 OUTPUT CROWBAR As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300 mV . The value for the crowbar limit follows the programmable PWRGD high limit. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed. OUTPUT ENABLE AND UVLO For the ASP0800 to begin switching, the input supply current to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.8 V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the ASP0800 is disabled. This holds the PWM outputs at ground and forces PWRGD, ODN and OD1 signals low. In the application circuit (see Figure TBD), the OD1 pin should be connected to the OD inputs of the external drivers for the phases that are always on. The ODN pin should be connected to the OD inputs of the external drivers on the phases that are shut down during low power operation. Grounding the driver OD inputs disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors. OVERCLOCKING (OC) LIMITS AND OFFSETS The ASP0800 includes an overclocking function. The total output current is monitored by the ASP0800 using the IMON output. Read_IOUT Command gives the total current in Amps The IOUT value is compared with the Over Clocking or OC Thresholds. There are three OC thresholds Command TBD = OC Threshold 1; Default = TBD Command TBD = OC Threshold 2; Default = TBD Command TBD = OC Threshold 3; Default = TBD I OUT is first compared with OC3, If IOUT is greater than OC3 then the system is in OC State TBD and Offset TBD is applied. If IOUT is less than OC3 but greater than OC2 then the system is in OC State TBD. If IOUT is less than OC2 but greater than OC1 then the system is in OC State TBD. If IOUT is less than OC1 then the system is in OC State TBD. Each offset state has a corresponding Offset voltage. The offset voltage for each state is programmable in TBD mV steps up to a max value of ±200 mV. Register TBD VR Offset 1 = Offset voltage for State 1, default value = 0x00 Register TBD VR Offset 2 = Offset voltage for State 2, default value = 0x00 Register TBD VR Offset 3 = Offset voltage for State 3, default value = 0x00 Register TBD VR Offset 4 = Offset voltage for State 4, default value = 0x00 PMBUS INTERFACE Control of the ASP0800 is carried out using the PMBus Interface. The physical protocol for PMBus closely matches that of SMBus. The ASP0800 is connected to this bus as a slave device, under the control of a master controller. To setup the PMBus Address the ASP0800 sources a 10uA current from the ADD pin through an external resistor. The voltage is then measured by the ADC and user to set the PMBus address. The table below gives the thresholds for each possible PMBus address and also a suitable resistor value. Table 10: Setting up the PMBus Address Address (8 Bits) High Threshold Low Threshold Suggested Resistor Value 0xC0 0.1 0xC2 0.25 0.15 0xC4 0.5 0.3 0xC6 0.75 0.55 0xC8 1.0 0.8 0xCA 1.4 1.1 0xCC 1.9 1.5 0xCE 2.0 Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or Preliminary Technical Data ASP0800 Rev. Pr H| Page 19 of 38 write operation is limited only by what the master and slave devices can handle. 1. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ASP0800, write operations contain one, two or three bytes, and read operations contain one or two bytes. The command code or register address determines the number of bytes to be read or written, See the register map for more information. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. The first byte of a read or write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write byte operation is shown in Figure 11. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. 2. The read byte operation is shown in Figure 12. First the command code needs to be written to the ASP0800 so that the required data is sent back. This is done by performing a write to the ASP0800 as before, but only the data byte containing the register address is sent, because no data is written to the register. A repeated start is then issued and a read operation is then performed consisting of the serial bus address; R/W bit set to 1, followed by the data byte read from the data register. Preliminary Technical Data ASP0800 Rev. Pr H| Page 19 of 38 write operation is limited only by what the master and slave devices can handle. 1. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ASP0800, write operations contain one, two or three bytes, and read operations contain one or two bytes. The command code or register address determines the number of bytes to be read or written, See the register map for more information. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. The first byte of a read or write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write byte operation is shown in Figure 11. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. 2. The read byte operation is shown in Figure 12. First the command code needs to be written to the ASP0800 so that the required data is sent back. This is done by performing a write to the ASP0800 as before, but only the data byte containing the register address is sent, because no data is written to the register. A repeated start is then issued and a read operation is then performed consisting of the serial bus address; R/W bit set to 1, followed by the data byte read from the data register. Rev. P1 | Page 17 of 36 | www.onsemi.com
- After the last data byte the master asserts a No ACK
- The master asserts a STOP condition on SDA
Figure 19. Block Write to a Command Coder Bit 3 SMB_TO_EN = 1; PMBus timeout enabled. Bit 3 TODIS = 0; PMBus timeout disabled (default).
Table 11. VR11 and VR10.x VID Codes for the ASP0800
Preliminary Technical Data ASP0800 Rev. Pr H| Page 25 of 38 VR11 DAC CODES: VIDSEL = HIGH OUTPUT VID7 VID6 VID5 VI D4 VID3 VID2 VID1 VID0 1.30625 0 0 1 1 0 0 0 1 1.30000 0 0 1 1 0 0 1 0 1.29375 0 0 1 1 0 0 1 1 1.28750 0 0 1 1 0 1 0 0 1.28125 0 0 1 1 0 1 0 1 1.27500 0 0 1 1 0 1 1 0 1.26875 0 0 1 1 0 1 1 1 1.26250 0 0 1 1 1 0 0 0 1.25625 0 0 1 1 1 0 0 1 1.25000 0 0 1 1 1 0 1 0 1.24375 0 0 1 1 1 0 1 1 1.23750 0 0 1 1 1 1 0 0 1.23125 0 0 1 1 1 1 0 1 1.22500 0 0 1 1 1 1 1 0 1.21875 0 0 1 1 1 1 1 1 1.21250 0 1 0 0 0 0 0 0 1.20625 0 1 0 0 0 0 0 1 1.20000 0 1 0 0 0 0 1 0 1.19375 0 1 0 0 0 0 1 1 1.18750 0 1 0 0 0 1 0 0 1.18125 0 1 0 0 0 1 0 1 1.17500 0 1 0 0 0 1 1 0 1.16875 0 1 0 0 0 1 1 1 1.16250 0 1 0 0 1 0 0 0 1.15625 0 1 0 0 1 0 0 1 1.15000 0 1 0 0 1 0 1 0 1.14375 0 1 0 0 1 0 1 1 1.13750 0 1 0 0 1 1 0 0 1.13125 0 1 0 0 1 1 0 1 1.12500 0 1 0 0 1 1 1 0 1.11875 0 1 0 0 1 1 1 1 1.11250 0 1 0 1 0 0 0 0 1.10625 0 1 0 1 0 0 0 1 1.10000 0 1 0 1 0 0 1 0 1.09375 0 1 0 1 0 0 1 1 OFF N/A OFF N/A OFF N/A OFF N/A 1.08750 0 1 0 1 0 1 0 0 1.08125 0 1 0 1 0 1 0 1 1.07500 0 1 0 1 0 1 1 0 1.06875 0 1 0 1 0 1 1 1 1.06250 0 1 0 1 1 0 0 0 1.05625 0 1 0 1 1 0 0 1 1.05000 0 1 0 1 1 0 1 0 1.04375 0 1 0 1 1 0 1 1 1.03750 0 1 0 1 1 1 0 0 1.03125 0 1 0 1 1 1 0 1 1.02500 0 1 0 1 1 1 1 0 Rev. P1 | Page 23 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 26 of 38 VR11 DAC CODES: VIDSEL = HIGH OUTPUT VID7 VID6 VID5 VI D4 VID3 VID2 VID1 VID0 1.01875 0 1 0 1 1 1 1 1 1.01250 0 1 1 0 0 0 0 0 1.00625 0 1 1 0 0 0 0 1 1.00000 0 1 1 0 0 0 1 0 0.99375 0 1 1 0 0 0 1 1 0.98750 0 1 1 0 0 1 0 0 0.98125 0 1 1 0 0 1 0 1 0.97500 0 1 1 0 0 1 1 0 0.96875 0 1 1 0 0 1 1 1 0.96250 0 1 1 0 1 0 0 0 0.95625 0 1 1 0 1 0 0 1 0.95000 0 1 1 0 1 0 1 0 0.94375 0 1 1 0 1 0 1 1 0.93750 0 1 1 0 1 1 0 0 0.93125 0 1 1 0 1 1 0 1 0.92500 0 1 1 0 1 1 1 0 0.91875 0 1 1 0 1 1 1 1 0.91250 0 1 1 1 0 0 0 0 0.90625 0 1 1 1 0 0 0 1 0.90000 0 1 1 1 0 0 1 0 0.89375 0 1 1 1 0 0 1 1 0.88750 0 1 1 1 0 1 0 0 0.88125 0 1 1 1 0 1 0 1 0.87500 0 1 1 1 0 1 1 0 0.86875 0 1 1 1 0 1 1 1 0.86250 0 1 1 1 1 0 0 0 0.85625 0 1 1 1 1 0 0 1 0.85000 0 1 1 1 1 0 1 0 0.84375 0 1 1 1 1 0 1 1 0.83750 0 1 1 1 1 1 0 0 0.83125 0 1 1 1 1 1 0 1 0.82500 0 1 1 1 1 1 1 0 0.81875 0 1 1 1 1 1 1 1 0.81250 1 0 0 0 0 0 0 0 0.80625 1 0 0 0 0 0 0 1 0.80000 1 0 0 0 0 0 1 0 0.79375 1 0 0 0 0 0 1 1 0.78750 1 0 0 0 0 1 0 0 0.78125 1 0 0 0 0 1 0 1 0.77500 1 0 0 0 0 1 1 0 0.76875 1 0 0 0 0 1 1 1 0.76250 1 0 0 0 1 0 0 0 0.75625 1 0 0 0 1 0 0 1 0.75000 1 0 0 0 1 0 1 0 0.74375 1 0 0 0 1 0 1 1 0.73750 1 0 0 0 1 1 0 0 0.73125 1 0 0 0 1 1 0 1 0.72500 1 0 0 0 1 1 1 0 0.71875 1 0 0 0 1 1 1 1 0.71250 1 0 0 1 0 0 0 0 Rev. P1 | Page 24 of 36 | www.onsemi.com
Preliminary Technical Data ASP0800 Rev. Pr H| Page 27 of 38 VR11 DAC CODES: VIDSEL = HIGH OUTPUT VID7 VID6 VID5 VI D4 VID3 VID2 VID1 VID0 0.70625 1 0 0 1 0 0 0 1 0.70000 1 0 0 1 0 0 1 0 0.69375 1 0 0 1 0 0 1 1 0.68750 1 0 0 1 0 1 0 0 0.68125 1 0 0 1 0 1 0 1 0.67500 1 0 0 1 0 1 1 0 0.66875 1 0 0 1 0 1 1 1 0.66250 1 0 0 1 1 0 0 0 0.65625 1 0 0 1 1 0 0 1 0.65000 1 0 0 1 1 0 1 0 0.64375 1 0 0 1 1 0 1 1 0.63750 1 0 0 1 1 1 0 0 0.63125 1 0 0 1 1 1 0 1 0.62500 1 0 0 1 1 1 1 0 0.61875 1 0 0 1 1 1 1 1 0.61250 1 0 1 0 0 0 0 0 0.60625 1 0 1 0 0 0 0 1 0.60000 1 0 1 0 0 0 1 0 0.59375 1 0 1 0 0 0 1 1 0.58750 1 0 1 0 0 1 0 0 0.58125 1 0 1 0 0 1 0 1 0.57500 1 0 1 0 0 1 1 0 0.56875 1 0 1 0 0 1 1 1 0.56250 1 0 1 0 1 0 0 0 0.55625 1 0 1 0 1 0 0 1 0.55000 1 0 1 0 1 0 1 0 0.54375 1 0 1 0 1 0 1 1 0.53750 1 0 1 0 1 1 0 0 0.53125 1 0 1 0 1 1 0 1 0.52500 1 0 1 0 1 1 1 0 0.51875 1 0 1 0 1 1 1 1 0.51250 1 0 1 1 0 0 0 0 0.50625 1 0 1 1 0 0 0 1 0.50000 1 0 1 1 0 0 1 0 OFF 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1 Rev. P1 | Page 25 of 36 | www.onsemi.com
Table 1. PMBus Commands for the ASP0800 the power to the ASP0800 is cycled.
Preliminary Technical Data ASP0800 Rev. Pr H| Page 29 of 38 Cmd Code R/W Default Description # Bytes Comment 0x19 R 0xB0 Capability 1 This command allows the host to get some information on the PMBus device Bit Default Comment 7 1 PEC (Packet Error Checking is supported) 6:5 01 Max supported bus speed is 400kHz 4 1 ASP0800 has an SMBus ALERT pin and ARA is supported 3:0 000 Reserved for future use 0x20 R 0x20 VOUT_MODE 1 The ASP0800 supports VID mode for programming the output voltage. 0x21 R/W 0x00 VOUT_COMMAND 2 Sets the output voltage using VID. 0x25 R/W 0x0020 VOUT_MARGIN_HIGH 2 Sets the output voltage when operation command is set to Margin High. Programmed in VID Mode. 0x26 R/W 0x00B2 VOUT_MARGIN_LOW 2 Sets the output voltage when operation command is set to Margin Low. Programmed in VID Mode. 0x38 R/W 0x0001 IOUT_CAL_GAIN 2 Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in 1/: 0x39 R/W 0x0000 IOUT_CAL_OFFSET 2 This offset is used to null out any offsets in the output current sensing circuitry. Units are Amps 0x4A R/W 0x0064 IOUT_OC_WARN_LIMIT 2 This sets the high current limit. Once this limit is exceeded IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and an ALERT is generated. This limit is set in Amps. 0x6A R/W 0x012C POUT_OP_WARN LIMIT 2 This sets the output power over power warn limit. Once exceeded Bit 0 of the Status IOUT Command gets set and the ALERT output gets asserted (if not masked) 0x78 R 0x00 STATUS BYTE 1 Bit Name Description
7 BUSY A fault was declared because the ASP0800
was busy and unable to respond
6 OFF This bit is set whenever the ASP0800 is not
5 VOUT_
This bit gets set whenever the ASP0800 goes into OVP mode.
4 IOUT_
This bit gets set whenever the ASP0800 latches off due to an over current event.
3 VIN_U
V Not supported
2 TEMP Not supported
1 CML A Communications, memory or logic fault
0 None
A fault has occurred which is not one of the above Rev. P1 | Page 27 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 30 of 38 Cmd Code R/W Default Description # Bytes Comment 0x79 R 0x0000 STATUS WORD 2 Byte Bit Name Description Low 7 Res Reserved for future use Low 6 OFF This bit is set whenever the ASP0800 is not switching Low 5 VOUT_ OV This bit gets set whenever the ASP0800 goes into OVP mode Low 4 IOUT_O C This bit gets set whenever the ASP0800 latches off due to an over current event Low 3 Res Reserved for future use Low 2 TEMP Not supported Low 1 CML A Communications, memory or logic fault has occurred Low 0 None of the Above A fault has occurred which is not one of the above High 7 VOUT This bit gets set whenever the measured output voltage goes outside its power good limits or an OVP event has taken place, i.e. any bit in Status VOUT is set High 6 Iout/Po ut This bit gets set whenever the measured output current or power exceeds its warning limit or goes into OCP . i.e. any bit in Status IOUT is set High 5 INPUT Not supported High 4 MFR A manufacturer specific warning or fault has occurred High 3 POWER GOOD# The Power Good signal is deasserted. Same as PowerGood in General Status High 2 Res Reserved for future use High 1 OTHER A Status bit in Status Other is asserted High 0 Res Reserved for future use Rev. P1 | Page 28 of 36 | www.onsemi.com
Preliminary Technical Data ASP0800 Rev. Pr H| Page 31 of 38 Cmd Code R/W Default Description # Bytes Comment 0x7A R 0x00 STATUS VOUT 1 Bit Name Description
7 Res Not supported
6 VOUT_OVERVO
This bit gets set whenever the measured output voltage goes above its powergood limit
5 VOUT_UNDERV
This bit gets set whenever the measured output voltage goes below its powergood limit
4 Res Reserved for future use
3 VOUT_MAX
Not supported, Can’t program an output greater than max VID as there are no bits to program it
2 Res Not supported
1 Res Not supported
0 Res Not supported
0x7B R 0x00 STATUS IOUT 1 Bit Name Description
7 IOUT
This bit gets set if the ASP0800 latches off due to an OCP Event
6 Reserved Reserved for future use
5 IOUT
This bit gets set if IOUT exceeds its programmed high warning limit
4 Reserved Reserved for future use
3 Reserved Reserved for future use
2 Reserved Reserved for future use
0 POUT Over
This bit gets set if the measured POUT exceeds the Warn Limit 0x7E R 0x00 STATUS CML 1 Bit Name Description
7 Invalid or
6 Invalid or
5 PEC Failed Supported
4 Memory Fault
3 Processor Fault
2 Reserved Supported
0 Other memory
Rev. P1 | Page 29 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 32 of 38 Cmd Code R/W Default Description # Bytes Comment 0x80 R 0x00 STATUS_ALERT 1 Bit Name Description
7 Res Reserved for future use
6 Res Reserved for future use
5 Res Reserved for future use
3 Res Reserved for future use
2 VMON WARN Gets asserted when VMON exceeds
1 Res Reserved for future use
0 Res Reserved for future use
0x8B R 0x00 READ_ VOUT 2 Readback output volt age. Voltage is read back in VID Mode 0x8C R 0x00 READ_IOUT 2 Readback output current. Current is read back in Linear Mode (Amps) 0x96 R 0x00 READ_POUT 2 Readback Output Power, read back in Linear Mode in W’s. 0x99 R 0x41 MFR_ID 1 0x41 0x9A R 0x4000 MFR_MODEL 2 0x3298 0x9B R 0x00 MFR_REVISION 1 0 Rev. P1 | Page 30 of 36 | www.onsemi.com
Table 2. Manufacturer Specific Command Codes for the ASP0800
1 Reset Resets all registers to their POR
0 Lock Logic 1 locks all limit values to their
phases turned on during PSI. PMBus Timeout feature is enabled.
1 ALERT_EN Enable the ALERT pin
ASP0800 Preliminary Technical Data Rev. PrH | Page 34 of 38 Cmd Code R/W Default Description # Bytes Comment 0xD2 R/W 0x52 VR Config. 1A 1 Bit Name Description 6:4 Phase Enable Bits 000 = Phase 1 001 = Phase 2 010 = Phase 3 011 = Phase 4 100 = Phase 5 101 = Phase 6 110 = Phase 7 111 = Phase 8
3 VID_EN When the VID_EN bit is set to 1, the
VID code in the VOUT_COMMAND register sets the output voltage. When VID_EN is set to 0, the output voltage follows the VID input pins.
2 LOOP_EN When the LOOP_EN bit is set to 1 in
both registers, the control loop test function is enabled. This allows measurement of the control loop AC gain and phase response with appropriate instrumentation. The control loop signal insertion pin is IMON. The control loop output pin is COMP .
1 CLIM_EN When CLIM_EN is set to 1, the
current limit time out latch off functions normally. When this bit is set to 0 in both registers, the current limit latch off is disabled. In this state, the part can be in current limit indefinitely. 0xD3 R/W 0x52 VR Config. 1B 1 This register is for security reasons. It has the same format as register 0xD2. Bits need to be set in both registers for the function to take effect. 0xD4 R/W 0x03 Ton Delay 1 0xD5 R/W 0x02 Ton Rise 1 0xD6 R/W 0x03 Ton Transition 1 0xD7 R 0x00 VMON Voltage 2 This is a 16 bit value that reports back the voltage measured between FB and FBRTN 0xD8 R 0x00 EN/VTT Voltage 2 This is a 16 bit valu e that reports back the voltage on the VTT Pin. 0xD9 R/W 0x00 OC Offset 1 1 This offset is added to the VID Code when in overclocking state 00 0xDA R/W 0x00 OC Offset 2 1 This offset is added to the VID Code when in overclocking state 01 0xDB R/W 0x00 OC Offset 3 1 This offset is added to the VID Code when in overclocking state 10 0xDC R/W 0x00 OC Offset 4 1 This offset is added to the VID Code when in overclocking state 11 0xDC R/W 0x00 VOUT_CAL 1 Offset Co mmand Code for Vout, max +/- 200mV 0xDE R/W 0x10 Load Line Calibration 1 This value sets the internal load line attenuation DAC calibration value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 = 100% of external Load Line Rev. P1 | Page 32 of 36 | www.onsemi.com
Preliminary Technical Data ASP0800 Rev. Pr H| Page 35 of 38 Cmd Code R/W Default Description # Bytes Comment 0xDF R/W 0x00 Load Line Set 1 This value sets the internal load line attenuation DAC value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 = 100% of external Load Line 0xE0 R/W 0x00 PWRGD Hi Threshold 1 This value sets the PWRGD Hi Threshold and the CROWBAR Threshold: Code = 00, PWRGD HI = 300mV (default) Code = 01, PWRGD HI = 250mV Code = 10, PWRGD HI = 200mV Code = 11, PWRGD HI = 150mV 0xE1 R/W 0x00 PWRGD Lo Threshold 1 This value sets the PWRGD Lo Threshold: Code = 000, PWRGD Lo = -500mV (default) Code = 001, PWRGD Lo = -450mV Code = 010, PWRGD Lo = -400mV Code = 011, PWRGD Lo = -350mV Code = 100, PWRGD Lo = -300mV Code = 101, PWRGD Lo = -250mV Code = 110, PWRGD Lo = -200mV Code = 111, PWRGD Lo = -150mV 0xE2 R/W 0x10 Current Limit Threshold 1 This value sets the internal current limit adjustment value. The default current limit is programmed using a resistor to ground on the LIMIT pin. The value of this register adjusts this value by a percentage between 50% and 146.7%. Each LSB represents a 3.33% change in the current limit threshold. 11111 = 146.7% of external current limit 10000 = 100% of external current limit (default) 00000 = 50% of external current limit 0xE3 R/W 0x10 Phase Bal SW1 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE4 R/W 0x10 Phase Bal SW2 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE5 R/W 0x10 Phase Bal SW3 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE6 R/W 0x10 Phase Bal SW4 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 Rev. P1 | Page 33 of 36 | www.onsemi.com
ASP0800 Preliminary Technical Data Rev. PrH | Page 36 of 38 Cmd Code R/W Default Description # Bytes Comment 0xE7 R/W 0x10 Phase Bal SW5 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE8 R/W 0x10 Phase Bal SW6 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xE9 R/W 0x10 Phase Bal SW7 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xEA R/W 0x10 Phase Bal SW8 1 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by +/-25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 0xEC R/W 0x00 OC_Counter Limit 1 0xEE R/W 0x00 OC Threshold 1 1 0xEF R/W 0xFF OC Threshold 2 1 0xF0 R/W 0xFF OC Threshold 3 1 0xF1 R 0x00 ICPU MSB 1 0xF2 R 0x00 OC Status 1 0xF6 R/W 0x0002 VMON Warn Limit 2 VMON Warn Limit 0xF9 R/W 0x00 Mask ALERT 1 Bit Name Description
7 Mask Vout Masks any ALERT caused by bits in
6 Mask IOUT Masks any ALERT caused by bits in
5 Mask OC_Chng Masks any ALERT caused by
4 Mask
3 Mask CML Masks any ALERT caused by bits in
2 VMON Masks any ALERT caused by VMON
exceeding its high or low limit
1 Reserved Reserved
0 Mask POUT Masks any ALERT caused by POUT
exceeding its programmed limit 0xFA R/W 0x00 Mask FAULT 1 Bit Name Description
7 Mask Vout
Masks any ALERT caused by OVP
6 Mask IOUT
Masks any ALERT caused by OCP Rev. P1 | Page 34 of 36 | www.onsemi.com
Preliminary Technical Data ASP0800 Rev. Pr H| Page 37 of 38 Cmd Code R/W Default Description # Bytes Comment 0xFB R 0x0C General Status 1 Bit Name Description
6 ALERT
5 POWER GOOD Replaced by Bit 3 of the Status Word
4 RDY
0xFC R 0x00 Phase Status 1 Bit. Name Description
7 Phase 8 This bit is set to 1 when Phase 8 is
6 Phase 7 This bit is set to 1 when Phase 7 is
5 Phase 6 This bit is set to 1 when Phase 6 is
4 Phase 5 This bit is set to 1 when Phase 5 is
3 Phase 4 This bit is set to 1 when Phase 4 is
2 Phase 3 This bit is set to 1 when Phase 3 is
1 Phase 2 This bit is set to 1 when Phase 2 is
0 Phase 1 This bit is set to 1 when Phase 1 is
Rev. P1 | Page 35 of 36 | www.onsemi.com
0.50 BSC
0.20 REF
0.80 MAX
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
0.25 MIN
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