ASL1507SHN NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 56
Technical content
ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Rev. 1 — 26 April 2018 Product data sheet
1 Introduction
The ASL1507SHN is a highly integrated and flexible one-phase DC-to-DC boost converter IC. The IC has one integrated gate driver which can drive one external power metal-oxide-semiconductor field-effect transistor (MOSFET) and two integrated proportional-integral (PI) controllers which can regulate the output voltage. It has a serial peripheral interface (SPI) allowing control and diagnostic communication with an external microcontroller. The ASL2507SHN is a highly integrated and flexible two-phase DC-to-DC boost converter IC. The IC has two integrated gate drivers which can drive two external power metal-oxide-semiconductor field-effect transistors (MOSFETs) and two integrated proportional-integral (PI) controllers which can regulate the output voltage on both channels. It has a serial peripheral interface (SPI) allowing control and diagnostic communication with an external microcontroller. The ASL1507SHN; ASL2507SHN is designed primarily for use in automotive LED lighting applications and provides an optimized supply voltage for ASLx416/17SHN multichannel LED buck driver. For simplicity, the data sheet states always 'gate drivers' and 'output voltages'. The ASL1507SHN has only one gate driver and can only drive one output.
2 General description
The ASL1507SHN; ASL2507SHN has a fixed frequency peak current mode control with parabolic/non‑linear slope compensation. It can operate with input voltages from 5.5 V to 40 V. It can be configured in boost topology via SPI for output voltages of up to 80 V, to power the LED buck driver IC. The ASL1507SHN is a single-phase boost converter with one output voltage. The ASL2507SHN is a two-phase boost converter, which can have two independent outputs. The ASL2507SHN is configurable via the SPI interface, as a single output converter with either one phase or two phases, or two independent output voltages. In case the SPI communication is lost in an abnormal situation, it switches to limp-home mode operation ensuring system safety. The ASL1507SHN; ASL2507SHN boost converter can drive up to two external low-side N channel MOSFETs from an internally regulated adjustable supply. It can drive either logic or standard level MOSFETs. The integrated SPI interface also allows for programming the supply under/overvoltage range, output voltage range, frequency spread spectrum, and DC-to-DC switching frequency. It enables the optimization of external components and flexibility for electromagnetic compatibility (EMC) design. This interface can be used also to provide diagnostic information such as the device temperature, battery voltage, VGG voltage, output voltage etc.
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018 The ASL1507SHN; ASL2507SHN integrates a non-volatile memory (NVM) to save the default configuration internally. The configuration includes boost ramp-up, boost voltage, frequency setting, error detection and etc. The default configuration is used in limp‑home mode (SPI fail) and autonomous mode (no MCU). Additional features include input undervoltage lockout and thermal shutdown when the junction temperature of the ASL1507SHN; ASL2507SHN exceeds Tsd(otp). The device is housed in a very small HVQFN32 package with an exposed thermal pad. It is designed to meet the stringent requirements of automotive applications. It is fully AEC-Q100 grade 1 qualified. It operates over the −40 °C to +125 °C ambient automotive temperature range.
3 Features and benefits
- AEC-Q100 grade 1 qualified
- Limp-home mode ensuring system safety
- Up to two flexible output voltages with 3 % accuracy programmable via SPI
- Single phase on each output or double phase on one output
- Fixed frequency operation via built-in oscillator from 125 kHz to 700 kHz
- Slope compensation to track the frequency and output voltage
- Programmable control loop compensation
- Programmable spread spectrum functionality
- Gate switching is halted when overvoltage on output is detected
- Programmable gate voltage
- Low electromagnetic emission (EME) and high electromagnetic immunity (EMI)
- Output voltage monitoring
- Supply voltage measurement
- Control signal to enable the device low quiescent current < 5 μA when EN = 0
- Read-back programmed voltage and frequency range via SPI
- Junction temperature monitoring via SPI
- Small package outline HVQFN32
- Wide operating input voltage range from +5.5 V to +40 V
- Operating ambient temperature range of −40 °C to +125 °C
4 Applications
- Automotive LED lighting – Daytime running lights – Position or park light – Low beam – High beam – Turn indicator – Fog light – Cornering light
5 Ordering information
Table 1. Ordering information
6 Block diagram
Figure 1. Block diagram for ASL1507SHN
Figure 2. Block diagram for ASL2507SHN
7 Pinning information
7.1 Pinning
Figure 3. Pin configuration for ASL1507SHN Figure 4. Pin configuration for ASL2507SHN
7.2 Pin description
Table 2. Pin description
[1] Not connected pins are internally not connected and can be left floating or can be connected to any voltage level. [2] See Figure 6 and Figure 19 for recommend connections for pin FB1 and FB2. [3] Internally connected pins should be connected to GND. package should be soldered to board ground (and not to any other voltage level).
8 Functional description
8.1 Operating modes
Figure 5. State diagram
Table 3. Operating modes [1] Setting the bit CFG_DN to logic 0 also grants write access to the configuration registers. Table 4. Operation mode register (address 56h)
8.1.1 Reset mode
below the power-on detection threshold voltage Vth(det)pon or the pin EN is LOW.
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
8.1.2 Configuration mode
The ASL1507SHN; ASL2507SHN switches from reset mode to configuration mode, as soon as the input voltage is above the power-on detection threshold voltage Vth(det)pon and pin EN is HIGH. The configuration registers can be set when the ASL1507SHN; ASL2507SHN is in the configuration mode.
8.1.3 Standby mode
The ASL1507SHN; ASL2507SHN switches from operation to standby mode when bit CFG_DN is set to logic 0 while bit AUTO is set to logic 0 as well. In standby mode VO1 and VO2 are turned off while VGG remains on.
8.1.4 Operation mode
The ASL1507SHN; ASL2507SHN switches from configuration mode to operation mode, as soon as the configuration done bit is set. Once the bit is set to logic 1, the configuration registers are locked and cannot be changed. In operation mode, the output is available as configured via the SPI interface. Setting the bit VO1EN or VO2EN, starts up VGG. Once VGG is in regulation (signaled by bit VGG_OK), the output voltages VO1 and VO2 are turned on accordingly. When the converters are on, the battery monitoring functionality is available.
8.1.5 Fail silent mode
The ASL1507SHN; ASL2507SHN switches from operation, configuration, standby, or limp-home mode to fail silent mode, when the junction temperature exceeds the overtemperature shutdown threshold or a VGG error is detected. It also switches modes when the input voltage is below the undervoltage detection threshold or above the overvoltage detection threshold. In fail silent mode, all outputs are turned off and only the SPI interface remains operational.
8.1.6 Limp-home mode
The ASL1507SHN; ASL2507SHN limp-home mode is activated by detecting loss of SPI communication. In limp-home mode, the outputs are operating according to predefined conditions in an NVM; see Section 8.12 for more information. During limp-home mode operation, the SPI interface remains functional but only the limp‑home mode control register can be written. The other registers offer only read access.
8.1.7 NVM access mode
The ASL1507SHN; ASL2507SHN switches from configuration mode to NVM access mode when the NVM access mode entry command is given. In NVM access mode, the NVM settings can be defined and read back.
8.2 Boost converter configuration
a MOSFET and a diode as shown in Figure 6. Figure 6. Phase of the boost converter with IC and application connections ASL2507SHN as shown in Figure 7. Figure 7. Mapping of virtual phases (V1_1 to V2_4) to physical phases (G1 and G2)
8.2.1 Configuration of the virtual phases
The ASL2507SHN can generate up to two internal phases for up to two virtual outputs. phases are generated for the individual virtual outputs.
Table 5. SS scenario logic 1 (address 0Bh) Table 6. SS scenario logic 2 (address 0Ch)
8.2.2 Association of gate drivers to the output voltages
Each phase that the ASL2507SHN offers must be associated to one of the outputs. phase to one output and one phase to another one.
Table 7. Gate driver output (address 02h)
8.2.3 Association of gate drivers to the internal phase generation
connecting to physical gate driver. Table 8. Gate driver phase (address 0Fh) Table 9. Phase select configuration (address 10h)
8.2.4 Enabling of connected phases
The gate driver enable register is used to configure which of the phases is active.
Table 10. Gate driver enable (address 01h) [1] For the ASL1507SHN, this bit is reserved.
8.2.5 Configuration of the boost converter frequencies
frequency of the boost converter. Figure 8. Phase control generator Table 11. Clock divider for VO1 (address 09h)
Table 12. Clock divider for VO2 (address 0Ah) Table 13. Phase-off time and phase delay of output 1 (address 0Dh) Table 14. Phase-off time and phase delay of output 2 (address 0Eh) possible settings of the delay between the phases close to 32.
8.2.6 Control loop parameter setting
according to the external components and the operating frequency. Table 15. Loop filter proportional configuration (address 11h) Table 16. Loop filter integral configuration (address 12h) Table 17. Slope compensation configuration (address 13h)
Table 18. Current sense slope resistor configuration (address 14h)
8.3 Output voltage programmability
and output overvoltage protection of the output via the SPI interface.
8.3.1 Output voltage target programming
than the supply voltage minus the drop of the converter diode (Dx in Figure 6). Table 19. Output voltage 1 register (address 03h) Table 20. Output voltage 2 register (address 04h)
8.3.2 Output overvoltage protection programming
halt of the energy delivery to the output.
toggling again. The regulation loop regulates the output back to the target value. case of overshoots due to load changes. Table 21. Limit voltage output 1 register (address 05h) Table 22. Limit voltage output 2 register (address 06h)
8.3.3 Output voltage ramp up
Table 23. Ramp up output 1 (address 1Fh)
Table 24. Ramp up output 2 (address 20h)
8.3.4 Dead-band setting
changed in configuration mode. Table 25. Internal register 5 (address 30h)
8.4 Frequency spread spectrum
fsw(set) is the set switching frequency. fosc(int) is the internal oscillator frequency. x is according to Table 29 and Table 30. Table 26. Spread spectrum enable register (address 1Ch)
5 RESTART_TEMP restart after TEMP
4 RESTART_VBAT restart after VBAT
Table 27. SS scenario logic 1 register (address 0Bh)
3 EN_P4_1 phase 4 enabled - see Table 5
2 EN_P3_1 phase 3 enabled - see Table 5
1 EN_P2_1 phase 2 enabled - see Table 5
0 EN_P1_1 phase 1 enabled - see Table 5
Table 28. SS scenario logic 2 register (address 0Ch)
3 EN_P4_2 phase 4 enabled - see Table 6
2 EN_P3_2 phase 3 enabled - see Table 6
1 EN_P2_2 phase 2 enabled - see Table 6
0 EN_P1_2 phase 1 enabled - see Table 6
Table 29. Ramp profile Table 30. Random profile
8.5 Coil peak current limitation
be realized with this function. switching cycle to ensure stable operation of the system. be placed well above the maximum expected current. Table 31. Maximum coil current VO1 register (address 07h) Table 32. Maximum coil current VO2 register (address 08h)
8.6 Enabling the output voltage
operation mode, the output voltages are turned on with the bit VO1EN and VO2EN. tstartup the gate drivers start switching, provided the bit VGG_OK is set.
Table 33. Function control register (address 00h)
8.7 Gate voltage supply
Table 34. VGG control register (address 15h); bit 4 in NVM address 00h register is set to logic 0
Table 35. VGG control register (address 15h); bit 4 in NVM address 00h register is set to logic 1 operates, parameters of VGG are not guaranteed.
8.7.1 Gate voltage supply diagnostics
- VGG available; details can be found in Section 8.10
- VGG protection active; details can be found in Section 8.10
8.8 Supply voltage monitoring
allows the system to monitor the supply voltage without additional external components. It also offers the option to put an automatic undervoltage/overvoltage protection in place.
8.8.1 Battery voltage measurement
or when bit 6 in SPI register 00h is set to logic 1. Table 36. Battery voltage register (address 45h)
8.8.2 Undervoltage detection
The ASL1507SHN; ASL2507SHN offers a variable undervoltage detection threshold. and the gate pin stops toggling and no more power is delivered to the output. Table 37. Undervoltage threshold register (address 1Bh)
8.8.3 Overvoltage detection
The ASL1507SHN; ASL2507SHN offers a variable overvoltage detection threshold. Table 38. Overvoltage threshold register (address 1Ah)
8.9 Junction temperature information
Table 39. Junction temperature register (address 46h)
8.10 Diagnostic information
each bit can be found in the following subsections. Table 40. Diagnostic register (address 5Fh)
0 VO1 is deviating from the target value7 VO1_OK VO1 regulated
1 VO1 is regulated to the target value
0 VO2 is deviating from the target value6 VO2_OK VO2 regulated
1 VO2 is regulated to the target value
0 VGG is not available5 VGG_OK VGG regulation OK
1 VGG is available
0 VGG protection not active0 VGG_ERR VGG error
1 VGG protection has turned on and VGG is deactivated
8.10.1 Bit VBAT_OV
enables an option to select the auto recover or fail silent mode. of the clearing of the bit, the device stays in fail silent mode.
8.10.2 Bit VBAT_UV
Section 8.8.2. It indicates that the device has detected an undervoltage condition. of the clearing of the bit, the device stays in fail silent mode.
8.10.3 Bit SPI_ERR
commands. When the command is not allowed, the SPI_ERR bit is set. A write access to the diagnostic register or entering off mode, clears the bit.
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
8.10.4 Bit TJ_ERR
The bit TJ_ERR indicates that the junction temperature has exceeded the maximum allowable temperature and the device has entered fail silent mode. A write access to the diagnostic register or entering off mode, clears the bit. Independent of the clearing of the bit, the device stays in fail silent mode.
8.10.5 Bit VGG_ERR
The bit VGG_ERR is set when the gate voltage did not reach the VGG_OK window (when Vdrv(G)VGG_OK is within the range) within tstartup. Once bit VGG_ERR is set, it indicates that an error on the gate voltage regulator has been detected and the device has entered fail silent mode. A write access to the diagnostic register clears the VGG_ERR bit. The device stays in fail silent mode irrespective of the clearing of the bit.
8.10.6 Bit VGG_OK
The bit VGG_OK indicates that the gate driver voltage is regulated to the target voltage and allows the gate drivers to drive the gate driver pins. If the gate driver voltage is outside the VGG_OK window (Vreg(VGG_OK)) after tstartup, the device clears the VGG_OK bit and the device enters fail silent mode.
8.10.7 Bits VO1_OK and VO2_OK
The bits VO1_OK and VO2_OK indicate whether the output voltage is regulated to the target value. The bits are set as soon as the corresponding output voltage is VO(VO_OK) for more than tfltr(Vo). The bits are cleared when the corresponding output is not equal to VO(VO_OK) for more than tfltr(Vo).
8.11 Restart on error
In case the ASL1507SHN; ASL2507SHN enters fail silent mode, it switches off the outputs. In default mode, the EN pin must be cycled and the ASL1507SHN; ASL2507SHN should be reconfigured to start operation. In another mode of operation, ASL1507SHN; ASL2507SHN can be configured which does not require the EN pin cycling. In this mode, when the error condition is resolved, the state machine automatically exits the fail silent mode. The operation restarts as configured prior to entering the fail silent mode. This auto restart mode can be controlled through NVM by programming the bits. Restart can be independently done for TJ_ERR, VBAT_UV and VBAT_OV conditions; refer to Section 8.4.
8.12 Limp-home mode
according to predefined conditions stored in an NVM. populates these settings into the registers and operates according to them. operates according to the SPI register. Limp-home offer the same operational features as normal operation. Bit 3 in register 54h indicates the limp-home mode status of the device. Table 41. Limp-home mode indication (address 54h)
8.12.1 Limp-home mode activation
expires, the device enters into limp-home mode. Refer to Section 8.13.1 for more information on starting the NVM write sequence.
8.12.2 Limp-home mode operation
ASL1507SHN; ASL2507SHN modifies the control registers accordingly. Figure 9. Limp-home mode startup
8.12.3 Limp-home mode deactivation
must be written to the limp-home mode control register (address 3Ch). Table 42. Limp-home mode deactivation sequence accessible as defined for operation mode again.
8.12.4 Limp-home mode control register
The limp-home mode control register allows control of the limp-home mode. Table 43. Limp-home mode control register (address 3Ch)
8.13 NVM memory
generated and in case of errors the corrections are done automatically. Table 44. ECC code register (address 39h)
7 EEB disables ECC
6 ECB disables ECC
Table 45. NVM control register (address 3Ah) [1] NVM accesss is only executed when NVM_DONE is set to logic 1. Table 46. NVM status register (address 55h)
0 NVM action in progress0 NVM_DONE NVM action
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
8.13.1 NVM write sequence
To write an NVM register, the device must be in NVM access mode. The following sequence should be used. 1. Check that the ASL1507SHN; ASL2507SHN is in configuration mode (register 56h shows binary 0010 0XXXb) and limp-home mode is not active (register 54h shows binary XXXX X0XXb). 2. Enter NVM access mode by setting register 3Ah to 04h. 3. Confirm that the ASL1507SHN; ASL2507SHN is in NVM access mode (register 56h shows binary 1101 1XXXb). 4. Write target NVM address to NVM address register (register 36h is target register). 5. Write target NVM_DATA[15:8] into data register 37h. 6. Write target NVM_DATA[7:0] into data register 38h. 7. Ensure that the ECC is calculated internally (register 39h = 00h). 8. Ensure that the NVM is ready (register 55h shows binary XXXX XXX1b). 9. Initiate NVM write:
- Write register 3Ah with XXXX 0100b.
- Write register 3Ah with XXXX 0110b. 10.Wait until NVM access is completed (register 55h shows binary XXXX XXX1b). 11.If further NVM access is required, start at step four of the read or write sequence. 12.Exit NVM access mode by setting register 3Ah to 08h. 13.NVM access complete; for reset set pin EN = LOW. Note: The IC is only considering the NVM content programmed as valid when bit 1 and bit 0 in the NVM register 00h indicate 10b. The IC is allowing 200 write cycles to the NVM. The number for write counts can be stored in the NVM write counter in NVM address 01h. This counter should be increased after each update.
Figure 10. Sequence to write into NVM registers
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
8.13.2 NVM read sequence
To read an NVM register, the device must be in NVM access mode. The following sequence should be used. 1. Check that the ASL1507SHN; ASL2507SHN is in configuration mode (register 56h shows binary 0010 0XXXb) and limp-home mode is not active (register 54h shows binary XXXX X0XXb). 2. Enter NVM access mode by setting register 3Ah to 04h. 3. Confirm that the ASL1507SHN; ASL2507SHN is in NVM access mode (register 56h shows binary 1101 1XXXb). 4. Write target NVM address to NVM address register (register 36h is target register). 5. Ensure that the NVM is ready (register 55h shows binary XXXX XXX1b). 6. Initiate NVM read:
- Write register 3Ah with XXXX 0100b.
- Write register 3Ah with XXXX 0101b. 7. Wait until NVM access is completed (register 55h shows binary XXXX XXX1b). 8. Data from the NVM is now available in NVM data read register 59h for NVM_DATA[15:8] and register 5Ah for NVM_DATA[7:0]. 9. If further NVM access is required, start at step four of the read or write sequence. 10.Exit NVM access mode by setting register 3Ah to 08h. 11.NVM access complete; for reset set pin EN = LOW.
Figure 11. Sequence to read from NVM registers
8.13.3 NVM register map
The ASL1507SHN; ASL2507SHN allows limp-home values during NVM access. Table 47 shows the linking of the NVM addresses to the register addresses. Table 47. Mapping of NVM registers to control registers The NVM data fields that contain more than just one register are shown in Table 48. Table 48. Overview of multi-content NVM data field
8.14 Autonomous mode
detection of SPI communication timeout. Figure 12. Autonomous mode operation Table 49. Comparison of limp-home mode and autonomous mode
8.14.1 Limp-home mode/autonomous mode NVM
Table 50. NVM programming options
8.15 SPI
writing the control register.
8.15.1 SPI introduction
- CSB - SPI chip select: active LOW
- SCLK - SPI clock: default level is LOW due to low-power concept
- SDI - SPI data input
- SDO - SPI data output: floating when pin CSB is HIGH Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge as illustrated in Figure 13. B15 MSB B14 B13 B12 B11 B10 B9 B3 B2 B1 B0 B11 B10 B9 B3 B2 B1 B0 aaa-016623 SCLK CSB SDI B15 MSB B14 B13 B12 SDO driving edge sampling edge
Figure 13. SPI timing protocol must be sent to the LED driver. The first byte is an identifier byte that consists of the 7-bit address and one read-only bit. written into the register. So an SPI access consists of at least 16 bit. Figure 14 together with Table 51 and Table 52 demonstrates the SPI frame format.
Figure 14. SPI frame format Table 51. SPI frame format for a transition to the device Table 52. SPI frame format for a transition from the device[1] [1] The first SPI command after leaving the off mode returns 00h. LOW and lasts until it is asserted HIGH. The ASL1507SHN; ASL2507SHN also tolerates SPI accesses with a multiple of 16 bits. It allows a daisy chain configuration of the SPI.
8.15.2 Typical use case illustration (write/read)
fashion. The following commands are performed during one sequence (first sequence).
- Write data FFh to register 1Ah of slave 1
- Read from register 2h of slave 2
- Write data AFh to register 2Fh of slave 3
- Read from register 44h of slave 4 aaa-016627 b15-b8 = Default read reg of slave4 b7-b0 = Data from 0x44 of Slave4 b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave4 Response from previous sequence b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 Slave 4 b15 = 1 b14-b8 = 0x44 b7-b0 = xx Slave 3 b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF Slave 2 b15 = 1 b14-b8 = 0x2 b7-b0 = xx Slave 1 b15 = 0 b14-b8 = 0x1A b7-b0 = 0xFF b15-b8 = Default read reg of slave1 b7-b0 = xx b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave1 b7-b0 = xx b15-b8 = Default read reg of slave1 b7-b0 = xx b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 1 b14-b8 = 0x2 b7-b0 = xx Next command for Slave4 Next command for Slave3 Next command for Slave2 Next command for Slave4 Next command for Slave3 Next command for Slave2 Next command for Slave1 Next command for Slave3 Next command for Slave4 Next command for Slave4 b15-b8 = Default read reg of slave1 b7-b0 = xx XXX Master SDO/ Slave1 SDI SCLK CSB 1st Sequence 1 x 16 SCLK's 2 x 16 SCLK's 3 x 16 SCLK's 4 x 16 SCLK's 1 x 16 SCLK's 2 x 16 SCLK's 3 x 16 SCLK's 4 x 16 SCLK's 2nd Sequence Slave1 SDO/ Slave2 SDI Slave2 SDO/ Slave3 SDI Slave3 SDO/ Slave4 SDI Slave4 SDO/ Master SDI XXX XXX XXX XXX XXX XXX XXX XXX XXX Current sequence Command decoded by Slave
Figure 17. SPI frame format
8.15.3 Diagnostics for the SPI interface
- SPI write is attempted to a read-only location or reserved location
- SPI write is attempted during operation to a configuration register
- SPI read is attempted from a reserved location
- SPI command does not consist of a multiple of 16 clock counts If an SPI access is considered to be erratic, no modifications to an SPI register are made. The access after the erratic SPI command returns for bit 15 to bit 8 the content of the diagnostic register, and for bit 7 to bit 0 as 00h. For details about the SPI_ERR bit, see Section 8.10.3.
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
8.15.4 Register map
8.15.4.1 Control registers
Table 53 provides an overview of the control registers and their reset value.
Table 53. Control register group overview [1] Bit is locked with bit CFG_DN = 1. When bit CFG_DN = 0, bits can be changed. Read is always possible. the CFG_DN and VGG_OK are set to logic 1, are off, even when the bits are set to logic 1 later.
8.15.4.2 Configuration registers
this register can only be read. Table 54. Configuration register group overview
8.15.4.3 Internal registers
registers but leave them all at their default value. Table 55. Internal register overview
8.15.4.4 Diagnostic registers
Table 56. Diagnostic register group overview
9 Limiting values
Table 57. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 kΩ). [2] Charged Device Model (CDM): according to AEC-Q100-011 (field induced charge; 4 pF).
10 Thermal characteristics
Table 58. Thermal characteristics and thermal via array under the exposed pad connected to the first inner copper layer.
11 Static characteristics
Table 59. Static characteristics IC. Typical values are given at VVBAT = 40 V, VEN = 5 V, VVCC = 5 V and Tj = 25 °C; unless otherwise specified.
12 Dynamic characteristics
Table 60. Dynamic characteristics IC. Typical values are given at VVBAT = 40 V, VEN = 5 V, VVCC = 5 V and Tj = 25 °C; unless otherwise specified.
Figure 18. SPI timing diagram
boost converter IC with one output voltage. Figure 19. ASL2507SHN, configured as two-phase, single output boost converter
14 Test information
14.1 Quality information
circuits, and is suitable for use in automotive applications.
- Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Figure 20. Package outline SOT617-12 (HVQFN32)
Table 61. Revision history
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
17 Legal information
17.1 Data sheet status
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018 applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018 Tables Tab. 13. Phase-off time and phase delay of output 1 Tab. 14. Phase-off time and phase delay of output 2 Tab. 15. Loop filter proportional configuration Tab. 16. Loop filter integral configuration (address Tab. 17. Slope compensation configuration (address Tab. 18. Current sense slope resistor configuration Tab. 26. Spread spectrum enable register (address Tab. 31. Maximum coil current VO1 register (address Tab. 32. Maximum coil current VO2 register (address Tab. 34. VGG control register (address 15h); bit 4 in Tab. 35. VGG control register (address 15h); bit 4 in Tab. 37. Undervoltage threshold register (address Tab. 38. Overvoltage threshold register (address Tab. 43. Limp-home mode control register (address Tab. 47. Mapping of NVM registers to control Tab. 49. Comparison of limp-home mode and Tab. 51. SPI frame format for a transition to the Tab. 52. SPI frame format for a transition from the deviceThe first SPI command after leaving Figures Fig. 6. Phase of the boost converter with IC and Fig. 7. Mapping of virtual phases (V1_1 to V2_4) to Fig. 19. ASL2507SHN, configured as two-phase,
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Product data sheet Rev. 1 — 26 April 2018
NXP Semiconductors ASL1507SHN; ASL2507SHN Single-phase and two-phase boost converter with limp-home mode Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 April 2018 Document identifier: ASL1507_ASL2507