ASG509A

ADG508A AD | Alldatasheet

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Co DEVICES 4/8 Channel Analog Multiplexers FEATURES FUNCTIONAL BLOCK DIAGRAMS 44V Supply Maximum Rating Vs to Voo Analog Signal Range Single/Dual Supply Specifications ADG508A ADGS509A Wide Supply Ranges (10.8V to 16.5V) siQ—oTo Od siAO—oTo © DA Extended Plastic Temperature Range i Mm (40°C to +85°C) nf sao Low Power Dissipation (28mW max) iy 1} Low Leakage (20pA typ) ey sBwO——%° 7 oe Available in 16-Lead DIP/SOIC and | Wott 20-Lead PLCC/LCCC Packages sv 7° sO 79 Superior Airernative to: DG508A, HI-508 DG5O9A, HI-509 53-44 664 AO Al A2 EN AO Al EN GENERAL DESCRIPTION ORDERING GUIDE The ADGSO8A and ADGSO9A are CMOS monolithic analog multiplexers with 8 channels and dual 4 channels respectively. ‘Temperature | Package The ADGSOBA switches one of 8 inputs to a common output Model’ Range Option? depending on the state of three binary addresses and an enable input. The ADGSO9A switches one of 4 differential inputs to a ADGSOBAKN | —40°Ct0 + 85°C | N-16 common differential output depending on the state of two binary ADGSO8AKR | —40°Cto + 85°C | R-16A addresses and an enable input. Both devices have TTL and SV ADGS08AKP | ~40°Cto +85°C | P-20A CMOS logic compatible digital inputs. ADGSO8ABQ_ | — 40°C to + 85°C | Q-I16 - ADGS08ATQ: | -55°Cto +125°C | Q-16 ‘The ADGSO8A and ADGSO9A are designed on an enhanced ADGSO8ATE | —55°Cto +125°C| E.20A LC2MOS process which gives an increased signal capability of Vss to Vip and enables operation over a wide range of supply ADGS09AKN | —40°Cto +85°C | N-16 voltages. The devices can comfortably operate anywhere in the ADGSO9AKR | —40°Cto +85°C_ | R-16A 10.8V to 16.5V single or dual supply range. These multiplexers ADGSO9AKP | —40°Cto +85°C | P-20A also feature high switching speeds and low Ron. ADGSO9ABQ: | —40°Cto +85°C | Q16 ADGSO9ATQ | —55°Cto + 125°C | Q-16 PRODUCT HIGHLIGHTS ADGSO9ATE | ~55°Cto + 125°C | E-20A 1. Single/Dual Supply Specifications with a Wide Tolerance: The devices are specified in the 10.8V to 16.5V range for NOTES | MIL-STD.803, Clase B procemed parts, add both single and dual supplies. /883B to part number. See Analog Devices Military 2. Extended Signal Range: Products Databook (1990) for military data sheet. ‘The enhanced LC2MOS processing results in a high breakdown Plastic DIPS? © Phuc Loaded Chie Goer (PLCC); and an increased analog signal range of Vss to Vpp- Q = Cerdip; R = 0.15° Small Outline IC (SOIC). 3. Break-Before-Make Switching: Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 4. Low Leakage: Leakage currents in the range of 20pA make these multiplexers suitable for high precision circuits. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

K Version BVersion T Version =40°Cto =40°Cto -55°Cto Parameter #25°C 485°C | 25°C 85°C | 425°C +125°C_| Units | Comments ANALOG SWITCH ‘Analog Signal Range Vss_ Vs. Vss_ Vs Vss_ Vs Vmin Vpp = Vop Yoo — Vpp Yoo = Vpp Vmax Ron 280 280 280 Qyp ~10V=Vs= + 10V, Ips= ImA; Test Circuit 1 450 600 450 600 450 600 OQmax 300 400 300 400 Amax | Vop=1SV( + 10%), Vss= — 19V(+ 10%) 300-400 Qmax | Vpp=15V(+5%), Vss = — 1SV( 5%) Ron Drift 0.6 0.6 0.6 %/°Ctyp | Vs=0,Ips=ImA Ron Match 5 5 5 %typ = 10V<Ve< + 10V, Ips= 1mA. Is (OFF), Off Input Leakage 0.02 0.02 0.02 sAtyp | Vi=*10V,V2=+10V;TestCircuit2 1 50 1 50 1 50 nA max Ip (OFF), Off Output Leakage | 0.04 0.04 0.04 aAtyp | VI= +10V,V2=710V;TestCircuit 3 ADGSO8A. 1 100 1 100 1 100 nA max ADGS09A 1 30 1 50 1 50 nA max Ip(ON), OnChannel Leakage | 0.04 0.04 0.04 nAtyp | V1=V2= + 10V;TestCircuit4 ADGS08A 1 100 1 100 1 100 nA max ADGSO9A 1 50 1 50 1 50 nA max Ipier, Differential Off Output Leakage (ADGSO9A only) 25 25 25 nAmax_| V1= +10V,V2=+10V; TestCircuitS DIGITAL CONTROL. Vina Input High Voltage 24 24 24 Vmin Vint» Input Low Voltage 0.8 08 0.8 Vmax Teor inn 1 1 1 wAmax | Vin=0toVpp Ci Digital InputCapacitance _| 8 8 8 pF max DYNAMIC CHARACTERISTICS trransrrton! 200 200 200 astyp | VI= +10V,V2=¥10V; Test Circuit 300 400 300 400 300-400 nsmax toven? 50 50 50 nstyp | TestCircuit7 25 10 25 10 25 10 ns min ton (EN)! 200 200 200 nstyp Test Circuit 8 300-400 300-400 300-400 ‘ns max torr (EN)! 200 200 200 nstyp | Test Circuit 8 300-400 300-400 300-400 ns max OFF Isolation 68 68 68 dBiyp | Ven=0.8V,Ry=1k0, C= 15pF, 50 50 50 dBmin | Vs=7Vrms, f= 100kHz Cs(OFF) 5 5 5 pFiyp | Ven=0.8V Cp (OFF) ADGSO8A 2 2 2 pFiyp | Ven=0.8V ADGS09A in n u pFiyp Quy, Charge Injection 4 4 4 pCtyp | _Rs=00, Vs=0; Test Circuit9 POWER SUPPLY Ipp 06 0.6 0.6 mAtyp) | Vin=VineorVinn 1s 1s LS mA max Iss 20 20 20 wAyp | Vix~VixiorVisn 0.2 0.2 0.2 mA max Power Dissipation 10 10 10 mW typ 28 28 28 mW max NOTE "Sample tested at 25°C to ensure compliance. ‘Specifications subject to change without notice. -2- REV. B

SINGLE SUPPLY w,, = +t0.8v to +16.5v, Vc, = GND = OV unless otherwise noted.) ADGS08A ADGS08A. ‘ADGSO8A ADGS509A. ADGS09A ADGS09A K Version BVersion T Version -40°C to =40°Cto =55°Cto . Parameter +25°C +85°C | +25°C +85°C | +25°C +125°C | Units | Comments ANALOG SWITCH Analog Signal Range GND GND |GND GND |GND GND | Vmin Yop Vpp Yoo Vop Yoo Yop Vmax Row 500 500 500 Qtyp | GND=Vs=+ 10V, Ips=0.5mA Test; Circuit 1 700 1000 700 1000 700 1000 OQmax Roy Drift 0.6 0.6 0.6 %Ctyp | Vs=0,Ips=0.5mA Row Match 5 5 5 %eyp | GNDSVs=+10V, Ips=0.5mA 1s(OFF), Off Input Leakage | 0.02 0.02 0.02 nAtyp | V1=+10V/GND,V2=GND/+10v, 1 50 1 50 1 50 nA max ‘Test Circuit 2 Ip(OFF), Off Output Leakage | 0.04 0.04 0.04 nAtyp | Vi=+10W/GND,V2=GND/+ 10V; ADGSO8A 1 100 1 100 1 100 nA max Test Circuit 3 ADGSO9A 1 50 1 50 1 30 nA max Ip(ON), On Channel Leakage | 0.04 0.04 0.04 nAtyp | V1=V2= +10V/GND; ADGS08A 1 100 1 100 1 100 nA max TestCircuit4 ADGS09A 1 50 1 50 1 50 nA max Ipirrs Differential Off Output V1 = +10V/GND, V2=GND/+ 10V; Leakage (ADGS09A only) 25 2s 25 nAmax | TestCircuitS DIGITAL CONTROL. Vines Input High Voltage 24 24 24 Vmin Vint» Input Low Voltage 0.8 0.8 08 Vmax Tnvt.oF tiv, 1 1 1 pAmax | Vix=0t0Vpp Cin Digital Input Capacitance | 8 8 8 pF max DYNAMICCHARACTERISTICS trransirion! 300 300 300 nstyp | V1= +10V/GND, V2=GND/+ 10V; TestCicuit 6 450 600 450, 600 450 600 ns max topen! 50 50 50 nstyp Test Circuit 7 25 10 25 10 25 10 ns min ton (EN)! 250 250 250 nstyp | Test Circuits 450 600 450 600 450 600 nsmax torr (EN)! 250 250 250 ns typ Test Circuit 8 450600 450600 450 600 nsmax OFF Isolation 68 68 68 aBtyp | Ven=0.8V,R.=1k0,C. = 15pF, 50 50 50 dBmin | Vs=3.5Vrms,{=100kHz Cs(OFF) 5 5 5 pFiyp | Vex=0.8V Cp (OFF) ADGSO8A 2 2 2 pFiyp | Viw=0.8V ADGSO9A in u n pF yp Quy Charge Injection 4 4 4 pCryp_| Rs=00, Vs=0V; TestCircuit9 POWER SUPPLY Ip 0.6 0.6 mAtyp | Vin=Vintor Vint LS Ls mA max Power Dissipation 10 10 mW yp 25 25 mW max 'Sample tested at 25°C to ensure compliance. Cw Digital input capacitance Specifications subject to change without notice. torr (EN) Delay time between the 50% and 10% points of the digital input and switch “OFF” condition TERMINOLOGY trranstrion Delay time between the 50% and 90% points of Ron Ohmic resistance between terminals D and $ the digital inputs and switch “ON” condition Ron Match __ Difference between the Ron of any two channels when switching from one address state to Ron Drift Change in Ron versus temperature another Is (OFF) Source terminal leakage current when the switch topEn “OFF” time measured between 50% points of is off both switches when switching from one address Ip (OFF) Drain terminal leakage current when the switch state to another is off Vin. Maximum input voltage for Logic “0” Ip (ON) Leakage current that flows from the closed switch = Vinu Minimum input voltage for Logic “1” into the body Tint. (ine) Input current of the digital input Vs (Vp) Analog voltage on terminal S$ or D Vpp Most positive voltage supply Cs (OFF) Channel input capacitance for “OFF” condition Vss Most negative voltage supply Cp (OFF) Channel output capacitance for “OFF” Ipp Positive supply current condition Iss Negative supply current REV. B 3

ABSOLUTE MAXIMUM RATINGS* TRUTH TABLES (Tq = 25°C unless otherwise noted) (aaa en onsen VpptoVss oe eee eee eee ee 4V x lx lx ° NONE VsstOGND 20. ee ee ee = 25V 1 0 0 1 1 2 Analog Inputs : : ; Vpp +2Vor ° 1 1 1 4 20mA, Whichever Occurs First 1 ° ° l 5 Pulsed Current S or D 1 1 0 1 7 Digital Inputs! . Vpp +4Vor ADG508A 20mA, Whichever Occurs First Power Dissipation (Any Package) swrcn Upto +75... ee eee 470mW A en | PAIR Operating Temperature x NONE NOTE = ¥ 'Overvoltageat A, EN, S or D will be clamped by diodes. Current should be X=Don'tCare limited to the Maximum Rating above. ADG509A *COMMENT;; Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected; WARNING! however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam print 4 should be discharged to the destination socket before devices are removed. ESD SENSITIVE DEVICE PIN CONFIGURATIONS DIP, SOIC Lccc PLCC Bega Eveloeo aE] Ls] “ Vea ty te onp ves [a] fia] no cae [4] evo ss 17 eo fos Ol er SC] avesoea [2] von ne 6 ADG5OBA 18 No ne (5 Tor view big} ne sz] kORMew., [2] 85 se (Wot t0 Seale) 1838 2 Dl (Nor to Seale) fis] s» «G] [re] s7 SS ofa [a] se Tera Pes 3° 2 BB Nne- Noconnecr 3 © 8 BG nc~noconnecr > g2e28 B2is PIRI Earl a Ole [re] a. foe ev [is] eno Ves tf 18 oo vss Ei] Ii) veo ves BY [ia] veo sas v7 sia su sie ADGS09A

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sea To] gfORMEW [ia] see s7a 7 ‘iNet to Scaled 15 S28 S2A [15] s2e so [e] fa] sas SIA 8 14 S38 saa [2] [ra] sae se G] pe) se 9 10 11 12 13 Mey LG] [2] gsegag 1 ss82 _ ° 3 Ne = NOCONNES $8 2 8 F ne -noconnecr -4- REV. B

Typical Performance Characteristics— ADGS508A/ADG509A The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5V. aft ETT Te Ty att ty Ty yy ELT on 500 f\\ 500 Vso = 0 PT | MAT Pt tT ATT = 400 t ~ 400 Foal lvoe? | NL TP aL Sm B/AR at LAN PAL | I wf tt EN Pssce[ ST T | Pt tT PT tT Tt vo LY | | 100 Ltt Tt ttt | LETT? | tt “2-0-5 a VolVs)- Volts VolVs) - Volts: Ron as a Function of Vp(Vs): Dual Supply Voltage, Ron as a Function of Vp(Vs): Single Supply Voltage, Ta = +25°C Ta = +25°C 100 18 Voo = +188v © p10 <4 18 F Io (OFF) a s 3 4 [N 3 o 5 p g A F PM a se 7 8 8 wn w ww 1 TEMPERATURE _-< SUPPLY VOLTAGE” Volts —~"" Leakage Current as a Function of Temperature Trigger Levels vs. Power Supply Voltage, Dual or Single (Note: Leakage Currents Reduce as the Supply Voltages Supply, Ta = +25°C Reduce) LT 100 KN | ft " soo soo < Nel 3 Eo ss Fas “Rat =P a | SY " ses 7 8 8 wo ww ws s 67 8 8 wn wm 4 ws ww SUPPLY VOLTAGE Volts SUPPLY VOLTAGE-Votts trransition VS. Supply Voltage: Dual and Single Supplies, Ippo vs. Supply Voltage: Dual or Single Supply, Ta = +25°C Ta = +25°C (Note: For Vpp and |Vss/ < 10V; V1 = Vpp/Vss, V2 = Vss/Vpp. See Test Circuit 6) REV. B 5.

ADGS508A/ADG509A — Test Circuits Note: All Digital Input Signal Rise and Fall Times Measured from 10% to 90% of 3V. tg = tr = 20ns. TEST CIRCUIT 1 TEST CIRCUIT 2 TEST CIRCUIT 3 Ron Is (OFF) Ip (OFF) los Voo — Vss CD Voo ss Voo Vss cr > 1s (OFF) () a ! ° ° en () Io (OFF) ° ° |, +08V00 yy GND EN Vs ° u= v= GND b V7 =v TEST CIRCUITS TEST CIRCUIT 4 lore Ip(ON) Voo Vs Yoo = Vss Voo — Vss 5 -ENT—osv ITF = poo | te © a [ | apcsosa u v2 = Ipiony 26ND v2 vO 5” v Vv Ine = loa (OFF) ~ lpg (OFF) TEST CIRCUIT6 SWITCHING TIME OF MULTIPLEXER, trransrrion Voo Ves 3v—_| | ADDRESS foo X_brive (Ww) ov—+ h Voo Ves \\ \\ a2 si vi ! 1 [ | re T | 7 o0% Vin ms | ‘1 $2 THRU S7 yy ! Bs Ao I ‘7 output ss ve | ADG508A* 1 \\. 90% I V 2av rN p joureur ake Ake GND 1MQ_ == 35pF trnansmow ——_trnansmion ee *SIMILAR CONNECTION FOR ADGS09A V ~ V TEST CIRCUIT7 BREAK-BEFORE-MAKE DELAY, topen Voo Vas Voo Vss av ADDRESS s1 +5V DRIVE (Vw) al a2 ov Vw @) om a At $2 THRU S7 % \\ f “ ADGSOBA* F50% — ourpuT V aav —| en » Loumur > GND 1k 35pF toren V *SIMILAR CONNECTION FOR ADGSO9A V ~6- REV. B

ENABLE DELAY, ton (EN), torr (EN) Voo — Vss. wy ENABLE ov JI 50% ! a 2 s1 +5V ' i V Al s2 THRU SB it a ADG5O8A" | output 4 a = toe! EN D len | Vw @Q § 500 GND 1K 35pF *SIMILAR CONNECTION FOR ADGSOSA V V V TEST CIRCUIT 9 CHARGE INJECTION Voo Vs wv Voo Vss Vw no ov 4 ¥ Ha Vo Wo p= == 4 a2 ADGSO8A* 1 so y,

1 Vs T °

E-- oy | Quy = CL x AVo to | 500 V *SIMILAR CONNECTION FOR ADGSO9A b SINGLE SUPPLY OCTAL DAC APPLICATION voltage reference on a monolithic CMOS chip. The entire system The following circuit shows the ADGSO8A connected as a de- operates from a single + 15V power supply. The ADGSO8A is multiplexer to provide eight separate digitally programmable ideally suited for the application because it has both low charge voltages (0 to + 10V) from the AD7245. The AD7245 isacomplete _ injection and Is (OFF) leakage current. 12-bit, voltage output DAC with output amplifier and Zener +15V +15V DB11 Ree C1 st x Voury Cc) Deo Vour D v4 TLC274 0.01nF Vv AD7245, ws ADGS508A a Rors REF OUT v se va TLe274 AO AT AZ | 0.01pF Vv toe t O1nF i T 10nF ADG508A in a Single-Supply Octal DAC Circuit REV. B -7-

Dimensions shown in inches and (mm). 16-Pin Plastic (N-16) 16-Pin Cerdip (Q-16) — yi 8 0.24 (61) "24 169) i —t me q 2785 090) + 206117) oat aay opeue 3 on a2) Seay 015513957) mn Sct 0 t ‘276 48) . aa I So00to200) tas a a4 RT ° wien Gaaae LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 i a 16-Lead Narrow Body SOIC (R-16A) 20-Terminal Leadiess Ceramic Chip Carrier (E-20A) I * ames san oe Sean 9.04045" KR} UU, TOUEONOL = + oss, 0.3859 (9.80) hes 4 ro — £ = = F o.0688 (1.75) — oC .0098,025) 005221135) 0.0089(025) 9, Lito. ECan nn dy ononvew oninotan ooreatas) Satan sasoouran ,| [7 ed as, ee pore eas he 20-Terminal Plastic Leaded Chip Carrier (P-20A) + f soieezn ‘ poner augh SOROS F TIT C+ wenmmen =] | pean ‘on é os) Es a g q 1356 00 | FF osoean = > q ro? view 0.305 (9.78) 0.013033) 9590(638) [}>—D_ BOTTOM VIEW 5 : =e 7 a= E: le 4) 0032 (087) A RARA 4 2 oe! \\ i iit & — _ [5.510 (2.78) -8- REV. B