ASDP-21060CW-133

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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and reliable. infringements of patents or other rights of th ird parties that may result from its use. registered trademarks are the property of their respective owners. .3113 ©2008 Analog Devices, Inc. All rights reserved.

40 MIPS, 25 ns instruction rate, single-cycle instruction

120 MFLOPS peak, 80 MFLOPS sustained performance

Figure 1. Functional Block Diagram

parison across family members, see Table 1.

10 DMA channels for transfers between ADSP-2106x internal

240 MBps transfer rate over parallel bus

240 MBps transfer rate over link ports

Table 1. ADSP-2106x SHARC Processor Family Features

33 MHz

40 MHz

erals supported by a dedicated I/O bus. mance benchmarks for the ADSP-2106x. 32-bit DSP core with integrated, on-chip system features.

• Computation units (ALU, multiplier and shifter) with a shared data register file
• Data address gen erators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro- cessor cycle
• Interval timer
• O n - c h i p S R A M
• External port for interfacing to off-chip memory and peripherals
• Host port and multiprocessor Interface
• DMA controller
• Serial ports and link ports
• JTAG Test Access Port SHARC FAMILY CORE ARCHITECTURE The ADSP-2106x includes the following architectural features of the ADSP-21000 family core. The ADSP-2106x processors are code- and function-compatible with the ADSP-21020. Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter all per- form single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multi- function instructions execute parallel ALU and multiplier oper- ations. These computation units support IEEE 32-bit single- precision floating-point, extended precision 40-bit floating- point, and 32-bit fixed-point data formats. Data Register File A general–purpose data register file is used for transferring data between the computation units and the data buses, and for stor- ing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP-21000 Harvard architecture, allows unconstrained data flow between computation units and internal memory.

Table 2. Benchmarks (at 40 MHz)

1024 Point Complex FFT (Radix 4, with

Figure 2. ADSP-2106x System Sample Configuration

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 5 of 64 | March 2008 Single-Cycle Fetch of Instruction and Two Operands The ADSP-2106x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-2106x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing. Data Address Generators with Hardware Circular Buffers The ADSP-2106x’s two data address generators (DAGs) imple- ment circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-2106x contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. Circular buffers can start and end at any mem- ory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-2106x can conditionally execute a multiply, an add, a subtract and a branch, all in a single instruction. MEMORY AND I/O INTERFACE FEATURES The ADSP-2106x processors add the following architectural features to the SHARC family core. Dual-Ported On-Chip Memory The ADSP-21062/ADSP-21062L contains two megabits of on- chip SRAM, and the ADSP-21060/ADSP-21060L contains 4M bits of on-chip SRAM. The internal memory is organized as two equal sized blocks of 1M bit each for the ADSP-21062/ ADSP-21062L and two equal sized blocks of 2M bits each for the ADSP-21060/ADSP-21060L. Each can be configured for dif- ferent combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle. On the ADSP-21062/ADSP-21062L, the memory can be config- ured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 40k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, or 48-bit words. On the ADSP-21060/ADSP-21060L, the memory can be config- ured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 80k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. All of the memory can be accessed as 16-bit, 32-bit or 48-bit words. A 16-bit floating-point storage format is supported, which effec- tively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit float- ing-point formats is done in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the ADSP-2106x’s external port. On-Chip Memory and Peripherals Interface The ADSP-2106x’s external port provides the processor’s inter- face to off-chip memory and peripherals. The 4-gigaword off- chip address space is included in the ADSP-2106x’s unified address space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for sim- plified addressing of page-mode DRAM. The ADSP-2106x provides programmable memory wait states and external mem- ory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements. Host Processor Interface The ADSP-2106x’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with lit- tle additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-2106x’s exter- nal port and is memory-mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-2106x’s external bus with the host bus request (HBR ), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the inter- nal memory of the ADSP-2106x, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands.

Figure 3. Shared Memory Multiprocessing System

taneously executing its program instructions. 32-, or 48-bit words is performed during DMA transfers. chaining for automatic linked DMA transfers. Figure 4. Memory Map

Rev. F | Page 8 of 64 | March 2008 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports The ADSP-2106x features six 4-bit link ports that provide addi- tional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. Link- port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously, with a maximum data throughput of 240M bytes/s. Link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. Program Booting The internal memory of the ADSP-2106x can be booted at sys- tem power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is controlled by the BMS (boot memory select), EBOOT (EPROM Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host processors can be used for booting. The processor also sup- ports a no-boot mode in which instruction execution is sourced from the external memory. DEVELOPMENT TOOLS The ADSP-2106x is supported by a complete set of CROSSCORE ®† software development tools, including Analog Devices emulators and VisualDSP++®‡ development environ- ment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2106x. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The ADSP-2106x SHARC DSP has architectural features that improve the effi- ciency of compiled C/C++ code. The VisualDSP++ debugger has a number of important fea- tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com- plexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Sta- tistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and effi- ciently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assemb ly code (interleaved source and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory, and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the ADSP-2106x development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits:
• Control in how the developmen t tools process inputs and generate outputs
• Maintenance of a one-to-one correspondence with the tools’ command line switches The VisualDSP++ kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem- ory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre- emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the gen- eration of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine run-time stack and heap usage. The † CROSSCORE is a registered trademark of Analog Devices, Inc. ‡ VisualDSP++ is a registered trademark of Analog Devices, Inc.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 9 of 64 | March 2008 expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphi- cal and textual environments. In addition to the software development tools available from Analog Devices, third parties provide a wide range of tools sup- porting the SHARC processor family. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. EVALUATION KIT Analog Devices offers a range of EZ-KIT Lite®† evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board proces- sor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standal- one unit, without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus- tom-defined system. Connecting an Analog Devices JTAG emulator to the EZ-KIT Lite board enables high speed, nonin- trusive emulation. DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter- face—the emulator does not affect target system loading or tim- ing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2106x architecture and functionality. For detailed information on the ADSP-21000 family core architecture and instruction set, refer to the ADSP-2106x SHARC User’s Manual, Revision 2.1. † EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

respect to CLKIN (or with respect to TCK for TMS, TDI). Table 3. Pin Descriptions processing bus master is reading or writing its internal memory or IOP registers. resistors on unused DATA pins are not necessary. MS3–0 lines are decoded memory address lines that change at the same time as the other address lines. lines are output by the bus master. bus master and is input by all other ADSP-2106xs. has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT). ADRCLK O/T Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master.

ACK pin that maintains the input at the level to which it was last driven. or used with a DRAM controller. IRQ2–0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive. a condition. As an output, they can be used to signal external peripherals. TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero. HBG is output by the ADSP-2106x bus master and is monitored by all others. CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x. and HBR inputs are asserted. DMAR2–1 I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8). DMAG2–1 O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8). high; the processor’s own BRx line must not be pulled high or low because it is an output. ID2–0 O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP-2106x. lines are a system configuration selection that should be hardwired or changed at reset only. system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x. not required in a system, the CPA pin should be left unconnected. DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k/g58 internal pull-up resistor. DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k/g58 internal pull-up resistor. TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k/g58 internal pull-up resistor. RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k/g58 internal pull-up resistor. Table 3. Pin Descript ions (Continued)

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1). RFSx I/O Receive Frame Sync (Serial Ports 0, 1). disabled by the LPDRD bit of the LCOM register. disabled by the LPDRD bit of the LCOM register. enabled or disabled by the LPDRD bit of the LCOM register. EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM. description below. This signal is a system configuration selection that should be hardwired. description below. This signal is a system configuration selection that should be hardwired. BMS I/OT Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0). mode (when BMS is an output). 0 0 0 (Input) No Booting. Processor executes from external memory. not be halted, changed, or operated below the minimum specified frequency. TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k/g58 internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. low for proper operation of the ADSP-2106x. TRST has a 20 k/g58 internal pull-up resistor. EMU O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only. ICSA O Reserved, leave unconnected. GND G Power Supply Return. (30 pins). NC Do Not Connect. Reserved pins which must be left open and unconnected.

and other JTAG devices on the chain. port can also be used for board-level testing. Figure 5. If you are not going to use the test access port for 9, and 11) are connected on the EZ-ICE probe. contain multiple ADSP-2106x processors. Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. sors, simply tie Pin 4 of the EZ-ICE header to ground. critical signals in terms of skew. ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference. Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator Table 4. Core Instruction Rate/CLKIN Ratio Selection

1 TRST is driven low until the EZ-ICE probe is turned on by the emulator at software

start-up. After software start-up, is driven high.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 15 of 64 | March 2008 ADSP-21060/ADSP-21062 SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (5 V) ELECTRICAL CHARACTERISTICS (5 V) A Grade C Grade K Grade Parameter Description Min Max Min Max Min Max Unit TCASE Case Operating Temperature –40 +85 –40 +100 –40 +85 /g113C VIH11 1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS , TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1. VIH22 2 Applies to input pins: CLKIN, RESET, TRST. Parameter Description Test Conditions Min Max Unit VOH 1, 2 High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 4.1 V VOL 1, 2 Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V IIH 3, 4 High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA IIL

3 Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA

4 Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA

5, 6, 7, 8 Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA IOZL 5, 9 Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA IOZHP

9 Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA

7 Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA IOZLA 10 Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA IOZLAR 8 Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA IOZLS

6 Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA

11, 12 Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 4.7 pF 1 Applies to output and bidirectional pins: DATA47–0, ADDR31-0, MS3–0 , RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS , TDO, EMU, ICSA. 2 See “Output Drive Currents” for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET , TCK. 4 Applies to input pins with internal pull-ups: DR0, DR1, TRST , TMS, TDI. 5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx, TDO, EMU. (Note that ACK is pulled up internally with 2 k /g58 during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.) 6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k/g58 during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. 10Applies to ACK pin when keeper latch enabled. 11Applies to all signal pins. 12Guaranteed but not tested.

Rev. F | Page 16 of 64 | March 2008 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (5 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissi- pation Measurements.” Specifications are based on the operating scenarios. To estimate power consumption for a specific application, use the following equation where % is the amount of time your pro- gram spends in that state: %PEAK I DDINPEAK +%HIGH IDDINHIGH +%LOW IDDINLOW + %IDLE IDDIDLE = Power Consumption Operation Peak Activity (IDDINPEAK) High Activity (I DDINHIGH) Low Activity (I DDINLOW) Instruction Type Multifunction Multifunction Single Function Instruction Fetch Cache Internal Memory Internal Memory Core memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles Parameter Test Conditions Max Units IDDINPEAK Supply Current (Internal)1 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 745 850 mA mA I DDINHIGH Supply Current (Internal)2 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 575 670 mA mA I DDINLOW Supply Current (Internal)2 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 340 390 mA mA I DDIDLE Supply Current (Idle)3 VDD = Max 200 mA 1 The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. 2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code. 3 Idle denotes ADSP-2106x state during execution of IDLE instruction.

tion execution sequence and the data operands involved.

• the number of output pins that switch during each cycle (O)
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
• their voltage swing (V DD) and is calculated by: PEXT = O /g117 C /g117 VDD 2 /g117 f The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t CK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Example: Estimate PEXT with the following assumptions:
• A system with one bank of external data memory RAM (32-bit)
• Four 128K /g117 8 RAM chips are used, each with a load of 10 pF
• External data memory writes occur every other cycle, a rate of 1/(4tCK), with 50% of the pins switching
• The instruction cycle rate is 40 MHz (t CK = 25 ns) The PEXT equation is calculated for each class of pins that can drive: A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: PTOTAL = PEXT + (IDDIN2 /g117 5.0 V) Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.

Table 5. External Power Calculations (5 V Devices)

Rev. F | Page 18 of 64 | March 2008 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060L/ADSP-21062L SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (3.3 V) ELECTRICAL CHARACTERISTICS (3.3 V) A Grade C Grade K Grade Parameter Description Min Max Min Max Min Max Unit TCASE Case Operating Temperature –40 +85 –40 +100 –40 +85 /g113C VIH11 1 Applies to input and bidirectional pins: DA TA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS , TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1 VIH22

2 Applies to input pins: CLKIN, RESET, TRST

Parameter Description Test Conditions Min Max Unit VOH 1, 2 High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 2.4 V VOL 1, 2 Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V IIH 3, 4 High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA IIL 5, 6, 7, 8 Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA IOZL 5, 9 Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA IOZHP 7 Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA IOZLA 10 Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA IOZLAR 8 Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA IOZLS 11, 12 Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 4.7 pF 1 Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0 , RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS , TDO, EMU, ICSA. 2 See “Output Drive Currents” for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET , TCK. 4 Applies to input pins with internal pull-ups: DR0, DR1, TRST , TMS, TDI. 5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx, TDO, EMU. (Note that ACK is pulled up internally with 2 k /g58 during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.) 6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k/g58 during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. 10Applies to ACK pin when keeper latch enabled. 11Applies to all signal pins. 12Guaranteed but not tested.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 19 of 64 | March 2008 INTERNAL POWER DISSIPATION (3.3 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissi- pation Measurements.” Specifications are based on the operating scenarios. To estimate power consumption for a specific application, use the following equation where % is the amount of time your pro- gram spends in that state: %PEAK I DDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW + %IDLE IDDIDLE = Power Consumption Operation Peak Activity (IDDINPEAK) High Activity (I DDINHIGH) Low Activity (I DDINLOW) Instruction Type Multifunction Multifunction Single Function Instruction Fetch Cache Internal Memory Internal Memory Core memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles Parameter Test Conditions Max Units IDDINPEAK Supply Current (Internal)1 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 540 600 mA mA I DDINHIGH Supply Current (Internal)2 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 425 475 mA mA I DDINLOW Supply Current (Internal)2 tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max 250 275 mA mA I DDIDLE Supply Current (Idle)3 VDD = Max 180 mA 1 The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. 2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code. 3 Idle denotes ADSP-2106xL state during execution of IDLE instruction.

tion execution sequence and the data operands involved.

• the number of output pins that switch during each cycle (O)
• the maximum frequency at wh ich they can switch (f)
• their load capacitance (C)
• their voltage swing (V DD) and is calculated by: PEXT = O /g117 C /g117 VDD 2 /g117 f The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t CK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Example: Estimate PEXT with the following assumptions:
• A system with one bank of external data memory RAM (32-bit)
• Four 128K /g117 8 RAM chips are used, each with a load of 10 pF
• External data memory writes occur every other cycle, a rate of 1/(4tCK), with 50% of the pins switching
• The instruction cycle rate is 40 MHz (t CK = 25 ns) The PEXT equation is calculated for each class of pins that can drive: A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: PTOTAL = PEXT + (IDDIN2 /g117 5.0 V) Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed Table 7 may cause permanent dam age to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 6. External Power Calculations (3.3 V Devices) Table 7. Absolute Maximum Ratings

Table 9. Clock Input

40 MHz, 5 V

33 MHz, 5 V

1 For the ADSP-21060LC, this specification is 9.5 ns min. Figure 9. Clock Input Table 10. Reset VDD and CLKIN (not including start-up time of external clock oscillator). nicating over the shared bus (through the external port), beca use the bus arbitration logic automatically synchronizes itself a fter reset. Figure 10. Reset

Table 13. Flags 1 Flag inputs meeting these setup and hold times for instruction cycl e N will affect conditional instructions in instruction cycl e N+2. Figure 13. Flags

Table 14. Memory Read—Bus Master W = (number of wait states specified in WAIT register) /H11547 tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0). 1 Data delay/setup: user must meet tDAD or tDRLD or synchronous spec tSSDATI. 2 The falling edge of MSx, SW, BMS is referenced. 4 ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK (high). Figure 14. Memory Read—Bus Master

Table 15. Memory Write—Bus Master W = (number of wait states specified in WAIT register) × tCK. H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0). 2 The falling edge of MSx, SW, BMS is referenced. 3 See Example System Hold Time Calculation on Page 47 for cal culation of hold times given capacitive and dc loads. Figure 15. Memory Write—Bus Master

and acknowledge setup and hold times. Table 16. Synchronous Read/Write—Bus Master 1 The falling edge of MSx, SW, BMS is referenced. 3 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.

Figure 16. Synchronous Read/Write—Bus Master

registers or internal memory (in multiprocessor memory space). The bus master must meet the bus slave timing requirements. Table 17. Synchronous Read/Write—Bus Slave 1 tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabl ed, tSRWLI (min)= 4 + DT/8. 2 For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-2106 0LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max. 3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max. 4 See Example System Hold Time Calculation on Page 47 for cal culation of hold times given capacitive and dc loads. of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR. Figure 17. Synchronous Read/Write—Bus Slave

synchronous and asynchronous (HBR, HBG). Table 18. Multiprocessor Bus Request and Host Bus Request User’s Manual, Revision 2.1. 2 Only required for recognition in the current cycle. 3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN. 4 For ADSP-21060LC, specification is 8.5 – DT/8 ns max. 5 For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max. 6 (O/D) = open drain, (A/D) = active drive. 7 For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min.

Figure 18. Multiprocesso r Bus Request and Host Bus Request

SHARC User’s Manual, Revision 2.1. Table 19. Read Cycle ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. 2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max. 3 For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max. Table 20. Write Cycle

Table 21. Three-State Timing—Bus Master, Bus Slave 1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns m in. 2 Strobes = RD, WR, PAGE, DMAG, BMS, SW. 3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max. 4 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 5 Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode). Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

These specifications describe the three DMA handshake modes. MS3–0, PAGE, DATA63–0, and ACK also apply. Table 22. DMA Handshake W = (number of wait states specified in WAIT register) /H11547 tCK. HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). 1 Only required for recognition in the current cycle. be driven tDATDRH after DMARx is brought high. the number of extra cycles that the access is prolonged. 4 See Example System Hold Time Calculation on Page 47 for cal culation of hold times given capacitive and dc loads. 5 For ADSP-21062/ADSP-21062L specification is –2.5 ns min, 2 ns max. 6 For ADSP-21060L/ADSP-21062L specification is –1 ns min.

Figure 23. DMA Handshake TIMING SPECIFICATIONS FOR ADDR31–0,RD, WR, SW MS3–0, AND ACK ALSO APPLY HERE.

Table 23. Link Ports—Receive 1 For ADSP-21062, specification is 3 ns min. 2 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. 3 For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max. Table 24. Link Ports—Transmit 1 For ADSP-21060L/ADSP-21060LC, specification is 20 ns min. 2 For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max. 3 For ADSP-21062, specification is 2.5 ns max. specification is (tCK/2) – 1 ns min, (tCK/2) + 2.25 ns max. specification is (tCK/2) – 2.25 ns min, (tCK/2) + 1 ns max. ADSP-21060LC specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 18.5 ns max.

fers at 33 MHz (tCK = 30 ns) work as specified. Table 25. Link Port Service Request Interrupts:1 /g117 and 2/g117 Speed Operations 1 Only required for interrupt recognition in the current cycle. Table 26. Link Ports—Receive 1 For ADSP-21060L, specification is 5 ns min. 2 For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min. 3 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.

Table 27. Link Ports—Transmit 1 For ADSP-21060/ADSP-21060C, specification is 2.5 ns max. 2 For ADSP-21062L, specification is –2.25 ns min. 3 For ADSP-21060, specification is (tCK/4) – 1ns min, (tCK/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (t CK/4) – 1 ns min, (tCK/4) + 1.5 ns max. 4 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C, specification is (t CK/4) – 1.5 ns min, (tCK/4) + 1 ns max.

Figure 24. Link Ports—Receive THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONL Y FOR THE FIRST NIBBLE TRANSMITTED. LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

and data setup and hold, and 3) SCLK width. Table 28. Serial Ports—External Clock 1 Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns mini mum from drive edge. 3 For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min. Table 29. Serial Ports—Internal Clock 1 Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns mini mum from drive edge. Table 30. Serial Ports—External or Internal Clock Table 31. Serial Ports—External Clock

Table 32. Serial Ports—Internal Clock 2 For ADSP-21060L/ADSP-21060C, specification is 0.5 TSCLK – 2 ns min, 0.5tSCLK + 2 ns max. Table 33. Serial Ports—Enable and Three-State 2 For ADSP-21060L/ADSP-21060C, specification is 3.5 ns min; for ADSP-21062 specification is 4.5 ns min. 3 For ADSP-21062L, specification is 16 ns max. 4 For ADSP-21062L, specification is 7.5 ns max. Table 34. Serial Ports—GATED SCLK with External TFS (Mesh Multiprocessing) 1 1 Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems. Table 35. Serial Ports—External Late Frame Sync 1 MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS. 2 For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-2106 0L/ADSP-21060LC, specification is 12.8 ns max. 3 For ADSP-21060/ADSP-21060C, specification is 3 ns min.

Figure 25. Serial Ports NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

Figure 26. Serial Ports—External Late Frame Sync

/g84CA =Value from Table 37 below. /g84CA =Value from Table 38 below. Table 37. Thermal Characteristics for Thermally Enhanced variance is seen in /g84CA at 5 W. 2 LFM = Linear feet per minute of airflow. Table 38. Thermal Characteristics for BGA 1 LFM = Linear feet per minute of airflow. Table 39. Thermal Characteristics for Thermally Enhanced variance is seen in /g84CA at 5W. /g84CA at 0 LFM varies with power. /g84JC = 0.24°C/W for all CQFP models. 2 LFM = Linear feet per minute of airflow.

Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2)

Figure 39. ADSP-21060/ADSP-21062 BGA Pin Assignments (Top View, Summary)

Table 41. ADSP-2106x MQFP_PQ4, ADSP-21060CW, and ADSP-21060LCW CQFP Pin Assignments (SP-240-2, QS-240-2)

2 ADDR21 42 TFS0 82 DATA40 122 DATA13 162 L2CLK 202

91 DATA34 131 DATA6 171 L3ACK 211

Table 42. ADSP-21060CZ/21060LCZ CQFP Pin Assignments (QS-240-1)

187 L1ACK 227

Figure 40. 225-Ball Plastic Ball Grid Array [PBGA]

2.70 MAX

0.15 MAX

3 PLACES

Figure 41. 240-Lead Metric Quad Flat Packa ge, Thermally Enhanced “PowerQuad” [MQFP_PQ4]

34.60 BSC

29.50 REF

32.00 BSC

24.00 REF

0.27 MAX

0.17 MIN

Figure 42. 240-Lead Ceramic Quad Flat Package, Heat Slug Up [CQFP]

32.00 BSC SQ

0.50 BSC

1. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX

(Sweep and/or Offset can be used as the controlling dimension).

2.06 REF

Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP]

75.50 BSC SQ

29.50 BSC

1.50 DIA

70.00 BSC SQ

Figure 44. 240-Lead Ceramic Quad Flat Pac kage, Heat Slug Down [CQFP]

1. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX

(Sweep and/or Offset can be used as the controlling dimension).

Figure 45. 240-Lead Ceramic Quad Flat Pa ckage, Mounted with Cavity Up [CQFP]

2.00 DIA

Table 43. BGA Data for Use with Surface-Mount Design

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 61 of 64 | March 2008 ORDERING GUIDE Model Temperature Range Instruction Rate On-Chip SRAM Operating Voltage Package Description Package Option ASDP-21060CZ-133 1 Model refers to package with formed leads. For model numbers of unformed lead versions (QS-240-1B, QS-240-2B), contact Analog D evices or an Analog Devices sales representative. –40/g113C to +100/g113C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A ASDP-21060CZZ-1331, 2 2 Z = RoHS Compliant Part. –40/g113C to +100/g113C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A ASDP-21060CZ-1601 –40/g113C to +100/g113C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A ASDP-21060CZZ-1601, 2 –40/g113C to +100/g113C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A ASDP-21060CW-1331 –40/g113C to +100/g113C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ASDP-21060CWZ-1331, 2 –40/g113C to +100/g113C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ASDP-21060CW-1601 –40/g113C to +100/g113C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ASDP-21060CWZ-1601, 2 –40/g113C to +100/g113C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ADSP-21060KS-133 0 /g113C to 85/g113C 33 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060KSZ-1332 0/g113C to 85/g113C 33 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060KS-160 0 /g113C to 85/g113C 40 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060KSZ-1602 0/g113C to 85/g113C 40 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060KB-160 0 /g113C to 85/g113C 40 MHz 4M Bit 5 V 225-Ball PBGA B-225-2 ADSP-21060KBZ-1602 0/g113C to 85/g113C 40 MHz 4M Bit 5 V 225-Ball PBGA B-225-2 ADSP-21060LKS-133 0 /g113C to 85/g113C 33 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060LKSZ-1332 0/g113C to 85/g113C 33 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060LKS-160 0 /g113C to 85/g113C 40 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060LKSZ-1602 0/g113C to 85/g113C 40 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21060LKB-160 0 /g113C to 85/g113C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21060LKBZ-1602 0/g113C to 85/g113C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21060LAB-160 –40 /g113C to +85/g113C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21060LABZ-1602 –40/g113C to +85/g113C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21060LCB-133 –40 /g113C to +100/g113C 33 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21060LCBZ-1332 –40/g113C to +100/g113C 33 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2 ASDP-21060LCW-1331 –40/g113C to +100/g113C 33 MHz 4M Bit 3.3 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ASDP-21060LCW-1601 –40/g113C to +100/g113C 40 MHz 4M Bit 3.3 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ASDP-21060LCWZ-1601, 2 –40/g113C to +100/g113C 40 MHz 4M Bit 3.3 V 240-Lead CQFP [Heat Slug Down] QS-240-1A ADSP-21062KS-133 0 /g113C to 85/g113C 33 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062KSZ-1332 0/g113C to 85/g113C 33 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062KS-160 0 /g113C to 85/g113C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062KSZ-1602 0/g113C to 85/g113C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062KB-160 0 /g113C to 85/g113C 40 MHz 2M Bit 5 V 225-Ball PBGA B-225-2 ADSP-21062KBZ-1602 0/g113C to 85/g113C 40 MHz 2M Bit 5 V 225-Ball PBGA B-225-2 ADSP-21062CS-160 –40 /g113C to +100/g113C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062CSZ-1602 –40/g113C to +100/g113C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LKS-133 0 /g113C to 85/g113C 33 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LKSZ-1332 0/g113C to 85/g113C 33 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LKS-160 0 /g113C to 85/g113C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LKSZ-1602 0/g113C to 85/g113C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LKB-160 0 /g113C to 85/g113C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21062LKBZ-1602 0/g113C to 85/g113C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21062LAB-160 –40 /g113C to 85/g113C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21062LABZ-1602 –40/g113C to 85/g113C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2 ADSP-21062LCS-160 –40 /g113C to +100/g113C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2 ADSP-21062LCSZ-1602 –40/g113C to +100/g113C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

Rev. F | Page 62 of 64 | March 2008 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F | Page 63 of 64 | March 2008

Rev. F | Page 64 of 64 | March 2008 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00167-0-3/08(F) ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC