AS9C25512M2018L-166BC

AS9C25512M2018L ALSC | Alldatasheet

Document overview

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Technical content

Features

• True Dual-Port memory cells that allow simulta- neous access of the same memory location
• Organisation: 524,288/262,144 × 18 [1]
• Fully Synchronous, independent operation on both ports
• Selectable Pipeline or Flow-Through output mode
• Fast clock speeds in Pi peline output mode: 250 MHz operation (9Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out- put mode
• Asynchronous output enable control
• F a s t O E access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out- put Mode
• 19/18 [1]-bit counter with Increment, Hold and Repeat features on each port
• Dual Chip enables on both ports for easy depth expansion
• Interrupt and Collision Detection Features
• 2.5 V power supply for the core
• LVTTL compatible, selectable 3.3V or 2.5V power supply for I/Os, addresses, clock and control signals on each port
• Snooze modes for each port for standby operation
• 15mA typical standby current in power down mode
• Available in 256-pin Ball Grid Array (BGA), 144-pin Thin Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array (fpBGA)
• Supports JTAG features compliant with IEEE 1149.1 Selection guide Feature -250 -200 -166 -133 Units Minimum cycle time 4 5 6 7.5 ns Maximum Pipeline clock frequency 250 200 166 133 MHz Maximum Pipeline clock access time 2.8 3.4 3.6 4.2 ns Maximum flow-through clock frequency 150 133 100 83 MHz Maximum flow-through clock access time 6.5 7.5 10 12 ns Maximum operating current TBD 350 300 260 mA Maximum snooze mode c u r r e n t 1 81 81 81 8 m A Note: 1. AS9C25512M2018L/AS9C25256M2018L

9/24/04, v.1.2 Alliance Semiconductor P. 2 of 30 Dual port logic block diagram Note: 1. Address A18 is a NC for AS9C25256M2018L REGISTER BANK QD REGISTER BANK QD R/W Control O/P ControlO/P Control PL/FT REGISTER BANK Q D

1 PL/FT

A18[1] A-A0A CE0A CE1A R/WA PL/FTA INTA COLA CLKA ZZA TDI TDO REGISTER BANK Q D REGISTER BANK Q D R/W Control O/P Control O/P Control PL/FT REGISTER BANK QD PL/FT REGISTER BANK Q D REGISTER BANK Q D Mirror Register Increment Logic Address Decoding Snooze Logic BE1B-BE0B Address Counter B CE0B CE1B R/WB PL/FTB RPTB ADSB INCB A18[1] B-A0B CE0B CE1B R/WB PL/FTB INTB COLB CLKB ZZB TMS TRST TCK DQ17A-DQ0A DQ17B-DQ0B QoutA<17:0> QoutB<17:0> DinB<17:0>DinA<17:0> OPTB CLKB OPTA CLKA OEB OPTA OPTB

9/24/04, v.1.2 Alliance Semiconductor P. 3 of 30 General Description The AS9C25512M2018L/AS9C25256M2018L is a high- speed CMOS 9/4.5-Mbit synchronous Du al-Port Static Random Access Memory device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock- to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation. Each port contains a 19/18 bit li near burst counter on the input address register that can loop through the whole address seque nce. After externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control, data, and address inputs provide minimal setup and hold times. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write to a certain location while another port is reading from the same location, but the validity of re ad data is not guaranteed. Ho wever, the reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than one port at the same time is undefined. The Asynchronous Output Enable input pin allo ws asynchronous disabling of output buffer s at any given time. The Byte Enable inp uts allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. AS9C25512M2018L/AS9C25256M2018L can support an ope rating voltage of either 3.3V or 2. 5V on either or both ports, which is controlled by the OPT pins. The power supply for the core of the de vice (VDD) is at 2.5V . This device is available in 256-pin B all Grid Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP) Address Counter The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire memory array. The Address counter features are discussed below: Load: Any required external address ca n be loaded on to the counter. This feature is similar to normal addres s load in conventional memories. Increment: The address counter has the capability to internally increment the address value, po tentially covering the entire memory arra y. Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known location has to be loaded before Increment operation. Hold: The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs. Repeat: The previously loaded address (l oaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18 bit register called “Mirror register” is us ed to hold the last loaded address.This re gister is not initialized on Power-up, hen ce a known location has to be loaded before Repeat operation (Refer Counter control truth table for details).

9/24/04, v.1.2 Alliance Semiconductor P. 4 of 30 Ball Assignment - 256-ball BGA Note: 1. Address A18 is a NC for AS9C25256M2018L 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A NC TDI NC A17 A A14A A11A A8A NC CE1 A OEA INCA A5A A2A A0A NC NC A BI N T A NC TDO A18[1] A A15A A12A A9A BE1A CE0A R/WA RPTA A4A A1A VDD NC NC B CC O L A DQ9A VSS A16 A A13A A10A A7A NC BE0 A CLKA ADSA A6A A3A OPTA NC DQ8 A C D NC DQ9 B NC PL/FT A VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB VDD NC NC DQ8 B D E DQ10 B DQ10A NC VDDQ A VDD VDD NC VSS VSS VSS VDD VDD VDDQ B NC DQ7 A DQ7B E F DQ11 A NC DQ11 B VDDQA VDD NC NC VSS VSS VSS VSS VDD VDDQ B DQ6B NC DQ6 A F G NC NC DQ12 A VDDQB VSS VSS VSS VSS VSS VSS VSS VSS VDDQ A DQ5A NC NC G H NC DQ12 B NC VDDQ B VSS VSS VSS VSS VSS VSS VSS VSS VDDQ A NC NC DQ5 B H J DQ13 A DQ14B DQ13B VDDQA ZZB VSS VSS VSS VSS VSS VSS ZZ A VDDQB DQ4B DQ3B DQ4A J K NC NC DQ14 A VDDQA VSS VSS VSS VSS VSS VSS VSS VSS VDDQ B NC NC DQ3 A K L DQ15 A NC DQ15 B VDDQB VDD NC NC VSS VSS VSS VSS VDD VDDQ A DQ2A NC DQ2 B L M DQ16 B DQ16A NC VDDQ B VDD VDD NC VSS VSS VSS VDD VDD VDDQ A DQ1B DQ1A NC M N NC DQ17 B NC PL/FT B VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA VDD NC DQ0 B NC N PC O L B DQ17A TMS A16 B A13B A10B A7B NC BE0 B CLKB ADSB A6B A3B NC NC DQ0 A P RI N T B NC TRST A18[1] B A15B A12B A9B BE1B CE0B R/WB RPTB A4B A1B OPTB NC NC R T NC TCK NC A17 B A14B A11B A8B NC CE1 B OEB INCB A5B A2B A0B NC NC T 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 AS9C25512M2018L/AS9C25256M2018L B - 256 Top view

9/24/04, v.1.2 Alliance Semiconductor P. 5 of 30 Ball Assignment - 208-ball fpBGA Note: 1. Address A18 is a NC for AS9C25256M2018L 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 A DQ9 A INTA VSS TDO NC A16 A A12A A8A NC VDD CLK A INCA A4A A0A OPTA NC VSS A BN C V S S C O L A TDI A17 A A13A A9A NC CE0 A VSS ADS A A5A A1A NC VDDQ B DQ8A NC B C VDDQ A DQ9B VDDQB PL/FTA A18[1] A A14A A10A BE1A CE1A VSS R/W A A6A A2A VDD DQ8 B NC VSS C D NC VSS DQ10 A NC A15 A A11A A7A BE0A VDD OE A RPTA A3A VDD NC VDDQ A DQ7A DQ7B D E DQ11 A NC VDDQ B DQ10B DQ6A NC VSS NC E F VDDQ A DQ11B NC VSS VSS DQ6 B NC VDDQ B F G NC VSS DQ12 A NC NC VDDQ A DQ5A NC G H VDD NC VDDQ B DQ12B VDD NC VSS DQ5 B H J VDDQ A VDD VSS ZZ B ZZA VDD VSS VDDQ B J K DQ14 B VSS DQ13 B VSS DQ3B VDDQA DQ4B VSS K L NC DQ14 A VDDQB DQ13A NC DQ3 A VSS DQ4 A L M VDDQ A NC DQ15 B VSS VSS NC DQ2 B VDDQB M N NC VSS NC DQ15 A DQ1B VDDQA NC DQ2 A N P DQ16 B DQ16A VDDQB COLB TRST A16B A12B A8B NC VDD CLK B INCB A4B NC DQ1 A VSS NC P R VSS NC DQ17 B TCK A17 B A13B A9B NC CE0 B VSS ADS B A5B A1B NC VDDQ A DQ0B VDDQB R T NC DQ17 A VDDQA TMS A18[1] B A14B A10B BE1B CE1B VSS R/W B A6B A2B VSS NC VSS NC T UV S S I N T B PL/FTB NC A15 B A11B A7B BE0B VDD OE B RPTB A3B A0 B VDD OPT B NC DQ0 A U 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 AS9C25512M2018L/AS9C25256M2018L F - 208 Top view

9/24/04, v.1.2 Alliance Semiconductor P. 6 of 30 Pin Assignment - 144-pin TQFP PL/FTA NC NC A18 [1] A A17A A16A A15A A14A A13A A12A A11A A10A A9A A8A A7A BE1A BE0A CE1A CE0A VDD VSS CLK A OEA R/WA ADSA INCA RPTA A6A A5A A4A A3A A2A A1A A0A VDD NC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS 1 108 OPT A VDDQB 2 107 VDDQ B VSS 3 106 VSS DQ9A 4 105 DQ8 A DQ9B 5 104 DQ8 B DQ10A 6 103 DQ7 A DQ10B 7 102 DQ7 B DQ11A 8 101 DQ6 A DQ11B 9 100 DQ6 B VDDQA 10 99 VSS VSS 11 98 VDDQ A DQ12A 12 97 DQ5 A DQ12B 13 96 DQ5 B VDDQB 14 95 VSS ZZB 15 94 VDDQ B VDD 16 93 VDD VDD 17 92 VDD VSS 18 91 VSS VSS 19 90 VSS VDDQA 20 89 ZZ A VSS 21 88 VDDQ A DQ13B 22 87 DQ4 B DQ13A 23 86 DQ4 A DQ14B 24 85 DQ3 B DQ14A 25 84 DQ3 A VDDQB 26 83 VSS VSS 27 82 VDDQ B DQ15B 28 81 DQ2 B DQ15A 29 80 DQ2 A DQ16B 30 79 DQ1 B DQ16A 31 78 DQ1 A DQ17B 32 77 DQ0 B DQ17A 33 76 DQ0 A VSS 34 75 VSS VDDQA 35 74 VDDQ A NC 36 73 OPT B PL/FT B NC NC A18[1] B A17B A16B A15B A14B A13B A12B A11B A10B A9B A8B A7B BE1B BE0B CE1B CE0B VDD VSS CLKB OEB R/WB ADSB INCB RPTB A6B A5B A4B A3B A2B A1B A0B VDD NC AS9C25512M2018L/AS9C25256M2018L T - 144 Top view Note: 1. Address A18 is a NC for AS9C25256M2018L

9/24/04, v.1.2 Alliance Semiconductor P. 7 of 30 Signal description Notes: 1. Subscript 'x' represents 'A' for Port A and 'B' for Port B. 2. OPTx,VDDQx and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port. OPTx = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQx must be supplied at 2.5V . Each port can independently operate on either of the VDDQ levels. 4. If unused JTAG inputs may be left unconnected. 5. JTAG , Collision Detection & Interrupt features are not supported in TQFP package. 6. Address A18 is a NC for AS9C25256M2018L. Signal I/O Properties Description NotesPort A Port B CLKA CLK B IC L O C K Clock. Each port has an independent Clock input that can be of different frequencies. All inputs except OEx and ZZx are synchronous to the corresponding port’s clock and must meet setup and hold time about the rising edge of the clock. A0A - A18A A0 B - A18B I SYNC External Address. Sampled on the ri sing edge of corresponding port clock 6 DQ0A - DQ17A DQ0B - DQ17B I/O SYNC Bidirectional data pins CE0A, CE1A CE0 B, CE1B IS Y N C Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of corresponding port clock. R/WA R/WB I SYNC Read/Write enable. Drive th is pin LOW to write to, or HIGH to Read from the memory array. BE0A - BE1A BE0 B - BE1B IS Y N C Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. (Refer Byte Control Truth Table) ADSA ADSB IS Y N C Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter Control Truth Table) INCA INCB IS Y N C Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control Truth Table) RPTA RPTB IS Y N C Address Counter Repeat. Active low. Reloads the counter with the previously loaded external address.(Refer Counter Control Truth Table) OEA OEB I ASYNC Asynchronous output enable. I/O pins are driven when the OE is low and the chip is in Read mode. A high on OE tristates the I/O pins. ZZA ZZB I ASYNC Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an internal pull-down and can be floating. PL/FTA PL/FTB IS T A T I C Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When high, enables double register Pipeline mode. This pin has an internal pull-up and can be left floating to operate in pipeline mode. OPTA OPTB IS T A T I C VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses, clock, and controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V mode. 1,2,3 INTA INTB OS Y N C Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth Table) 5 COLA COLB OS Y N C Collision Alert Flag. Used to indicate collision during simultaneous memory access to the same location by both the ports (Refer Collision Detection Truth Table) 5 VDDQA VDDQB I POWER Power to I/O bus. Can be 3.3V or 2.5V depending on OPT x input. 1,2,3 VDD I POWER Power Inputs (To be connected to 2.5V Power supply) 2 VSS I GROUND Ground Inputs (To be connected to Ground supply) TCK I CLOCK (JTAG) JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock. 4,5 TDI I SYNC (JTAG) JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. 4,5 TDO O SYNC (JTAG) JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally tristated except when the captured data is shifted out of the JTAG TAP. 5 TMS I SYNC (JTAG) JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. 4,5 TRST I ASYNC (JTAG) JTAG Test Reset Input. Asynchronous input used to initialize TAP controller. 4,5

9/24/04, v.1.2 Alliance Semiconductor P. 8 of 30 Byte control truth table[1,2,3,4,5] Notes: 1. L = low, H = high 2. CE0 = L, CE1 = H (Chip in Select mode) 3. R/W = H for a Read operation, R/W = L for a Write operation 4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0] 5. More than one byte enable may be simultaneously asserted Read/write control truth table[1,4] Notes: 1. L = low, H = high, X = don't care 2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H) 3. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DQn refers to the corresponding Byte 4. Snooze de-asserted (ZZ=L) 5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams] 6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. All DQs are tristated on power-up 8. OE should be asserted (OE = L) (Refer Read timing waveform) 9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L Counter control truth table[1,2,5,6] Notes: 1. L = low, H = high, X = don't care 2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BEn) 3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BEn (i.e Counter works independent of R/W, CE0,CE1 and BEn) 4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content. 5. Clock to the counter is disabled during Snooze mode (True for both ports). 6. The counter and the mirror registers are not initialized on Power-up (refer Counter description). BE1 BE0 CLK Mode H H L to H All Bytes Deselected - NOP H L L to H Read or Write Byte 0 L H L to H Read or Write Byte 1 CE[2] R/W BEn [3] CLK Operation DQn[0:8][3,7] H X X L to H Chip Deselect Hi-Z [5,9] L X H L to H Byte Deselect Hi-Z [5,9] L L L L to H Byte Write Din [6] L H L L to H Byte Read Qout [5,8] CLK ADS[3] INC[3] RPT[3] External Address Previous Address Accessed Mirror Register Content[4] Address Accessed Operation L to H L X H An X An An Load [4] L to H H L H X An Am An + 1 Increment L to H H H H X An Am An Hold L to H X X L X X Am Am Repeat

9/24/04, v.1.2 Alliance Semiconductor P. 9 of 30 Package Thermal Resistance Notes: 1. This parameter is sampled. Capacitance[1] (TA = +25 °C, F = 1.0 Mhz)[2] Notes: 1. Sampled, not 100% tested 2. T A stands for 'Ambient temperature'. 3. L = 0V; H = 3V Absolute maximum ratings[1] Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect reliability. Description Conditions Symbol Typical Units Thermal Resistance (junction to ambient)[1] Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 BGA θ JA TBD °C/W fpBGA θJA TBD °C/W TQFP θJA TBD °C/W Thermal Resistance (junction to top of case)[1] θJC TBD °C/W Parameter Symbol Signals Test Condition[3] B G A (Max) f p B G A (Max) T Q F P (Max) Unit Input Capacitance C IN Address and Control pins VIN = L to H or H to L TBD TBD TBD pF Output Capacitance C OUT Flag Output pins V OUT = L to H or H to L TBD TBD TBD pF I/O Capacitance C I/O I/O pins V I/O = L to H or H to L TBD TBD TBD pF Rating Parameter Symbol Min Max Unit Core supply voltage relative to VSS VDD -0.5 3.6 V I/O supply voltage relative to VSS VDDQ -0.3 3.9 V Input and I/O voltage relative to VSS V IN -0.3 VDDQ + 0.3 V Power Dissipation P D -T B D W Short circuit output current I OUT -T B D m A Storage Temperature T STG -65 150 °C Storage Temperature under Bias T BIAS -55 125 °C Junction Temperature T JN -T B D ° C

9/24/04, v.1.2 Alliance Semiconductor P. 10 of 30 Recommended operating Temperature Recommended operating conditions Notes: 1. OPT pin for a given port must be set to VSS(0V) to operate at VDDQ = 2.5V levels on the I/Os, addresses, clock and controls of that port. 2. OPT pin for a given port must be set to VDD(2.5V) to operate at VDDQ = 3.3V levels on the I/Os, addresses, clock and controls of that port. Notes: 1. Outputs disabled (High-Z condition). Grade Ambient Temperature (TA) Commercial 0°C to 70°C Industrial -40°C to 85°C VDDQ = 2.5V[1] VDDQ = 3.3V[2] Parameter Symbol Min Typ Max Min Typ Max Unit G r o u n d V S S 000000 V VDDQ = 2.5V VDDQ = 3.3V Parameter Symbol Test Conditions Min Max Test Conditions Min Max Units Input Leakage Current |ILI| VDDQ = Max; 0V < VIN < VDDQ VDDQ = Max; 0V < VIN < VDDQ -2 µ A PL/FT and ZZ Input Leakage Current |ILI| VDD = Max; 0V < VIN < VDD VDD = Max; 0V < VIN < VDD -2 µ A Output Leakage Current[1] |ILO| OE>=VIH; 0V < VOUT < VDDQ OE>=VIH; 0V < VOUT < VDDQ -2 µ A Input high (logic 1) voltage (Address, Control, Clock & Data Inputs) VIH - 1.7 VDDQ + 0.1V - 2 VDDQ + 0.15V V Input high voltage (ZZ,OPT,PL/FT) VIH - VDD - 0.2V VDD + 0.1V - VDD - 0.2V VDD + 0.1V V Input low (logic 0) voltage (Address, Control, Clock & Data Inputs) Input low voltage (ZZ,OPT,PL/FT) VIL - -0.3 0.2 - -0.3 0.2 V Output low voltage V OL IOL = +2mA; VDDQ = Min -0 . 4 IOL = +4mA; VDDQ = Min -0 . 4 V Output high voltage V OH IOH = -2mA; VDDQ = Min 2.0 - IOH = -4mA; VDDQ = Min 2.4 - V

9/24/04, v.1.2 Alliance Semiconductor P. 11 of 30 IDD operating conditions and maximum limits[4] (VDD = 2.5 V ± 100 mV) Notes: 1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions). 2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (VIN > VDDQ - 0.2V or VIN < 0.2V) and TTL (VIN > VIH or VIN < VIL) level inputs. 3. CEA and CEB are internal signals (CEx = L implies CE0x < VIL and CE1x > VIH, CEx = H implies CE0x > VIH or CE1x < VIL). 4. Subscript 'x' represents 'A' for Port A and 'B' for Port B. 5. “A” and “B” are interchangeable. Parameter Symbol Test Conditions -250 -200 -166 -133 Units Typ Max Typ Max Typ Max Typ Max Operating current (Both ports active) Pipeline mode -- (PL/FT > VIH) ICC Both ports enabled (CEA = CEB = L[3]), Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL, f=fMax [1] TBD TBD TBD 350 TBD 300 TBD 260 mA Operating current (Both ports active) Flow-through mode (PL/FT < VIL) TBD TBD TBD TBD TBD TBD TBD TBD mA Standby current (Both ports) ISB1 Both ports disabled (CEA = CEB = H), ZZA = ZZB < VIL, f=fMax [1] TBD TBD TBD 105 TBD 90 TBD 80 mA Standby current (One port) ISB2 One port enabled (CEA = L and CEB = H)[5], Active port's outputs disabled, ZZA = ZZB < VIL, f=fMax [1] TBD TBD TBD 265 TBD 225 TBD 190 mA Full standby current (Both ports) ISB3 Both ports disabled (CEA = CEB = H), ZZA = ZZB < VIL, f=0[2] 20 25 20 25 20 25 20 25 mA Full standby current (One port) ISB4 One port in Snooze (ZZA > VIH, ZZB < VIL, and CEB = L)[5], Active port's outputs disabled, f=f Max [1] TBD TBD TBD 265 TBD 225 TBD 190 mA Snooze mode current IZZ Both ports in Snooze (ZZA = ZZB > VIH), f=fMax [1] 15 18 15 18 15 18 15 18 mA

9/24/04, v.1.2 Alliance Semiconductor P. 12 of 30 AC timing characteristics[1,2,5,6] (VDD = 2.5 ± 100mV) Notes: 1. All timings are same for both ports. 2. These values are valid for either level of VDDQ (2.5V/3.3V) 3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V . Each port can independently operate in any of these modes. 4. Output Enable (OE) is an asynchronous input. 5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation. 6. Refer AC Test Conditions to view the test conditions used for these measurements. 7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location. 8. To avoid bus contention, at a given voltage and temperature tLZC is more than tHZC (True in both Pipeline and flow-through output mode). Parameter Symbol -250 -200 -166 -133 Unit Notes Clock Cycle Time (Pipeline) tCYCP 4 - 5 - 6 - 7.5 - ns 3 Clock High Pulse Width (Pipeline) tCHP 1.7 - 2 - 2.4 - 3 - ns 3 Clock Low Pulse Width (Pipeline) tCLP 1.7 - 2 - 2.4 - 3 - ns 3 Cycle Time (Flow-Through) tCYCF 6.5 - 7.5 - 10 - 12 - ns 3 Clock High Pulse Width (Flow-Through) tCHF 1.7 - 2 - 2.4 - 3 - ns 3 Clock Low Pulse Width (Flow-Through) tCLF 1.7 - 2 - 2.4 - 3 - ns 3 Output Clock access time (Pipeline) tCDP - 2.8 - 3.4 - 3.6 - 4.2 ns 3 Output Data Hold from Clock High (Pipeline) tOHP 1 - 1 - 1 - 1 - ns Clock High to Output Low-Z (Pipeline) tLZCP 1 - 1 - 1 - 1 - ns 3,8 Clock High to Output High-Z (Pipeline) tHZCP 12 . 813 . 413 . 614 . 2 n s 3 , 8 Clock access time (Flow-Through) tCDF - 6.5 - 7.5 - 10 - 12 ns 3 Output Data Hold from Clock High (Flow-Through) tOHF 1 - 1 - 1 - 1 - ns Clock High to Output Low-Z (Flow-Through) tLZCF 1 - 1 - 1 - 1 - ns 3,8 Clock High to Output High-Z (Flow-Through) tHZCF 12 . 813 . 413 . 614 . 2 n s 3 , 8 Output Enable to Data Valid tOE - 2.8 - 3.4 - 3.6 - 4.2 ns 4 Output Enable Low to Output Low-Z tLZOE 1 - 1 - 1 - 1 - ns 4 Output Enable High to Output High-Z tHZOE 12 . 813 . 413 . 614 . 2 n s 4 Setup Address Setup to Clock High Chip Enable Setup to Clock High tCES 1.2 - 1.5 - 1.7 - 1.8 - ns Byte Enable Setup to Clock High tBS 1.2 - 1.5 - 1.7 - 1.8 - ns R/W Setup to Clock High tWS 1.2 - 1.5 - 1.7 - 1.8 - ns Input Data Setup to Clock High tDS 1.2 - 1.5 - 1.7 1.8 - ns ADS Setup to Clock High tADSS 1.2 - 1.5 - 1.7 - 1.8 - ns INC Setup to Clock High tINCS 1.2 - 1.5 - 1.7 - 1.8 - ns RPT Setup to Clock High tRPTS 1.2 - 1.5 - 1.7 - 1.8 - ns Hold Address Hold from Clock High Chip Enable Hold from Clock High tCEH 0.3 - 0.5 - 0.5 - 0.5 - ns Byte Enable Hold from Clock High tBH 0.3 - 0.5 - 0.5 - 0.5 - ns R/W Hold from Clock High tWH 0.3 - 0.5 - 0.5 - 0.5 - ns Input Data Hold from Clock High tDH 0.3 - 0.5 - 0.5 - 0.5 - ns ADS Hold from Clock High tADSH 0.3 - 0.5 - 0.5 - 0.5 - ns INC Hold from Clock High tINCH 0.3 - 0.5 - 0.5 - 0.5 - ns RPT Hold from Clock High tRPTH 0.3 - 0.5 - 0.5 - 0.5 - ns Flag Interrupt Flag Set Time tSINT - 6 - 6 - 6 - 7n s Interrupt Flag Reset Time tRINT - 6 - 6 - 6 - 7n s Collision Flag Set Time tSCOL - 2.8 - 3.4 - 3.6 - 4.2 ns Collision Flag Reset Time tRCOL - 2.8 - 3.4 - 3.6 - 4.2 ns Port-to-Port Delay Clock-to-Clock Delay tCCO 3.0 - 3.5 - 4 - 5 - ns 7

9/24/04, v.1.2 Alliance Semiconductor P. 13 of 30 Timing waveform of read cycle[7] Notes: 1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics). 3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1 4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte. 5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H). 6. OE is an asynchronous input. 7. All timings are similar for both ports. 8. Read with Byte disabled. Data is not read out.Bus in High-Z condition. CLK CE[3] ADDRESS[5] OE[6] BEn[4] R/W [Pipeline Mode] tCEH tCES A1 A2 tCYC [2] tCLtCH tAS tAH tBS tBH A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Q10 Read (A1) tCDP tOHP tHZCP tLZCP tHZOE tLZOE DATA OUT[1] Q1 Q2 Q8 Read (A2) Dsel Read[8] (A4) Dsel Read (A6) Read (A7) Read (A8) Dsel Read (A10) Dsel Read (A12) Don’t care Undefined tOE tWS tWH tLZOE [Pipeline Mode] Q1 Q10 tCDF tOHF tHZCFtLZCF tHZOE tLZOE Q1 Q2 Q8 tOE tLZOE OE[6] [Flow-through Mode] [Flow-through Mode] DATA OUT[1] Q12

9/24/04, v.1.2 Alliance Semiconductor P. 14 of 30 Timing wave form read/write cycle[7] Notes: 1. Both Flow-through and Pipeline Inputs/Outputs indicated.A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation.(Refer AC Timing characteristics) 3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1 4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte. 5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H). 6. OE is an asynchronous input. 7. All timings are similar for both ports. 8. Invalid write. Memory Content of the selected location may get corrupted and should be re-written before future readback. 9. Write (A11) is invalid in Pipeline mode and Write (A8) is invalid in Flow-through mode. Memory Content of the selected location may get corrupted and should be re-written before future readback. CLK CE[3] ADDRESS[5] OE[6] BEn[4] R/W DATA IN[1] DATA IN[1] [Flow-through Mode] [Pipeline Mode] DATA OUT[1] DATA OUT[1] tCEH tCES D3 D6 Q1 Q2 A1 A2 tCYC [2] tCL tCH tAS tAH tBS tBH tWS tWH tCDP tLZCP tCDF tLZCF tOHF tHZCF tHZOE tDS tDH tDH tDS A3 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D3 D6 D11 Q4 Q7 Q9 Read (A1) Read (A2) Write[8] Write (A3) (A5) Read Read Read (A7) Write[9] (A8) Read (A9) Dsel Write[9] (A11)(A4) Write (A6) [Pipeline Mode] [Flow-through Mode] tHZCP tHZOE Don’t care Undefined OE[6] [Flow-through Mode] [Pipeline Mode]

9/24/04, v.1.2 Alliance Semiconductor P. 15 of 30 Timing waveform of address counter[6] Notes: 1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low, and in Pipeline mode if PL/FT is driven high or left unconnected. 2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics). 3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). Timings indicated for CE hold good for CE0 and CE1. 4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn. 5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also. 6. All timings are similar for both ports. CLK CE[3] R/W [Pipeline Mode] DATA OUT[1] [Flow-through Mode] tCEH tCES tCYC [2] tCLtCH Write (A1) DATA OUT[1] Incr A1ADDRESS A1 A1+1 A1+2 A1+2 A1+1 A1+2 A1+2 A2 A2+1 A2+1 A2A1 D1 D1+1 D1+2 D1+2 Q1 Q1+1 Q3 Q4 Q1 Q1+1 DATA IN RPT INC ADS ADDRESS INTERNAL Hold Rept tWH tWS tAS tAH tADSS tADSH tINCS tINCH tRPTS tRPTH tDS tDH tHZCFtOHFtCDF tLZCF tLZCP tCDP tOHP tHZCP Q1+2 Q1+2 Don’t care Undefined [4] [5] [5] Load Incr WriteWriteWrite Read Read Read Read Incr Incr Hold Load (A2) Dsel Dsel Dsel Dsel ReptHoldIncr

9/24/04, v.1.2 Alliance Semiconductor P. 16 of 30 Mailbox Interrupts The AS9C25512M2018L/AS9C25256M2018L has an Inbui lt Mailbox Logic that can be used fo r communication between the two ports. One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center for Port A and 7FFFF (HEX) for Port B (3FFFE and 3FFFF for AS9C25256M2018L). The port A interrupt flag (INTA) is asserted when the port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C2525 6M2018L). The port A clears the interrupt flag by reading the address location 7FFFE (HEX) (3F FFE for AS9C25256M2018L). Likewise, the port B interrupt flag (INT B) is asserted when the port A writes to memory location 7FFFF (HEX) (3FFFF for AS 9C25256M2018L) and to clear the interrupt flag (INT B), the port B must read the memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table). The interrupt flag is asserted in a flow-t hrough mode (i.e., it follow s the clock edge of the writ ing port). Also, the flag is reset in a flow- through mode (i.e., it follows the clock edge of the reading port). Each por t can read the other por t’s mailbox without de-asse rting the interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT pins can be ignored. Interrupt logic truth table[1,4,5] Notes: 1. L = low, H = high, X = don't care 2. CEx is an internal signal ('x' = 'A' or 'B'). CEx = H implies 'Chip is Deselected' (CE0x = H or CE1x =L), CEx = L implies 'Chip is Selected' (CE0x = L and CE1x =H) 3. Address specified here is the internal address (refer Counter control truth table). 4. Both Interrupt Flags are De-asserted on power-up. 5. Interrupt feature is not supported in TQFP package. 6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE CLKA R/WA CEA [2] A18A-A0A [3,6] CLKB R/WB CEB [2] A18B-A0B [3,6] INTA INTB Function L to H L L 7FFFF L to H X X X X L Assert Port B Interrupt Flag L to H X X X L to H H L 7FFFF X H De-assert Port B Interrupt Flag L to H X X X L to H L L 7FFFE L X Assert Port A Interrupt Flag L to H H L 7FFFE L to H X X X H X De-assert Port A Interrupt Flag

9/24/04, v.1.2 Alliance Semiconductor P. 17 of 30 Interrupt timing wave form[2] Notes: 1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics). 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. 3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle. 4. 7FFFF (3FFFF for AS9C25256M2018L) is the Mailbox for port B and 7FFFE (3FFFE for AS9C25256M2018L) is the Mailbox for port A. 5. “Aa” and “Ab” refer to any other valid address other than 7FFFF or 7FFFE (3FFFF or 3FFFE for AS9C25256M2018L). tCYC [1] tCH [1] tCL [1] CLKA R/WA [2] tWS tWH tAS tAH INTA ADDRESSA [3] CLKB R/WB [2] ADDRESSB [3] INTB 7FFFF tWH tWS tCYC [1] tCH [1] tCL [1] tSINT tRINT tSINT tRINT tAH tAS 7FFFF 7FFFE 7FFFF 7FFFE 7FFFE Don’t care [4] [4] Aa Aa Aa Aa Ab Ab Ab Ab [5] [5] Aa Ab

9/24/04, v.1.2 Alliance Semiconductor P. 18 of 30 Collision detection Three different cases of collisions can be listed depending on the type of access from two ports: Simultaneous Read: A true dual-ported memory cell allows data to be read s imultaneously from both ports of the device. Hence no data is corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted. Simultaneous Write: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the collision flag is asserted on both ports. Simultaneous Read and Write : When one port is writing and the other port is read ing from the same location in the memory, the data written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted. The alert flag (COL x) is asserted on the 3rd (for both pipe-lined and flow-t hrough output mode) ri sing clock edge of the affected port following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision alert flag will be asserted and de-asserted every alternate cycle. Collision detection truth table[1,2,4,5] Notes: 1. L = low, H = high, X = don't care 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected. 3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table). 4. Both Collision Flags are De-asserted on power-up. 5. Collision detection feature is not supported in TQFP package. CLKA R/WA CLKB R/WB Port address[3] COLA COLB Function L to H H L to H H MATCH H H Both ports reading. Not a valid collision. No collision flag asserted on either port. L to H H L to H L MATCH L H Port A reading, Port B writing. Valid collision. Collision flag asserted on port A. L to H L L to H H MATCH H L Port B reading, Port A writing. Valid collision. Collision flag asserted on port B. L to H L L to H L MATCH L L Both ports writing. Valid collision. Collision flag asserted on both ports. L to H L L to H H NO MATCH H H No match. No collision flag asserted on either port.

9/24/04, v.1.2 Alliance Semiconductor P. 19 of 30 Collision timing waveform[2] Notes: 1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics). 2. Chip Selected (CE0 = L and CE1 =H). True for both ports. 3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle. 4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address. 5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics). CLKA ADDRESSA [3] R/WA Am Aa Am Aa Aa Am Aa Am Am Am Am Aa COLA CLKB ADDRESSB [3] R/WB Am Ab Am Ab Ab Am Ab Am Am Am Am Ab COLB tCH [1] tCYC [1] tCL [1] tWS tAS tAH tCH [1] tCL [1] tCYC [1] tAS tAH tWS tWH tCCO tSCOL tRCOL tSCOL tRCOL tWH Don’t care [5] [4] [4]

9/24/04, v.1.2 Alliance Semiconductor P. 20 of 30 Depth and Width expansion AS9C25512M2018L/AS9C25256M2018L has two chipselect s (one active high and ot her active low) for simp le depth expansion. This permits easy upgrade from 512/256K de pth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an expanded width of 36 bits or wider. Notes: 1. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L 2. A<0:19> for AS9C25512M2018L, A<0:18> for AS9C25256M2018L 3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L Timing waveform of multi device read[4,5,6] Notes: 1. Parameters t CYC, tCH and tCL are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics). 2. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L 3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L 4. Refer to the above block diagram for the assumed setup. 5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion. 6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L. RPT INC ADS OE BE<0:1> R/W CLK CE1 CE0 RPT INC ADS OE BE<0:1> R/W CLK CE1 CE0 A<0:18>[1] DQ<0:17> A<0:18>[1] DQ<0:17> A<0:18>[1] A<0:18>[1] DQ<0:17> DQ<18:35> A<0:18>[1] A<0:18>[1] DQ<0:17> DQ<18:35> A<19>[3] A<19>[3] Clock Clock Data Address Controller Microprocessor BANK 1 BANK 0 512/256Kx18 DPSRAM DPSRAM DQ<0:35> A<0:19>[2] 512/256Kx18 tCH tCL tCYC [1] CLK R/W A[19][3] DATA OUT [0:35] [Pipeline Mode] (BANK 0) (BANK 1) DATA OUT [0:35] A[0:18][2] [Flow-through Mode] [Pipeline Mode] DATA OUT [0:35] (BANK 0) DATA OUT [0:35] [Flow-through Mode] (BANK 1) tAS tAH tWS tWH A1 A2 A3 A4 A5 A6 A7 A8 tCDP tOHP tHZCP tLZCP Q1 Q2 Q4 tCDP tOHP tHZCP tLZCPtCDF tOHF tHZCF tLZCF Q4Q1 Q2 tCDF tOHF tHZCF Q5 Q6 Read (Bank0) (Bank0) Read (Bank1) Read Read Read Read (Bank0) (Bank1) (Bank1) Read (Bank0) tLZCF Q5 Q6 Don’t care Undefined

9/24/04, v.1.2 Alliance Semiconductor P. 21 of 30 Snooze mode Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a very low value. Both ports are equipped with independent SN OOZE inputs (ZZ). During Snooze mode, all inputs of the port except ZZ are internally disabled and all its Outputs go to High-Z. ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode, the device is deselected and current is reduced to I ZZ. When ZZ A and ZZ B become a logic HIGH, I ZZ is guaranteed after the setup time tSCZZ is met. Any READ or WRITE operation pending when the port enters S nooze mode is not guaranteed to complete. Therefore, Snooze mode must not be initiated until valid pending oper ations are completed. Similarly during the time t RCZZ, when the port is transitioning out of snooze mode, only DESELECT cycles should be given. Snooze mode electrical characteristics Snooze mode timing waveform[1,3] Notes: 1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZx must be held Low in order to capture the parallel inputs of the bound- ary scan register. All static inputs (i.e. PL/FTx,OPTx) and ZZx themselves are not affected during snooze mode. 2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H). 3. All timings are same for Port A and Port B. 4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data integrity. 5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles. Description Conditions Symbol Min Max Units SNOOZE MODE Current ZZ A = ZZB >= VIH IZZ 15 18 mA ZZ active to input ignored t SCZZ - 2 cycle ZZ inactive to input sampled t RCZZ 2 - cycle ZZ active to enter Snooze Current t SIZZ - 2 cycle ZZ inactive to exit Snooze Current t RIZZ 0 - cycle CLK tCH tCYC tCL Don’t care tCEH tCES tSIZZ tRIZZ IZZ tSCZZ ZZ setup cycles tRCZZ ZZ recovery cycles High-Z CE[2,4] ZZ ISupply OUTPUTS[5] INPUTS (Except ZZ) (Qout) tHZC tLZC Undefined V alid Va li d

9/24/04, v.1.2 Alliance Semiconductor P. 22 of 30 AC test conditions Input Pulse Level (Address and Controls) GND to 3.0V/GND to 2.4V Input Pulse Levels (I/Os) GND to 3.0V/GND to 2.4V Input Rise/Fall Times 2V/ns Input Timing Reference Levels 1.5V/1.25V Output Reference levels 1.5V/1.25V Output Load (for t LZC, tHZC, tLZOE, tHZOE)F i g . C Output Load (for all other measurements) Fig. B Thevenin equivalent: GND 10% 90% 90% 10% +3.0/2.4 V Figure A: Input Waveform DOUT Z0 = 50Ω 50 Ω VL = 1.5/1.25 V +3.3/2.5 V; 5 pF* GND Figure B: Output Load (A) Figure C: Output Load (B) * Including scope and jig capacitance 10 pF* 319Ω / 1667Ω 353Ω / 1538Ω

9/24/04, v.1.2 Alliance Semiconductor P. 23 of 30 IEEE 1149.1 Serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels. In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in a reset state which will not interfere with normal device operation. TAP Controller block diagram Note: 1. x = 111 JTAG timing waveform Selection Circuitry Selection Circuitry 31 30 29 0 12... Boundary Scan Register1 Identification Register Bypass Register Instruction Register x[1] 012 012 TDI TMS TCK TDO TAP Controller TEST CLK TRST tJCYC TCK TMS/TDI TDO tJCH tJCL tJIS tJIH tJOH tJCD tJRS tJRR Don’t care Undefined

9/24/04, v.1.2 Alliance Semiconductor P. 24 of 30 TAP AC electrical characteristics[2] Notes: 1. tJCS and tJCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in the figure TAP AC output load equivalent. TAP AC test conditions & output load equivalent TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV) Description Symbol Min Max Units Clock Clock cycle time t JCYC 100 - ns Clock frequency f JTAG - 10 MHz Clock high time t JCH 40 - ns Clock low time t JCL 40 - ns Output Times TCK low to TDO unknown t JOH 0 - ns TCK low to TDO valid t JCD -2 0 n s Setup Times TMS/TDI setup t JIS 10 - ns Capture setup t JCS [1] 10 - ns Hold Times TMS/TDI hold t JIH 10 - ns Capture hold t JCH [1] 10 - ns Reset Times JTAG Reset t JRS 50 - ns JTAG Reset Recovery t JRR 50 - ns Description Symbol Conditions Min Max Units Input high (logic 1) voltage V IH 1.7 VDD + 0.3 V Input low (logic 0) voltage V IL -0.3 0.7 V Input leakage current |I LI| VDD = Max; 0V < V IN < VDD 0 10 µA Output leakage current |I LO| Outputs disabled, 0V < V OUT < VDDQ (DQx)0 1 0 µ A Output low voltage V OLC I OLC = 100µA 0.2 V Output low voltage V OLT I OLT = 2mA 0.7 V Output high voltage V OHC I OHC = -100µA 2.1 V Output high voltage V OHT IOHT = -2mA 1.7 V TDO 50Ω ZO=50Ω 1.25V 20pF Input pulse levels Vss to 2.5V Input rise and fall times 1V/ns Input timing reference levels 1.25V Output reference levels 1.25V Test load termination supply voltage 1.25V

9/24/04, v.1.2 Alliance Semiconductor P. 25 of 30 Identification register definitions Scan register sizes Instruction codes Instruction field Value Description Revision number (31:28) TBD Version Number Device depth (27:12) TBD ALSC part number JEDEC ID code (11:1) 00001010010 Manufacturer Identity Code (ALSC) Indicator Bit (0) 1 ID Regi ster presence indicator Register name Bit size Instruction Register (IR) 4 Bypass Register (BYR) 1 Identification Register (IDR) 32 Boundary Scan Register (BSR) 112 Instruction Code Description Selected Reg EXTEST 0000 Forces contents of the BSR onto the device outputs. BSR SAMPLE/PRELOAD 0001 Samples the I/O ring contents. Preloads test data into the BSR. BSR IDCODE 0010 Loads the IDR with the vendor ID code and places the register between TDI and TDO. IDR CLAMP 0011 Forces contents of the BSR onto the device outputs. BYR HIGHZ 0100 Forces all device 2-state and 3-state outputs to High-Z. BYR RESERVED 0101 - 1110 Reserved states. Do not use. BYR BYPASS 1111 Places the BYR between TDI and TDO. BYR

9/24/04, v.1.2 Alliance Semiconductor P. 26 of 30 Package Diagram: 256-ball Ball Grid Array (BGA) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 oooooooooooooooooooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo oooooooooooooooo A1 corner index All measurements are in mm. Min Typ Max A 1.00 B 16.95 17.00 17.05 C 15.00 D 16.95 17.00 17.05 E 15.00 F 0.36 G 0.35 0.50 H 1.60 I 0.40 0.50 0.60 J 0.70 0.35 ~ 0.50

1.60 MAX

0.36 0.70 0.35 Z Top View Bottom View Side View A B C A E D D F HG0.20 Z 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 + + A B C D E F G H J K L M N P R T / 0.50±0.10 (256X) Ø 0.15 Ø 0.25 Z Z XY Detail of Solder Ball I M M o o o o A B C D E F G H J K L M N P R T J

9/24/04, v.1.2 Alliance Semiconductor P. 27 of 30 Package Diagram: 208-ball fine pitch Ball Grid Array (fpBGA) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 oooooooooooooooooooooooooooooooooo ooooooooooooooooo ooooooooooooooooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo oooo ooooooooooooooooo ooooooooooooooooo ooooooooooooooooo ooooooooooooooooo ooooooooooooooooo / 0.45±0.05 (208X) Ø 0.08 Ø 0.15 A1 corner index All measurements are in mm. Min Typ Max A 0.80 B 14.95 15.00 15.05 C 12.80 D 14.95 15.00 15.05 E 12.80 F 0.26 G 0.25 0.40 H 1.40 I 0.40 0.45 0.50 J 0.70 Z Z XY 0.25 ~ 0.40

1.40 MAX

0.26 0.70 0.20 Z Top View Bottom View Side View Detail of Solder Ball A B C A E D D F HG I 0.15 Z M M 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 o A B C D E F G H J K L M N P R T U o o o A B C D E F G H J K L M N P R T U J

9/24/04, v.1.2 Alliance Semiconductor P. 28 of 30 Package Diagram: 144-pin Thin Quad Flat Pack (TQFP) TQFP Min Typ Max A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.20 0.27 c 0.09 0.20 D 20.00 nominal E 20.00 nominal e 0.50 nominal Hd 22.00 nominal He 22.00 nominal L 0.45 0.60 0.75 L1 1.00 nominal α 0° 3.5° 7° Dimensions in millimeters A1 A2L1 L c He E Hd D b e α

9/24/04, v.1.2 Alliance Semiconductor P. 29 of 30

Ordering Information

1. Alliance Semiconductor prefix 2. Speciality Memory 3. Operating V oltage: 25 - VDD = 2.5V 4. Device depth: 512 - 512K; 256 - 256K 5. M20 - Multiport - 2port, SSRAM, DCD 6. I/O width - 18 7. I/O interface: L - LVTTL 8. Clock speed (MHz) 9. Package Type: T - TQFP, B - BGA, F - fpBGA 10. Operating Temperature: C - Commercial (0 0C to 700C); I -Industrial (-400C to 850C) Package & Width -250 -200 -166 -133 512K X 18 BGA X 18 AS9C25512M2018L - 250BC AS9C25512M2018L - 200BC AS9C25512M2018L -166BC AS9C25512M2018L - 133BC AS9C25512M2018L - 250BI AS9C25512M2018L - 200BI AS9C25512M2018L - 166BI AS9C25512M2018L - 133BI fpBGA X 18 AS9C25512M2018L - 250FC AS9C25512M2018L - 200FC AS9C25512M2018L - 166FC AS9C25512M2018L - 133FC AS9C25512M2018L - 250FI AS9C25512M2018L - 200FI AS9C25512M2018L - 166FI AS9C25512M2018L - 133FI TQFP X 18 AS9C25512M2018L - 250TC AS9C25512M2018L - 200TC AS9C25512M2018L - 166TC AS9C25512M2018L - 133TC AS9C25512M2018L - 250TI AS9C25512M2018L - 200TI AS9C25512M2018L - 166TI AS9C25512M2018L - 133TI 256K X 18 BGA X 18 AS9C25256M2018L - 250BC AS9C25256M2018L - 200BC AS9C25256M2018L -166BC AS9C25256M2018L - 133BC AS9C25256M2018L - 250BI AS9C25256M2018L - 200BI AS9C25256M2018L - 166BI AS9C25256M2018L - 133BI fpBGA X 18 AS9C25256M2018L - 250FC AS9C25256M2018L - 200FC AS9C25256M2018L - 166FC AS9C25256M2018L - 133FC AS9C25256M2018L - 250FI AS9C25256M2018L - 200FI AS9C25256M2018L - 166FI AS9C25256M2018L - 133FI TQFP X 18 AS9C25256M2018L - 250TC AS9C25256M2018L - 200TC AS9C25256M2018L - 166TC AS9C25256M2018L - 133TC AS9C25256M2018L - 250TI AS9C25256M2018L - 200TI AS9C25256M2018L - 166TI AS9C25256M2018L - 133TI AS 9C 25 512/256 M20 18 L -XXX T or B or F C/I 1 234567 8 9 1 0

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: AS9C25512M2018L/ AS9C25256M2018L Document Version: v.1.2 © Copyright 2003 Alliance Semiconductor Corp oration. All rights reserved. Our three-po int logo, our name and Intelliwatt are tr ademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of th eir respective companies. Alliance reserve s the right to make changes to this document and its products at any time without notice. Alliance assumes no respon sibility for any errors that ma y appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product desc ribed herein is under development, signifi cant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or cust omer. Alliance does not assume any responsib ility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringe ment of any intellectual property rights, except as express ag reed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sa les of Alliance products are made exclusively according to Allian ce's Terms and Conditions of Sale. The purchase of products from Allianc e does not convey a license under any pate nt rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Allianc e does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to resu lt in significant injury to the user, and the inclusion of All iance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS9C25512M2018L AS9C25256M2018L