AS8C161831

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• 512K x36, 1M x 18 memory configurations Description * Supports high performance system speed - 200 MHz The AS8C163631/1831 are 25V high-speed 18,874,368-bit (3.2 ns Clock-to-Data Access) (18 Megabit) synchronous SRAMs. They are designed to eliminate dead * ZBT™ Feature - No dead cycles between write and read bus cycles when tuming the bus around between reads and writes, or cycles writesand reads Thus, they have been given the name ZBT™, or Zero | * Internally synchronized output buffer enable eliminates the | Bus Turnaround | need to control OE Address and control signals are applied to the SRAM during one | * Single R/W (READ/WRITE) control pin clock cycle, and two cycles later the associated data cycle occurs, be it * Positive clock-edge triggered address, data, and control read or write | signal registers for fully pipelined applications The AS8C163631/1831 contain data |/O, address andcontrolsignal * 4-word burst capability (interleaved or linear) registers Outputenable isthe only asynchronous signal and canbe used * Individual byte write (BW: - BWa) control (May tie active) todisable the outputs atany given time * Three chip enables for simple depth expansion AClock Enable CEN pin allows operation of the AS8C163631/1831 * 25V power supply (£5%) tobesuspendedaslongasnecessary Allsynchronousinputsare ignored * 25V VO Supply (Vppo) when (CEN)is high and the internal device registers will hold theirprevious * Power down controlled by ZZ input values: > = r * Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) There are three chip enable pins (CE1, CE2, CE2) that allow the | * Packaged in a JEDEC standard 100-pin plastic thin quad user to deselect the device when desired Ifany one of these three isnot flatpack (TQFP) asserted when ADV/LDis low, nonewmemory operation canbe initiated Pin Description Summary Address Inputs Input Synchronous a a Ta A sora ot OCTOBER 2010 DSO-5313/09

AS8C163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V W/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Description (cont.) However, anypending data transfers (reads orwrites) willbecompleted | interleaved burst sequence The ADV/LD signal is used to load a new Thedata bus will tri-state two cycles after the chipisdeselectedorawrite | externaladdress(ADV/LD=LOW) orincrementthe internal burstcounter isinitiated (ADV/LD = HIGH) The AS8C163631/1831 have an on-chip burst counter In the burst | The AS8C163631/1831 SRAMS utilize Alliance's atesthigh-periormance mode, the AS8C163631/1831 can provide fourcyclesofdataforasingle | 25V CMOS process, and are packaged in a JEDEC Standard 14mm x | address presented to the SRAM. The order of the burst sequence is | 20mm 100pinthin plastic quad flatpack (TQFP) defined by the LBO input pin The LBO pin selects between linear and Pin Definitions™ | Smet | Pafowis [WO [aoe [eS Ao-Ais ‘Address inputs WA | Synchronous Address inpu's The address register is triggered by a combinaton of the rising edge of CLK | ADVILD low, CEN iow, and tue chip enables. i Aoi Advance / Load NA | ADV/LDis a synchronous input that is used to load the intemal registers with new address and contro! when it is | sampled low at the rising edge of clock with the chip selected When ADV/ID is low with the chip deselected, i any bust in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced | for any bust that was in progress. The extemal addresses are ignored when ADV/LD is sampled high. | RW Read / Wile WA _ | RAW signal is a synchronous input that idenifies whether the curent load cycle inialed is a Read or Write access i to the memory array. The dala bus actvily for he current cycle takes place two clock cycles later CEN Clock Enable LOW | Synchronous Clock Enable Input When CEN is sampled high, all other synchronous inpuss, including clock are ignored and oulputs remain unchenged The effect of CEN sampled high on the device outpus is as if the low to high clock tansion did not occur For nonmal operation, CEN must be sampled low at rising edge of clock. BWBW: | Individue Byte LOW | Synchronous byle wile enables Each Sit byte has its own active low byle wrile enable On load wile cycles | Write Enables {when AW and ADVILD are sampled low) the appropriate byte write signal (BW:-BW) must be valid The byte L wile signal must also be valid oneach cycle ofa burstwite Byte Wrie signals are ignored when R/W is sampled high The appropriate byie(s) of data are writen ini the device two cycles Jaier BWi-BW: can al be fied low if always doing write to the entre 26-bit word | th C& Chip Enables LOW | Synchronous active low chip enable CE: and CE are used with CE2 to enable the AS8C163631/1831 (CE: or CE i ‘sampled high or CE2 sampled low) and ADV/CD iow at the rising edge of clock, initiates a deselect cycle The Z8T™ has a two cycle deselect, ie, the data bus will stale Iwo clock cycles aller deselect is initiated CE Chip Enable HIGH | Synctronous actve high chip enable. CE2 is used with CE: and GE2to enable the chip CEz has inverted polatty but otherwise identical to CE! and CEz, CLK Clock NA ___| This is the clock input to the AS8C163631/1831 Except for OE all timing references forthe device are made with respect to te rising edge of CLK. VOovOs! | Data InpuYOutput NA | Synchronous data inpuoutput (VO) pins Both the data input path and data output pah are regislered and tiggered L VOP1-VOPs by the rising edge of CLK ii'e) Linear Burst Order LOW | Burst order selection input When LBO is high the interleaved burst sequence is selected When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. Ouput Enabie Low | Asynetvonous output enable OE must be low to read data trom the asecxsaeati1eas When OE is high the VO pins are ina Pighirpedarce state OE does not need to be actvely controlled for read and wile cycles in normal operation, OF can be tied lov. Test Mode Select | 1 | NA | Gives input command for TAP contolle: Sampled on rising edge of TOK. This pin hes aninlemal pulup. (| ewan for ve | Ser input of registers placed between TDi and TOO Sampied on rising edge of TCK This pin hes an intemal Clock input of TAP controller. Each TAP event is clocked Testinputs are captured on rising edge of TCK while Tox Test Clock | NA Jest oupuis are driven from he fang edge of TCK. This pin has an intemal pulup. Test Oata Ouput Serial output of registers placed between TDI and TDO This ouput is actve depending on the stale of the TAP | coniroller. STAG Reset Optional asynchronous JTAG reset Can be used lo resetthe TAP contoller but not required JTAG reset occurs TRST (Optona Low | automatcally at power up and also resets using TMS and TCK per IEEE 1491 fi not used TRST can be let floating. This pin has an intemal pulup. Orly available in BGA package. 2 Sleep Mod Hig | S¥fehvonous sleep made input. ZZ HIGH wil gat the CLK intemal and power down the AS8C163631/1831 10 its intel lowest power consumption level, Data retention s guaranteed in Sleep Mode. This pin has an intemal puldown. Power Supply 2.8V core power supply. weve NOTE:

1 Alisynchronous inputs must meet specified setup and hold times with respect to CLK

AS8C 163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Functional Block Diagram TBO 512Kx36 BIT MEMORY ARRAY Address A [0:18] 2D a Address CEI, CE2,CE2 | | | RW oa Control CEN . ADvAD : Do i BW i t | Dea@ ok iz: “ Geek Boman | x ket so1aerwo1 T™s aL) sag DO Data VO [0:31], TCK VO P{1:4) SS, TBO Ld 1x8 BIT MEMORY ARRAY Address A [0:19] dp ak Address TEs, cE2, CE2 a Fly ob Control CEN —1 apvilD Fa Dio } fe CS Control Logic | Ok | | at Sel D ] Clock Output Register x | E ae hy S313 deworb T™s | ’ Tot mae D0 Data VO [0:15], Tck — | VO P[1:2] RSI, —— 7

AS8C 163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Recommended DC Operating Recommended Operating | Conditions Temperature and Supply Voltage [we [ove [woe Toit] (oe ] ambient Tes | yoo | vom Yoo | Core Supply Voltage 2.375 ‘Temperature’ V igh Voltage - 7 03 ert Input High Votlge-v0 [1.7 | — | Vocosos] v | 1 During producton tesing the case temperature equals the ambiant tmperature er sae

1 Vic {min} = -08V for pulse width less than tcvc/2, once per cycle

Pin Configuration — 512K x 36 Ig - 3/2) 35,0 M2l%y Den

2218 Miglglalaid 8 2 S2/8iy 8 2 g22

100 58 58-97-56 95 94 93 G2 S190 60 68 a7 6 8 84 09 82 81 vorsL_]1 ie) 80 [J vOre vOwL 2 mf iis vorbas v2 Ediois L voooL_] + 77 {J vooo vss(]5 76 (J vss vowlJe 75 (_] yors voisCa? 74 FJ yore vOaljs af Jyon vOaC 9 ve J vo vssE 10 7 FV vss VooeL_] 1 70 [J vooa Vee] 12 6 [J yoo vOes] 13 eal] Oe Vvoot] 14 e7 [J vss Voo{_] 15 6 [J voo voo] 16 6s I) voo Vesa 17 «fz L vO2s] 18 63[—] vor VO2sC_] 19 e2 [J vos vooaL_j 20 6: £) vooe vssLer 0 FJ vss vO2sC_ 22 sof) vos VOa Je s8 [5 yO t VOzeCZ] 24 s7 [J vos vOesL_j 2s ss [J] vO2 vssCZ] 26 ssf] vss VoooL_J 27 [2 vooe vOsoL 28 83 [J vor vOaiCj 28 s2 [2 voo VOrsL_ 30 si] vopr 3152 59 54 96 96 97 99 29 40 41 2 9 as a5 46 47 48 49 59 UUUUUUUDUUUUUUUUUUUUE ewerce P2222 ee pe 88oU 2282822 er ce Top View

100 TQFP

NOTES:

1 Pins 14 16 and 66 do not have to be connected directly to Voo as long as the input voltage is > Vie

2 Pins 38, 39 and 43 will be pulled internally to Von if not actively driven To disable the TAP controller without interfering with normal operation several settings are possible. Pins 38, 39 and 43 could be tied to Voo or Vss and pin 42 should be left unconnected. Or all JTAG inputs (TMS TDI and TCK) pins 38 39 and 43 could be left unconnected "NC and the JTAG circuit will remain disabled from power up 3 Pin 43 is reserved for the 36M address JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device

AS8C163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 25V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Pin Configuration — 1 Mx 18 Absolute Maximum Ratings 2 2i8 8 9 lglg 8 8 S18ig 8 2 222 aa Teawvemeun 7 «inal Voltage wit le) Cc ‘Vrerm® | Terminal Voltage with v net a. P noe mene Respect to GNO 0510 Von 08'0 Veo nots ra ING } > Vooa is 7 3) veca Vien? | Terminal Voltage with . gry v Vests Stove Respect to GND D5 to Vo0 +05 | -05to Voo +05 nope nc Net 78 Fad Orn Vreaa®® | Terminal Voltage with . v ie ° 4 Respect to GND 05 to Vora +05 | -05t0 Vora +05 Vss | 10 mF) vss Hi vooo E11 nf vo ” Operating Ambient ‘ . vw Le ov |™ ‘Temperature 0b +70 40 t0 +85 C von Eis eftiee veo 5, es EV vo0" vss C7 2B z gj P| voulez = foie parr vrs ]29 »fva NOTES: wees 25 fe 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may vss fos sf Ves cause permanent damage to the device This is a stress rating only and functional ooo =| 2 # = Vooa operation of the device at these or any other conditions above those indicated vee sBx in the operational sections of this specification is not implied Exposure to absolute fom SFI No maximum rating conditions for extended periods may affect reliabilty ueeussywyonegusuceso 2 Veo terminals ony UUUUUUUOEOOOOOOU TUTE sss 3500 terminals only fr ig _ QaSS Qe zeczzce 4° Input terminals only 5 9 $5 5 VO terminals only.

2 Fy 6 This is a steady-state DC parameter that applies after the power supply has

Fy reached its nominal operating value Power sequencing is not necessary; Top View however, the voltage on any input or /O pin cannot exceed Vooa during power

100 TQFP supply ramp up

NOTES: 7 During production testing, the case temperature equals Ta

1 Pins 14, 16, and 66 do not have to be connected directly to Von as long as

the input vollage is 2 Vix

2 Pins 38, 39 and 43 wil be pulled internally to Voo if not actively driven To

disable the TAP contoller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to Voo or Vss and r pin 42 should be left unconnected Or all JTAG inputs (TMS, TD! and TCK) pins 38 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up 3. Pin 43 is reserved for the 36M address JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device 100-Pin TQFP Capacitance (Ta= +25°C, f = 1.0MHz) simbo | Peane? [conto [or [ tr] Input Capacitance Vin = 3dV

10 Capacitance

AS8C 163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Synchronous Truth Table™ CEN Chip) | avid ADDRESS PREVIOUS CYCLE CURRENT CYCLE ie) Enable USED (2 cycles later) L x x H Vali Internal LOAD WAITE / BURST WRITE on | BURST WRITE (Advance burst countey® | L x x H x intemal LOAD READ / BURST READ qn | BURST READ (Advance burst counter® 599106 NOTES:

1 L= Vu, H = Vm, X = Don't Care

2 When ADVILO signal is sampled high, the internal burst counter is incremented The A/W signal is ignored when the counter is advanced Therefore the nature of the burst cycle (Read or Writa) is determinad by the status of the PAW signal when the first address is loaded at the beginning of the ourst cycle. 3 Deselect cycle is initiated when either (CEs, or CE2 is sampied high or CEz is sampled low) and AOVICD is sampled low at rising edge of clack The data bus will tri-state two cycles alter deselect is initiated 4 When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part The state of all the internal registers and the WOsremainsunchanged 5 Toselect the chip requires CE: = L, CEz=, CE2=H on hese chip enables Chip is deselected if any one of the chip enables is false

8 Device Outputs are ensured 10 be in High-Z alter the first rising edge of clock upon power-up

7 Q- Data read from the device D - dala written to the device

Partial Truth Table for Writes READ WRITE ALL BYTES WATE BYTE 1 WO(O7, vor re ee ee eee WATE BYTE 2 WO IS, FOr a ee ee ee NOWATE sgl oF NOTES:

1 L= Vu, H= Va, X = Dont Care

2 Multiple bytes may be selected during the same cycle

3 NA for X18 configuration

AS8C 163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 25V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Interleaved Burst Sequence Table (LBO=Vpp) NOTE: S813 D1 10 1 Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting Linear Burst Sequence Table (LBO=Vss) ee ee ee a NOTE: 313 B11 1 Upon completion of the Burst sequence the counter wraps around to its initial stata and continues counting Functional Timing Diagram") CYCLE n29n430 n431 ne32 n33 ns n45 n36 00437 r — i cLocK (2) | | : ADDRESS A29 | (A380 A31 A382 A33 A384 A35 A386 A387 (Ao - Ara) contro.” | | ce9 C30 C31 C32 C33 C34 C35 C36 C37 (RIW, ADV/LD, BWx) (2) , DATA p/a27 | pias | pia2e | o/aso | pasi | D/as2 pass | pias4 | D/Q35 VOj0:31}, VO Pray 5313drw 03 NOTES: _ 1 This assumes CEN. CE: CE2 CE2 are all true 2 All Address, Control and Data_in are only required to meet set-up and hold time with respect to the rising edge of clock Data_Out is valid after a clock-to-data delay from the rising edge of clock

2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles’) Tom [ saiem [om [om [om [om [oe [a [wo [ommw C= Pet» fats [ope fxs [x fiw +d Oe a Der fox pep fe fe [| onion id Feof m Pepe pepe pe [x Po fore id a ree? x fxf{« [xpetx px] o feo 4 reef x pepe Pxpe pe fe | o fete | Cerf» fete te Pe fete fo fw 4 NOTES: 5313 BI 12 L

1 CE=Lis defined as CE: = L, CE2 = and CE2=H CE = His detined as CE: =H CE2=H or CE2=L

2 H=High; L = Low; X = Don't Care; Z = High Impedance

Read Operation") oe [ sone [ot [ons [om [OR [ oe OT vo foe Leet Pet x Lax fx Px [1 | om [oom nace merece | NOTES: $318 DIG 1 H = High; L = Low; X = Don't Care; Z = High impedance.

2 CE=Lis defined as CE1 = CE2=L and CE2 =H CE = His defined as CE1 = H CEe =H or CE2=L

SSPE RISA REECE SOS NERS ES EL EAU

AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Burst Read Operation) poe fom Pap Pe Pe Fx Tx Tx [rcarss na cont moat soup NOTES: seen

1 H=High;L = Low; X = Don | Care; 2 = High Impedance

2 CE=Lis defined as CE: =L CE2=Land CE2=H CE =H is defined as CE: =H CE2 =H or CE2=L

Write Operation) Nc Sno NOTES:

1 H-= High; L = Low; X = Don't Care; Z = High Impedance a

2 CE=Lis defined as CE: = L, CE2 = L and CE2=H CE = His defined as CE1 = H, CEe = Hor CRe = Lb

Burst Write Operation“) soe NOTES: 1 H= High; L = Low; X = Dont Care; ? = Don't Know; Z = High Impedance 2. CE=Lis defined as CE1 = L CEz=LandC&2=H CE =His defined as CE: = H CEe =H or CE2=L

2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Read Operation with Clock Enable Used‘) Fone | te [mi | oi [oe [| oe] oF [we [ome a ee EO ee NOTES: seen 1 H = High; L = Low; X = Don't Care; Z = High impedance.

2 CE =Lis defined as CE: = L, CE2 = L and CE2=H CE =His defined as CE1 = H CE2 = Hor CE2=L

Write Operation with Clock Enable Used" [eae | me | om avs [om [et om] of [Wem] A a beeps pep pe pe pp fo fom A sone NOTES: 1 H= High; L = Low; X = Don't Care; Z = High Impedance. — .

2 CE=Lis defined as CEr=1 CE2=LandCE2=H CE =H is defined as CE1=H CE2=H or CE2=L

2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Read Operation with Chip Enable Used) [ene [tome [0m | | om | om | om | OF [wn foamed Peep pep po it | eee pe ep a a ia so | NOTES: sere 1 He High; L = Low; X = Don't Care; ? = Don't Know, Zz High impedance _ _

2 CE=Lis defined as CEs=L CE2=L and CE2=H CE =His defined as CE: =H CE2=H or CE2=L

1. Device Outputs are ensured to be in High-Z alter the first rising edge of clock upon power-up Write Operation with Chip Enable Used") see | ee | | ts [om | | om | |W [em A A a A Peep eo ee rece rs NOTES: sean 1 H-= High; L = Low; X = Don't Care; ? = Dont Know; Z = High Impedance =

2 CE =Lis defined as CEr=L CE2=L and CE2=H CE =H is defined as CE: = H CE2 = H or CE2 = L

1 All values are maximum guaranteed values

3 For VOs VHo = Vooo~ 02V Vio = 02V For other inputs VHo = Voo - 02V Vin = 02V i

8 Figure 1, AC Test Load Output Timing Reference Levels (Vooa/2)

5 AC Test Load See Figure 1

Figure 2. Lumped Capacitive Load, Typical Derating

2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Temperature Ranges) [oe [ ie [ise [meme sy Paranr Fan [a me Pe a | CT [fe lewrewe | pe |— fe] fw] Pm [— [oe [ae] a eS | fam lomammeomune [off] —fel—[s[—[s] =| ees Joormoome bole fels]sls>elels| | «| a A fo [asessantw tw {—[e]—[s|-|v]—-]o]—]e | fs fownsoome fe [=P [= fe [= Po f= To [=] | fo fraawmesarme ef Pe [= Ps [Tv [- To [Te [so [ronataas novionwtne [ret —fist—{s{—| 7]—] || r [so op eaneseecrsap tom [|] is] —]s[-]) |] @[—] | [lore vie cane iiysap me | ie|—fe]—]st—-)v]-l[—le| [x __[aaememame [| —-]@]—[s]-]=|[-[=[-]*] fm [asinsstow tne ‘fos f [sf —]os}—]os]—|o[—| | [wor [rsanstoes ovinyroa we [oe | —[os]—[os{—[es{—]os|—|w| [ie [ove wienoe Bvgnowrmme [oe | — [os —[os{—]os|—]os]—|w] NOTES: 5313 bat 1 iF = teye 2 Measured as HIGH above 0.6Vo00 and LOW below 0 4Vo0a

3 Transition is measured +200mV from steady-state

1. These parameters are guaranteed with the AC load (Figure 1) by device characterization They are not production tested § Toavoid bus contention. the output butfersare designed such that tcxz (device turn-off} is faster than tciz (device turn-on)ata given temperatureand voltage The specsasshown donotimply bus contention because tc:zisa Min parameterthatis worse case at totally differenttestconditions (0deg C 2 625V) thantcuz whichisaMax parameter (worse case at70deg C,2375V)

AS8C 163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of Read Cycle1:2:3.4) | Fi g 8 Ae 3 g 8

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AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of Write Cycles(1:2;3,4.5) H & 2 i 3 £3 Bks g 2 3 8 i 82 8 2 § 2 | 34 = Bs ae 3 & 3 zon o S2e 232 bg See 3 5 sh Ses 2 & za 2 ese 2g sik 4 ge2 a & sp 2% g28 2 5 a sau 3 8 es | S88 § & | sag ¢ = 2 gece% so dx] 22088 2 3 3| 23523 8 & & eras § E588 8 peeee 3 r

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AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of Combined Read and Write Cycles(1-2>) l | 8 | q 0) q be : rs A : | ; | b<J 2 j > A ge gf ia fa g 488 | y ai Fe SEE B85 ess 223 je Ls) gos | =et zg L if ‘ 225 2se 282 S's | | 2e< ><] Sey x2 ess Sis a ne 2 ig ‘ { °8z 282 < so Q eee 5 ss ° q q 0) ie eB s2 = Esko Zoe x ht exes PS £ex8 | = 1% | K g 3828 i P 3 oges 1 8 gees a) tt ae le AH i sis3 t Hz2= 88 (2) eSaee a Qo wes i: n & z jus z ia iz fa) iat 5 2 8 8 ¢ 6 4 < FA

AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of CEN Operation(1:2:3.4) | 8 | im se 3 — | by s 3 s S Y pe: | . ia 1a Be 332 ge 8 = EB = ass 2 go5 8 ge 22 2 Ke BSE § 3 | Z52 = Vas! SAR s (3 i gEe & B88 2 ww & 2 Hl BE 2 | 258 = - asf < Es é 2es q 22 2 F ! J By S48 5 8 <2 sirss g Ie 8 , 26535 > Sy 2) Ny Ofsas NJ gjss 85585 t 4 A t=) Sue sas Sb e282 22ge55 Eassze EBcsis "4 $eR228 _ 228392 | SS8Segs | Bosse FS 223 J eyeeea . eebess - _ ia ; 2 & = woz 5 SP2238 é 6 & & € g8 € BZ 3 gece’ a x = 0 < & @Salh g3e Fd a iT = a < Bose sss 2 6 E o Ziacs +

AS8C 163631, AS8C161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of CS Operation 2:3:4) i | Ss f-—}-+ ° Bg 5 Bg fa 3 a8 ke. al gE SS | vy i = 3 | Ss B Zea a $5 2 S25 3 Pee Bee beet Be Bs Bee = | ca $28 2 P< S33 § ; age z F a ial RG . oS ess 68 t y iy g22 s | 4 bx Su § 2 bX 225e2 L | (_] alge 38 = ze8ee2 2 tae cis $o228 g2es32 ' . Tara fae) a J ff ath sty 2 £a5255 222282 ezsegR 2258298 a ogee ae ~ — — S2E5s= YU | g55238 A epitas x iz Tal I 2 <n < ™ z 5 G@zSzRSB a8 8 & ~@ 8 € B Zg 8 Sap 2a% a x = 2 < & S 2 8 Fa 2 4 5 Zeus ¥ < &

AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V V/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range JTAG Interface Specification tucyc UF. a TCK Devieg aS Cc rovrus Ga US tuoc Device Outputs®/ ee TDO pale tJRSR tcD ms k M5313 drw 01 tJRST NOTES:

1 Device inputs = All device inputs except TOI, TMS and TRST

2 Device outputs = All device outputs except TDO r

3 During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically TRST is an optional JTAG reset Characteristics 1:2:3:4) |_Simbe) ister Si ul [win [x | Scan Register Sizes noe | sme Gack rpaPema | wo | — |e | as Coenen | wo | — | | Register Nae r TG Goa tw | | — [m= | [ismton ra | st TAG Goek se Tne | — | a | vw | |Siass 6A) IAG Gock Faltine | — |e” | me | [TAG Werticaton oR |e sme reset [0 | — [ rs | Booty Sn OS weet sme resetRecovey [so | — | ms | yore . JTAG Data Output | — | 2 | «| 1 The Boundary Scan Descriptive Language (BSDL) file for this device is available ee a moseo [2 | — | | sacred | | = | ss | NOTES:

1 Guaranteed by design

2 AC Test Load (Fig. 1) on external output signals

3 Refer to AC Test Conditions stated earlier in this document

4 STAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet

‘AS8C163631, AS8C161831, 512K x 36, 1M x 18, 2.8V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range JTAG Identification Register Definitions Revision Number (31:28) Reserved for version number. IOT Device 10 (27:12) Defines part number AS8C 163631 and AS8C161831, respectively IDT JEDEC 1D (11:1) Allows unique identiicaton of device vendor ID Register Indicator Bit (Bit 0) Indicates the presence of an ID register woe Available JTAG Instructions | Forces contents of the boundary scan cells onio the device outputs" EXTEST Places the boundary scan register (BSR) between TDI and TDO 000 Places the boundary scan register (BSR) between TDI and TDO SAMPLE allows data from device inputs” and outputs” to be captured E SAMPLE/PRELOAD in the boundary scan calls and shifted serially through TDO PRELOAD ooo allows data to be input serially inlo the boundary scan cells via the TOI DEVE ID Loads the JTAG ID register (JIOR) with the vendor ID code and places r - the register between TDI and TDO HIGHZ Places the bypass register (BYR) between TDI and TDO Forces all device outpul drivers to a High stale RESERVED Several combinations are reserved. Do not use codes other than those | or identfied for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, RESERVED VALIDATE and BYPASS instructions [ ono RESERVED ont L oun Uses BYR Forces contents of the boundary scan cells onto the device 1000 outputs Places the bypass register (BYA) between TDI and TDO Same as above Automateally loaded ino the instruction register whenever the TAP VALIDATE controller passes through the CAPTURE-IR stale. The lower two bits 01" 1101 are mandated by the IEEE sid 11491 specification 1 The BYPASS instruction is used to truncate the boundary scan register BYPASS as a single bit in length mt 6313 bl OF NOTES:

1 Device outputs = All device outputs exceat TOO

2 Device inputs = All device inputs except TDI TMS and TRST

AS8C163631, AS8C 161831, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range 100-Pin Thin Quad Flatpack (TQFP) Package Diagram Outline i | de EVEN LEAD SIDES ODD LEAD SIDES ; TT TARA RAR RAR ARR RRR RAR | TT = = |) _ { —_ oN — oan oom leer LE ; | = 1 NN Ee "Enea fom | \\ ial [= SI SS OETAL_A | = a ae = | = ow == —_ iy = nae | oe Fa ; | +} EBUUBUBUBUEEU BU UERERERUEEE [4 ~~ «GMRiTs “Hk Ba «es — | (Sex) an wad L + [Fa] | | [2 Ak ene a 1 wn | . | | coarser QETAL @ | L LL gran | | awn wads ! PEN ac woe | | DETAIL C i | z LAND PATTERN DIMENSIONS fe CO A A $$ | Terie hepie-T ee ' ss 2) ' [—zn00 a8 F52] — ee nnonnnaneannneeccoocnonnnnone o | | XA = — | =I St Fes —I S 3 re | Ss =] fet a =S S BRESESE SS Te Ee? | NOTES = ——e ) ALL DNENSONING AND TOLERANGNG CONFORM TO ANS Y14 Su- 1962 *T 2S merce we BC SWULER WN gor EUCE BF JS mm _ JO9000000000o00000000000000000 | A ons ava EE] 10 oc orrerweeo at oan rune (ES) — = J | 2 oversons 0 110 € a 10 OF OeToRMD AT ScAING PUNE ; | A. ovensons 01 9 £1 99 nat ncwse wou> enotayson, auowae a SH RAS eubne ae wears [alae tee AX CIS oF pn» mote os crows. Bu UIST BC LATO man He assy ar Ban ates Fart tasop a0] i AS OMENSIN 2 DOrS NOT IGLWEE CAUBAR PROTRUSON, ALDINE cAWEAE a a } or ihe root Cet “ea ] | A caer 5470 oF wor comes sorte | Ax mise onensons appur 70 ME FAT SteTION OF THE LEAD BETWEEN SEBS seats ib | | 1 Bas cata sosoas ro aaes avavewtes 95 spsanroN ve~t38

2.5V VO, Burst Counter, and Pipelined Outputs Commercial Temperature Range Timing Waveform of OE Operation") OE toe touz to.z DATAouT ‘ie ~ Valid =) works 5313 diw 11 TA read operation is assumed to be in progress.

ORDERING INFORMATION

AS8C163631-QC166N | 512K x 36 2,3 -2.6V 100 pin TQFP Comercial: 0 -70C AS8C161831-QC166N 1M x 18 2.3-2.6V 100 pin TQFP Comercial: 0 - 70C 166 PART NUMBERING SYSTEM 01= ZBT Q= 100 Pin TOFP 0~70C 166MHz | N= Leadfree Syne. 16 = 16M 18=x18 | 00= Pipelined SRAM prefix 36= x36 | 25=Flow- Thru | | 31 = ZBT (Pipelined) | | | Alliance Memory, Inc. .

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San Carlos, CA 94070 All Rights Reserved al Sa 510-0500 Part Number: AS8C163631/1831 Document Version: v. 1.0 www.alliancememory.com