AS6WA5128

AS6WA5128 ALSC | Alldatasheet

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Features

• AS6WA5128  Intelliwatt™ active power circuitry  Industrial and commercial temperature ranges available  Organization: 524,288 words × 8 bits  3.0V to 3.6V at 55 ns  Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns  Low power consumption: STANDBY - 72 µW max at 3.6V  1.2V data retention  Equal access and cycle times  Easy memory expansion with CS , OE inputs  Smallest footprint packages - 36(48)-ball FBGA - 32-pin TSOP I and TSOP II packages are available on Alliance AS6UB5128 product family (available January 2001)  ESD protection ≥≥≥≥ 2000 volts  Latch-up current ≥≥≥≥ 200 mA Logic block diagram Sense amp Input bufferA10 A11 A12 A13 A14 A15 A16 I/O1 I/O8 OE CS WE Row decoder Controlcircuit V CC GND Column decoder 512K × 8 Array (4,194,304) 36(48)-CSP BGA Package (shading indicates no ball) 123456 AA 0 A 1 NC A 3 A 6 A 8 BI / O 5 A 2 WE A 4 A 7 I/O1 CI / O 6 NC A 5 I/O2 DV SS V CC EV CC V SS FI / O 7 A 18 A 17 I/O3 GI / O 8 OE CS A 16 A 15 I/O4 HA 9 A 10 A 11 A 12 A 13 A 14 Selection guide Product V CC Range Speed (ns) Power Dissipation Min (V) Typ2 (V) Max (V) Operating (ICC ) Standby (I SB1 ) Max (mA) Max ( µµµµA) AS6W A5128 3.0 3.3 3.6 55 2 20

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The AS6W A5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (t AA , tRC , tWC ) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, the device enters standby mode: the AS6 WA5128 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable ( WE) and chip select (CS) low. Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. The device is available in the JEDEC standard 36(48)-ball FBGA package. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this spec ification is not implied. Expo- sure to absolute maximum rating conditions for extended periods may affect reliability. Truth table Key: X = Don’t care, L = Low, H = High. Parameter Device Symbol Min Max Unit V oltage on VCC relative to VSS V tIN –0.5 V CC + 0.5 V V oltage on any I/O pin relative to GND V tI/O –0.5 V Power dissipation P D –1 . 0 W Storage temperature (plastic) T stg –65 +150 °C Temperature with VCC applied T bias –55 +125 °C DC output current (low) I OUT –2 0 m A CS WE OE Supply Current I/O1–I/O8 Mode HXX I SB High Z Standby (I SB ) LXX I SB High Z Standby (I SB ) LHH I CC High Z Output disable (I CC ) LHL I CC D OUT Read (ICC ) LLX I CC D IN Write (ICC )

10/6/00 ALLIANCE SEMICONDUCTOR 3 Recommended operating condition (over the operating range) Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL) 2 Parameter Description Test Conditions Min Max Unit V OH Output HIGH V oltage I OH = –2.1mA V CC = 3.0V 2.4 V V OL Output LOW V oltage I OL = 2.1mA V CC = 3.0V 0.4 V V IH Input HIGH V oltage V CC = 3.0V 2.2 V CC + 0.5 V V IL Input LOW V oltage V CC = 3.0V –0.5 0.8 V IIX Input Load Current GND < VIN < VCC –1 +1 µA IOZ Output Load Current GND < VO < VCC ; Outputs High Z –1 +1 µA ICC V CC Operating Supply Current CS = VIL, IOUT = 0mA, f = 0, V IN = VIL or VIH V CC = 3.6V 2 mA ICC1 @ 1M H z Average VCC Operating Supply Current at 1 MHz CS < 0.2V , VIN < 0.2V , or VIN > VCC – 0.2V , f = 1 mS V CC = 3.6V 5 mA ICC2 Average VCC Operating Supply Current CS ≠ VIL, VIN = VIL or VIH, f = fMax V CC = 3.6V (55 ns) 40 mA ISB CS Power Down Current; TTL Inputs CS > VIH, other inputs = 0V – VCC V CC = 3.6V 100 µA ISB1 CS Power Down Current; CMOS Inputs CS > VCC – 0.2 V, other inputs = 0V – V CC , f = fMax V CC = 3.6V 20 µA ISBDR Data Retention CS > VCC – 0.1 V, f = 0 V CC = 1.2V 2 µA Parameter Symbol Signals Test conditions Max Unit Input capacitance C IN A, CS , WE , OE V IN = 0V 5 pF I/O capacitance C I/O I/O V IN = VOUT = 0V 7 pF

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Read cycle (over the operating range)3,9 Key to switching waveforms Read waveform 1 (address controlled)3,6,7,9 Read waveform 2 (CS, OE controlled)3,6,8,9 Parameter Symbol Min Max Unit Notes Read cycle time t RC 55 – ns Address access time t AA –5 5 n s 3 Chip select (CS) access time t ACS –5 5 n s 3 Output enable (OE) access time t OE –2 5 n s Output hold from address change t OH 10 – ns 5 CS low to output in low Z t CLZ 10 – ns 4, 5 CS high to output in high Z t CHZ 02 0 n s 4 , 5 OE low to output in low Z t OLZ 5 – ns 4, 5 OE high to output in high Z t OHZ 02 0 n s 4 , 5 Power up time t PU 0 – ns 4, 5 Power down time t PD –5 5 n s 4 , 5 Undefined/don’t careFalling inputRising input tOH tAA tRC tOH D OUT Address Data validPrevious data valid current Supply OE D OUT tOE tOLZ tACE tCHZ tCLZ tPU tPD ICC ISB50% 50% tOHZ Data valid tRC1 CS

10/6/00 ALLIANCE SEMICONDUCTOR 5 Write cycle (over the operating range)11 Write waveform 1 (WE controlled)10,11 Write waveform 2 (CS controlled)10,11 Parameter Symbol Min Max Unit Notes Write cycle time t WC 55 – ns Chip select to write end t CW 40 – ns 12 Address setup to write end t AW 40 – ns Address setup time t AS 0 – ns 12 Write pulse width t WP 35 – ns Address hold from end of write t AH 0– n s Data valid to write end t DW 25 – ns Data hold time t DH 0 – ns 4, 5 Write enable to output in high Z t WZ 02 0 n s 4 , 5 Output active from write end t OW 5 – ns 4, 5 tAW tAH tWC Address WE D OUT tDH tOW tDW tWZ tWP tAS Data validD IN tAW Address CS WE D OUT tCW tWP tDW tDH tAH tWZ tWC tAS Data validD IN

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Data retention characteristics (over the operating range)13,5 Data retention waveform AC test loads and waveforms Notes 1D u r i n g VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions. 4t CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6W E is HIGH for read cycle. 7C S and OE are LOW for read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A. 13 1.2V data retention applies to commercial and industrial temperature range operations. 14 C = 30pF, except at high Z and low Z parameters, where C = 5pF. Parameter Symbol Test conditions Min Max Unit V CC for data retention V DR V CC = 1.2V CS ≥ VCC – 0.1V or V IN ≥ VCC – 0.1V or V IN ≤ 0.1V 1.2V 3.6 V Data retention current I CCDR –4 m A Chip deselect to data retention time tCDR 0– Operation recovery time t R tRC –n s Parameters V CC = 3.0V V CC = 2.5V V CC = 2.0V Unit R1 1105 16670 15294 Ohms R2 1550 15380 11300 Ohms R TH 645 8000 6500 Ohms V TH 1.75V 1.2V 0.85V V olts V CC CS tRtCDR Data retention mode V CC V CCV DR ≥ 1.2V V IH V IH V DR V CC OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) V CC OUTPUT 5 pF ALL INPUT PULSES (b) 10% 90% 10% 90% GND V CC Typ < 5 ns (c) Thevenin equivalent: OUTPUT RTH V INCLUDING JIG AND SCOPE

10/6/00 ALLIANCE SEMICONDUCTOR 7 Typical DC and AC characteristics V CC = VCC typ Supply voltage (V) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized ICC Normalized supply current Supply V oltage (V) 0.0 0.25 0.5 0.75 1.0 Normalized TAA Normalized access time vs. supply voltagevs. supply voltage Ambient temperature (°C) –55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 Normalized ISB2 Normalized standby current vs. ambient temperature Supply voltage (V) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized ISB Normalized standby current vs. supply voltage ISB2 Supply voltage (V) 0.10 0.50 1.0 1.5Normalized ICC Normalized ICC vs. Cycle Time TA = 25° C 3.0 –0.5 V IN = VCC typ 1 5 10 1511 . 9 2.8 3.7 V IN = VCC typ TA = 25° C V IN = 3.6V TA = 25° C V IN = VCC typ TA = 25° C

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Package diagrams and dimensions Minimum Typical Maximum A – 0.75 – B 6.90 7.00 7.10 B1 – 3.75 – C 10.90 11.00 11.10 C1 – 5.25 – D 0.30 0.35 0.40 E–– 1 . 2 0 E1 – 0.68 – E2 0.22 0.25 0.27 Y– – 0 . 0 8 Notes 1. Bump counts: 36(48) (8 row × 6 column). 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are ±0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max). 36(48)-ball FBGA Bottom View Top View 123456 A B C D E F G H A Ball #A1 Ball #A1 index SRAM Die C Elastomer B Side View Detail View E D Die Die E A Y 0.3/Typ

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55 AS6W A5128-BC 48-ball fine pitch BGA Commercial

55 AS6W A5128-BI 48-ball fine pitch BGA Industrial

AS6W A 5128 T, ST, HF, HR, B C, I SRAM Intelliwatt™ prefix Device number Package: B: CSP BGA Temperature range: C: Commercial: 0° C to 70° C I: Industrial: –40°C to 85° C