AS6VA25616

AS6VA25616 ALSC | Alldatasheet

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Features

• AS6VA25616  Intelliwatt™ active power circuitry  Industrial and commercial temperature ranges available  Organization: 262,144 words × 16 bits  2.7V to 3.3V at 55 ns  Low power consumption: ACTIVE - 132 mW at 3.3V and 55 ns  Low power consumption: STANDBY - 66 µW max at 3.3V  1.2V data retention  Equal access and cycle times  Easy memory expansion with CS, OE inputs  Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II  ESD protection ≥ 2000 volts  Latch-up current ≥ 200 mA Logic block diagram 256K × 16 Array (4,194,304) OE CS WE Column decoder Row Decoder A0A1 V CC V SS A12 A10 A11 A14 A15 A16 A17 A13 Control circuitI/O1–I/O8 I/O9–I/O16 UB LB I/O buffer Pin arrangement (top view) 48-CSP Ball-Grid-Array Package 123456 AL B OE A0 A1 A2 NC BI / O 9 U B A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 DV SS I/O12 A17 A7 I/O4 V CC EV CC I/O13 NC A16 I/O5 V SS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 HN C A 8 A 9 A 1 0 A 1 1 N C I/O14 I/O13 V SSV CCI/O12 I/O11 I/O10 I/O9 NC A10 A11 A12 CS I/O1 I/O2 I/O3 I/O4V CC V SSI/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 44-pin 400-mil TSOP II A14 A13 UB LBI/O16 I/O15 2A3 3A2 4A1 1A4 OE Selection guide Product V CC Range Speed (ns) Power Dissipation Min (V) Typ2 (V) Max (V) Operating (ICC ) Standby (I SB1 ) Max (mA) Max ( µA) AS6V A25616 2.7 3.0 3.3 55 2 20

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The AS6V A25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA , tRC , tWC ) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6V A25616 is guaranteed not to exceed 66 µW power consumption at 3.3V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the JEDEC standard 400-mm, TSOP II, and 48-ball FBGA packages. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table Key: X = Don’t care, L = Low, H = High. Parameter Device Symbol Min Max Unit V oltage on VCC relative to VSS V tIN –0.5 V CC + 0.5 V V oltage on any I/O pin relative to GND V tI/O –0.5 V Power dissipation P D –1 . 0 W Storage temperature (plastic) T stg –65 +150 oC Temperature with VCC applied T bias –55 +125 oC DC output current (low) I OUT –2 0 m A CS WE OE LB UB Supply Current I/O1–I/O8 I/O9–I/O16 Mode HXXXX ISB High Z High Z Standby (I SB ) LXXHH LHHXX I CC High Z High Z Output disable (I CC ) LHL LH ICC D OUT High Z Read (ICC )H L High Z D OUT LL D OUT D OUT LLX LH ICC D IN High Z Write (ICC )H L High Z D IN LL D IN D IN

10/6/00 ALLIANCE SEMICONDUCTOR 3 Recommended operating condition (over the operating range) Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL) 2 Parameter Description Test Conditions Min Max Unit V OH Output HIGH V oltage I OH = –2.1mA V CC = 2.7V 2.4 V V OL Output LOW V oltage I OL = 2.1mA V CC = 2.7V 0.4 V V IH Input HIGH V oltage V CC = 2.7V 2.2 V CC + 0.5 V V IL Input LOW V oltage V CC = 2.7V –0.5 0.8 V IIX Input Load Current GND < VIN < VCC –1 +1 µA IOZ Output Load Current GND < VO < VCC; Outputs High Z –1 +1 µA ICC V CC Operating Supply Current CS = VIL, V IN = VIL or VIH, IOUT = 0mA, f = 0 V CC = 3.3V 2 mA ICC1 @ 1M H z Average VCC Operating Supply Current at 1 MHz CS < 0.2V , VIN < 0.2V or VIN > VCC – 0.2V , f = 1 mS V CC = 3.3V 5 mA ICC2 Average VCC Operating Supply Current CS ≠ VIL, VIN = VIL or V IH, f = fMax V CC = 3.3V (55 ns) 40 mA ISB CS Power Down Current; TTL Inputs CS > VIH or UB = LB > VIH, other inputs = V IL or VIH, f = 0 V CC = 3.3V 100 µA ISB1 CS Power Down Current; CMOS Inputs CS > VCC – 0.2V or UB = LB > VCC – 0.2 V, other inputs = 0V – V CC , f = fMax V CC = 3.3V 20 µA ISBDR Data Retention CS > VCC – 0.1 V, UB = LB = VCC – 0.1V f = 0 V CC = 1.2V 2 µA Parameter Symbol Signals Test conditions Max Unit Input capacitance C IN A, CS, WE, OE, LB, UB V IN = 0V 5 pF I/O capacitance C I/O I/O V IN = VOUT = 0V 7 pF

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Read cycle (over the operating range)3,9 Shaded areas indicate preliminary information. Key to switching waveforms Read waveform 1 (address controlled)3,6,7,9 Read waveform 2 (CS, OE, UB, LB controlled)3,6,8,9 Parameter Symbol Min Max Unit Notes Read cycle time t RC 55 – ns Address access time t AA –5 5 n s 3 Chip select (CS ) access time t ACS –5 5 n s 3 Output enable (OE ) access time t OE –2 5 n s Output hold from address change t OH 10 – ns 5 CS low to output in low Z t CLZ 10 – ns 4, 5 CS high to output in high Z t CHZ 02 0 n s 4 , 5 OE low to output in low Z t OLZ 5 – ns 4, 5 UB /LB access time t BA –5 5 n s UB /LB low to low Z t BLZ 10 – ns 4, 5 UB /LB high to high Z t BHZ 02 0 n s 4 , 5 OE high to output in high Z t OHZ 02 0 n s 4 , 5 Power up time t PU 0 – ns 4, 5 Power down time t PD –5 5 n s 4 , 5 Undefined/don’t careFalling inputRising input tOH tAA tRC tOH D OUT Address Data validPrevious data valid Data valid tRC tAA tBLZ tBA tOE tOLZ tOH tOHZ tHZ tBHZ tACS tLZ Address OE CS LB , UB D OUT

10/6/00 ALLIANCE SEMICONDUCTOR 5 Write cycle (over the operating range)11 Shaded areas indicate preliminary information. Write waveform 1 (WE controlled)10,11 Write waveform 2 (CS controlled)10,11 Parameter Symbol Min Max Unit Notes Write cycle time tWC 55 – ns Chip select to write end tCW 40 – ns 12 Address setup to write end tAW 40 – ns Address setup time tAS 0 – ns 12 Write pulse width tWP 35 – ns Address hold from end of write tAH 0– n s Data valid to write end tDW 25 – ns Data hold time tDH 0– n s 4 , 5 Write enable to output in high Z tWZ 02 0 n s 4 , 5 Output active from write end tOW 5– n s 4 , 5 UB /LB low to end of write tBW 35 – ns Address CS LB , UB WE D IN D OUT tWC tCW tBW tAWtAS tWP tDW tDH tOW tWZ tAH Data undefined High Z Data valid Address CS LB , UB WE D IN tWC tCW tBW tWP tDW tDH tOW tWZ tAH D OUT Data undefinedHigh Z High Z tAS tAW Data validtCLZ

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Data retention characteristics (over the operating range)13,5 Data retention waveform AC test loads and waveforms Notes 1D u r i n g VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions. 4t CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6W E is HIGH for read cycle. 7C S and OE are LOW for read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A. 13 1.2V data retention applies to commercial and industrial temperature range operations. 14 C = 30pF, except at high Z and low Z parameters, where C = 5pF. Parameter Symbol Test conditions Min Max Unit V CC for data retention V DR V CC = 1.2V CS ≥ VCC – 0.1V or UB = LB = > VCC – 0.1V V IN ≥ VCC – 0.1V or V IN ≤ 0.1V 1.2V 3.3 V Data retention current I CCDR –4 m A Chip deselect to data retention time tCDR 0– n s Operation recovery time t R tRC – ns Parameters V CC = 3.0V V CC = 2.5V V CC = 2.0V Unit R1 1105 16670 15294 Ohms R2 1550 15380 11300 Ohms R TH 645 8000 6500 Ohms V TH 1.75V 1.2V 0.85V V olts V CC CS tRtCDR Data retention mode V CC V CCV DR ≥ 1.2V V IH V IH V DR V CC OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) V CC OUTPUT 5 pF ALL INPUT PULSES (b) 10% 90% 10% 90% GND V CC Typ < 5 ns (c) Thevenin equivalent: OUTPUT RTH V INCLUDING JIG AND SCOPE

10/6/00 ALLIANCE SEMICONDUCTOR 7 Typical DC and AC characteristics Package diagrams and dimensions Supply voltage (V) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized ICC Normalized supply current Supply Voltage (V) 0.0 0.25 0.5 0.75 1.0 Normalized TAA Normalized access time vs. supply voltagevs. supply voltage Ambient temperature (°C) –55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 Normalized ISB2 Normalized standby current vs. ambient temperature V CC = VCC typ Supply voltage (V) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized ISB Normalized standby current vs. supply voltage ISB2 Supply voltage (V) 0.10 0.50 1.0 1.5Normalized ICC Normalized ICC vs. Cycle Time TA = 25° C 3.0 –0.5 V IN = VCC typ 1 5 10 1511 . 9 2.8 3.7 V IN = VCC typ TA = 25° C V IN = VCC typ TA = 25° C V CC = 3.3V TA = 25° C 44-pin TSOP II Min (mm) Max (mm) A1 . 2 A 1 0.05 A 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 18.28 18.54 e 10.06 10.26 H e 11.56 11.96 E 0.80 (typical) l 0.40 0.60 d H e 1234567891 0 1 1 1 2 1 3 1 4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l A 1 A 2 E 44-pin TSOP II 0–5° e A b

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A – 0.75 – B 6.90 7.00 7.10 B1 – 3.75 – C 10.90 11 11.10 C1 – 5.25 – D 0.30 0.35 0.40 E–– 1 . 2 0 E1 – 0.68 – E2 0.22 0.25 0.27 Y–– 0 . 0 8 Notes 1. Bump counts: 48 (8 row × 6 column). 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are ±0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max). 65 4 32 1 48-ball FBGA Bottom View Top View A B C D E F G H Ball #A1 Ball #A1 Index A A B1 B Elastomer CSRAM Die Side View Detail View DieDie A E Y 0.3/TypE1 E E2 D

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