AS6UA51216 ALSC | Alldatasheet

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Technical content

Features

  • AS6UA51216
  • Intelliwatt™ active power circuitry
  • Industrial and commercial temperature ranges available
  • Organization: 524,288 words × 16 bits
  • 2.7V to 3.6V at 55 ns
  • 2.3V to 2.7V at 70 ns
  • 1.65V to 2.3V at 100 ns
  • Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns - 68 mW at 2.7V and 70 ns - 28 mW at 2.3 V and 100 ns
  • Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V - 28 µW max at 2.3V
  • 1.2V data retention
  • Equal access and cycle times
  • Easy memory expansion with CS , OE inputs
  • Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II
  • ESD protection ≥ 2000 volts
  • Latch-up current ≥ 200 mA Logic block diagram 512K × 16 Array (8,388,608) OE CS WE Column decoder Row Decoder A0A1 VDD VSS A12 A10 A11 A14 A15 A16 A17 A13 Control circuitI/O1–I/O8 I/O9–I/O16 UB LB I/O buffer A18 Pin arrangement (top view) 48-CSP Ball-Grid-Array Package 123456 AL B OE A0 A1 A2 NC BI / O 9 U B A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 DV SS I/O12 A17 A7 I/O4 V CC EV CC I/O13 V SS A16 I/O5 V SS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H A18 A8 A9 A10 A11 NC 1011 1213 1415 1617 1819 I/O14 I/O13V SSVCCI/O12 I/O11 I/O10 I/O9A8 A9A10 A11A12 A13 CS I/O1 I/O2I/O3 I/O4V CCVSSI/O5 I/O6I/O7I/O8WEA18 A17A16 44-pin 400-mil TSOP II 22A15A14 UB LBI/O16 I/O15 2A3 3A2 4A1 1A4 4039 3736 3534 3332 3130 2928 2726 2423 4241 44 A6 A7OE Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12, shorted. The bonding of this pad to VCC or VSS configures the device. There should only be 44+2+2 pads on the chip. T wo extra VCC to separate out Array from Peripheral and T wo-Mode Pads. Selection guide Product VCC Range Speed (ns) Power Dissipation Min (V) Typ2 (V) Max (V) Operating (ICC1)S t a n d b y ( I SB2) Max (mA) Max ( µA) AS6UA51216 2.7 3.0 3.6 55 2 20 AS6UA51216 2.3 2.5 2.7 70 1 15 AS6UA51216 1.65 2.0 2.3 100 1 12

2 ALLIANCE SEMICONDUCTOR 6/27/00

The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low . Data on the input pins I/O1– O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE ), chip enable (CS), UB and LB low , with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC standard 400-mL, TSOP II, and 48-ball FBGA packages. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilit y. Truth table Key: X = Don’t care, L = Low, H = High. Parameter Device Symbol Min Max Unit Voltage on VCC relative to VSS VtIN –0.5 V CC + 0.5 V Voltage on any I/O pin relative to GND V tI/O –0.5 V Power dissipation P D –1 . 0 W Storage temperature (plastic) T stg –65 +150 °C Temperature with VCC applied T bias –55 +125 °C DC output current (low) I OUT –2 0 m A CS WE OE LB UB Supply Current I/O1–I/O8 I/O9–I/O16 Mode HXXXX ISB High Z High Z Standby (I SB)LXX H H LHHXX I CC High Z High Z Output disable (I CC) LHL LH ICC DOUT High Z Read (ICC)HL H i g h Z D OUT LL D OUT DOUT LLX LH ICC DIN High Z Write (ICC)HL H i g h Z D IN LL D IN DIN

6/27/00 ALLIANCE SEMICONDUCTOR 3 Recommended operating condition (over the operating range) Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)□ Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = –2.1mA V CC = 2.7V 2.4 VIOH = –0.5mA V CC = 2.3V 2.0 IOH = –0.1mA V CC = 1.65V 1.5 VOL Output LOW Voltage IOL = 2.1mA V CC = 2.7V 0.4 VIOL = 0.5mA V CC = 2.3V 0.4 IOL = 0.1mA V CC = 1.65V 0.2 VIH Input HIGH Voltage VCC = 2.7V 2.2 V CC + 0.5 VVCC = 2.3V 2.0 V CC + 0.3 VCC = 1.65V 1.4 V CC + 0.3 VIL Input LOW V oltage VVCC = 2.3V –0.3 0.6 VCC = 1.65V –0.3 0.4 IIX Input Load Current GND < VIN < VCC –1 +1 µA IOZ Output Load Current GND < VO < VCC; Outputs High Z –1 +1 µA ICC VCC Operating Supply Current CS = VIL, VIN = VIL or VIH, IOUT = 0mA, f = 0 VCC = 3.6V 2 mAVCC = 2.7V 1 VCC = 2.3V 1 ICC1 @ 1M H z Average VCC Operating Supply Current at 1 MHz CS < 0.2V , VIN < 0.2V or VIN > VCC – 0.2V , f = 1 mS VCC = 3.6V 4 mAVCC = 2.7V 2 VCC = 2.3V 2 ICC2 Average VCC Operating Supply Current CS ≠ VIL, VIN = VIL or VIH, f = fMax VCC = 3.6V (55/70/100 mS) 40/30/20 mAVCC = 2.7V (55/70/100 mS) 30/25/15 VCC = 2.3V(55/70/100 mS) 25/10/12 ISB CS Power Down Current; TTL Inputs CS > VIH or UB = LB > VIH, other inputs = VIL or VIH, f = 0 VCC = 3.6V 100 µAVCC = 2.7V 100 VCC = 2.3V 100 ISB1 CS Power Down Current; CMOS Inputs CS > VCC – 0.2V or UB = LB > VCC – 0.2V other inputs = 0V – VCC, f = fMax VCC = 3.6V 20 µAVCC = 2.7V 15 VCC = 2.3V 12 ISBDR Data Retention CS > VCC – 0.1 V, UB = LB = VCC – 0.1V f = 0 VCC = 1.2V 2 µA Parameter Symbol Signals Test conditions Max Unit Input capacitance C IN A, CS, WE, OE, LB, UB VIN = 0V 5 pF I/O capacitance C I/O I/O V IN = VOUT = 0V 7 pF

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Read cycle (over the operating range)□□□ Shaded areas indicate preliminary information. Key to switching waveforms Read waveform 1 (address controlled)□□□□□□□ Read waveform 2 (CS, OE, UB, LB controlled)□□□□□□□ Parameter Symbol –55 –70 –100 Unit NotesMin Max Min Max Min Max Read cycle time tRC 55 – 70 – 100 – ns Address access time tAA – 55 – 70 – 100 ns 3 Chip enable (CS) access time tACS – 55 – 70 – 100 ns 3 Output enable (OE) access time tOE –2 5–3 5–5 0 n s Output hold from address change tOH 10 – 10 – 15 – ns 5 CS □□□ □o output in low Z tCLZ 10 – 10 – 10 – ns 4, 5 CS high to output in high Z tCHZ 02 002 002 0 n s 4 , 5 OE low to output in low Z tOLZ 5–5–5– n s 4 , 5 UB/LB access time tBA – 55 – 70 – 100 ns UB/LB low to low Z tBLZ 10 – 10 – 10 – ns 4, 5 UB/LB high to high Z tBHZ 02 002 002 0 n s 4 , 5 OE high to output in high Z tOHZ 02 002 002 0 n s 4 , 5 Power up time tPU 0–0–0– n s 4 , 5 Power down time tPD – 55 – 70 – 100 ns 4, 5 Undefined/don’t careFalling inputRising input tOH tAA tRC tOH DOUT Address Data validPrevious data valid Data valid tRC tAA tBLZ tBA tOE tOLZ tOH tOHZ tHZ tBHZ tACS tLZ Address OE CS LB, UB DOUT

6/27/00 ALLIANCE SEMICONDUCTOR 5 Write cycle (over the operating range)□□ Shaded areas indicate preliminary information. Write waveform 1 (WE controlled)□□□□□ Write waveform 2 (CS controlled)□□□□□ Parameter Symbol –55 –70 –100 Unit NotesMin Max Min Max Min Max Write cycle time tWC 55 – 70 – 100 – ns Chip enable to write end tCW 40 – 60 – 80 – ns 12 Address setup to write end tAW 40 – 60 – 80 – ns Address setup time tAS 0–0–0– n s 1 2 Write pulse width tWP 35 – 55 – 70 – ns Address hold from end of write tAH 0–0–0– n s Data valid to write end tDW 25 – 30 – 40 – ns Data hold time tDH 0–0–0– n s 4 , 5 Write enable to output in high Z tWZ 02 002 002 0 n s 4 , 5 Output active from write end tOW 5–5–5– n s 4 , 5 UB/LB low to end of write tBW 35 – 55 – 70 – ns Address CS LB, UB WE DIN DOUT tWC tCW tBW tAWtAS tWP tDW tDH tOW tWZ tAH Data undefined High Z Data valid Address CS LB, UB WE DIN tWC tCW tBW tWP tDW tDH tOW tWZ tAH DOUT Data undefinedHigh Z High Z tAS tAW Data validtCLZ

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Data retention characteristics (over the operating range)□□□□ Data retention waveform AC test loads and waveforms Notes 1D u r i n g VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC T est Conditions. 4t CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6W E is HIGH for read cycle. 7C S and OE are LOW for read cycle. 8 Address valid prior to or coincident with CS transition LOW . 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 N/A. 13 1.2V data retention applies to commercial and industrial temperature range operations. 14 C = 30pF, except at high Z and low Z parameters, where C = 5pF. Parameter Symbol Test conditions Min Max Unit VCC for data retention V DR VCC = 1.2V CS ≥ VCC – 0.1V or UB = LB = > VCC – 0.1V VIN ≥ VCC – 0.1V or VIN ≤ 0.1V 1.2V 3.6 V Data retention current I CCDR –2 m A Chip deselect to data retention time t CDR 0– n s Operation recovery time t R tRC –n s Parameters V CC = 3.0V V CC = 2.5V V CC = 2.0V Unit R1 1105 16670 15294 Ohms R2 1550 15380 11300 Ohms R TH 645 8000 6500 Ohms VTH 1.75V 1.2V 0.85V V olts VCC CS tRtCDR Data retention mode VCC VCCVDR ≥ 1.2V VIH VIH VDR VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) VCC OUTPUT 5 pF ALL INPUT PULSES (b) 10% 90% 10% 90% GND VCC Typ < 5 ns (c) Thevenin equivalent: OUTPUT RTH V INCLUDING JIG AND SCOPE

6/27/00 ALLIANCE SEMICONDUCTOR 7 Typical DC and AC characteristics Package diagrams and dimensions Supply voltage (V) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized I CC Normalized supply current Supply V oltage (V) 0.0 0.25 0.5 0.75 1.0 Normalized TAA Normalized access time vs. supply voltagevs. supply voltage Ambient temperature (°C) -55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 Normalized I SB2 Normalized standby current vs. ambient temperature VCC = VCC typ Supply voltage (V) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 Normalized I SB Normalized standby current vs. supply voltage ISB2 Supply voltage (V) 0.10 0.50 1.0 1.5Normalized I CC Normalized I CC vs. cycle time TA = 25° C 3.0 -0.5 VIN = VCC typ 1 5 10 1511 . 9 2.8 3.7 VIN = VCC typ TA = 25° C VIN = VCC typ TA = 25° C VCC = 3.6V TA = 25° C 44-pin TSOP II Min (mm) Max (mm) A1 . 2 A1 0.05 A2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 20.85 21.05 e 10.06 10.26 He 11.56 11.96 E 0.80 (typical) l 0.40 0.60 d He 1 2 3 4 5 6 7 8 9 10 11 12 13 14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l E 44-pin TSOP II 0–5° e A b

8 ALLIANCE SEMICONDUCTOR 6/27/00

A – 0.75 – B 6.90 7.00 7.10 B1 – 3.75 – C 8.4 8.5 8.6 C1 – 5.25 – D 0.30 0.35 0.40 E–– 1 . 2 0 E1 – 0.68 – E2 0.22 0.25 0.27 Y–– 0 . 0 8 Notes 1. Bump counts: 48 (8 row × 6 column). 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are ± 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max). 65 432 1 48-ball FBGA Bottom View Top View A B C D E F G H Ball #A1 Ball #A1 Index A A B1 B Elastomer C SRAM Die Side View Detail View DieDie A E Y 0.3/TypΕ1 Ε Ε2 D

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