AS6C8016-55TIN

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Rev. 1.0 Initial Issue November12.2015 Revision History List 512K x 16 bit -AS6C8016-55TIN - 48-pin TSOP I PACKAGE AS6C8016-55TIN Confidential -1/11- Rev.1.0 Nov 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice

FEATURES

n Fast access time : 55ns n Low power consumption: Operating current : 30/20mA (TYP.) Standby current : 1.5µA (TYP.) S L-version n Single 2.7V ~ 3.6V power supply n All inputs and outputs TTL compatible n Fully static operation n Tri-state output n Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) n Data retention voltage : 1.2V (MIN.) n Package : 48-pin 12mm x 20mm TSOP-I n Green & ROHS Compliant GENERAL DESCRIPTION The AS6C8016-55TIN is a 8,388,608-bit low power CMOS static random access memory organized as 524,288 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C8016-55TIN is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C8016-55TIN operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible FUNCTIONAL BLOCK DIAGRAM CONTROL CIRCUIT DECODER 512Kx16 MEMORY ARRAY COLUMN I/O A0-A18 Vcc Vss DQ8-DQ15 Upper Byte DQ0-DQ7 Lower Byte I/O DATA CIRCUIT CE2 WE# OE# LB# UB# CE# PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ15 Data Inputs/Outputs CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground PRODUCT FAMILY Product Family Operating Temperatur e Vcc Range Speed Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) AS6C8016-55TIN -40℃ ~ 85℃ 2.7 ~ 3.6V 55ns 1.5µA(SL) 30/20mA AS6C8016-55TIN Confidential -2/11- Rev.1.0 Nov 2015

WE# CE2 NC UB# LB# A18 A17 DQ13 NC DQ15 DQ7 DQ14 DQ6 A16 Vss DQ12 DQ5 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ1 DQ9 DQ8 DQ0 OE# Vss CE# ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 4.6 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature TA 0 to 70(C grade) ℃-40 to 85(I grade) Storage Temperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. AS6C8016-55TIN Confidential -3/11- Rev.1.0 Nov.2015

MODE CE# CE2 OE# WE# LB# UB# I/O OPERATION SUPPLY CURRENTDQ0-DQ7 DQ8-DQ15 Standby H X X X L X X X X X X X X X H X X H High – Z High – Z High – Z High – Z High – Z High – Z ISB,ISB1 Output Disable L L H H H H H H L X X L High – Z High – Z High – Z High – Z ICC,ICC1 Read L L L H H H L L L H H H L H L H L L DOUT High – Z DOUT High – Z DOUT DOUT ICC,ICC1 Write L L L H H H X X X L L L L H L H L L DIN High – Z DIN High – Z DIN DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Supply Voltage VCC 2.7 3.0 3.6 V Input High Voltage VIH 2.2 - VCC+0.3 V Input Low Voltage VIL - 0.2 - 0.6 V Input Leakage Current ILI VCC VIN VSS - 1 - 1 µA Output Leakage Current ILO VCC VOUT VSS, Output Disabled - 1 - 1 µA Output High Voltage VOH IOH = -1mA 2.2 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V Average Operating Power supply Current ICC Cycle time = Min. CE# = VIL and CE2 = VIH II/O = 0mA Other pins at VIL or VIH - 55 - 30 40 mA - 70 - 20 30 mA ICC1 Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or V CC-0.2V - 4 8 mA Standby Power Supply Current ISB CE# = VIH or CE2 = VIL Other pins at VIL or VIH - 0.15 1 mA ISB1 CE# VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V SLI *5 25℃ - 1.5 5 µA 40℃ - 1.5 5 µA SLI - 1.5 20 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V AS6C8016-55TIN Confidential -4/11- Rev.1.0 Nov.2015

CAPACITANCE (TA = 25, f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. AS6C8016-55TIN UNIT MIN. MAX. Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time tOE - 30 ns Chip Enable to Output in Low -Z tCLZ* 10 - ns Output Enable to Output in Low -Z tOLZ* 5 - ns Chip Disable to Output in High -Z tCHZ* - 20 ns Output Disable to Output in High -Z tOHZ* - 20 ns Output Hold from Address Change tOH 10 - ns LB#, UB# Access Time tBA - 55 ns LB#, UB# to High-Z Output tBHZ* - 25 ns LB#, UB# to Low-Z Output tBLZ* 10 - ns (2) WRITE CYCLE PARAMETER SYM. AS6C8016-55TIN UNIT MIN. MAX. Write Cycle Time tWC 55 - ns Address Valid to End of Write tAW 50 - ns Chip Enable to End of Write tCW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap tDW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns LB#, UB# Valid to End of Write tBW 45 - ns *These parameters are guaranteed by device characterization, but not production tested. AS6C8016-55TIN Confidential -5/11- Rev.1.0 Nov 2015

READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Dout Data Valid High-ZHigh-Z tCLZ tOLZ tCHZ tOHZ tOH OE# tOE LB#,UB# tBHZ tACE tBA tBLZ CE# tAA Address tRC CE2 Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. AS6C8016-55TIN Confidential -6/11- Rev.1.0 Nov.2015

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) TOW LB#,UB# tBW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW tWP tBW CE# Address tWRtAS tAW tWC CE2 AS6C8016-55TIN Confidential -7/11- Rev.1.0 Nov.2015

WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCWtAS tWP tBW CE# Address tWRtAW tWC CE2 Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. AS6C8016-55TIN Confidential -8/11 Rev.1.0 Nov.2015

DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR CE# VCC - 0.2V or CE2≦0.2V 1.2 - 3.6 V Data Retention Current IDR VCC = 1.2V CE# VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V SLI 25℃ - 1 3 µA 40℃ - 1 3 µA SLI - 1 20 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ¡Ù 1.2V CE# ¡Ù V cc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR ¡Ù 1.2V CE2 ¡Ø 0.2V Vcc(min.) VIL tRtCDR VIL Vcc(min.) Low Vcc Data Retention Waveform ( 3) (LB#, UB# controlled) Vcc LB#,UB# VDR ¡Ù 1.2V LB#,UB# ¡Ù Vcc -0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) AS6C8016-55TIN Confidential -9/11- Rev.1.0 Nov 2015

48-pin 12mm x 20mm TSOP-I Package Outline Dimension AS6C8016-55TIN Confidential -10/11- Rev.1.0 Nov 2015

Alliance Memory, Inc.

511 Taylor Way,

San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. PART NUMBERING SYSTEM

55 T I N

SRAM 8M=512K x 16 Speed=55 ns T = 48pin TSOP I I=Industrial (-40°C85°C) Indicates Pb and Halogen Free AS6C 8016 AS6C8016-55TIN Confidential -11/11- Rev.1.0 Nov 2015