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FEATURES

Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP .) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Lead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA GENERAL DESCRIPTION The AS6C8008 is a 8,388,608-bit low power CMOS static random access memory organized as 1,048,576 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C8008 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The A S6C8008 operates fr om a sin gle pow er supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby(ISB1,TYP.) Operating(Icc,TYP .) AS6C8008(I) -40 ~ 85℃ 2.7 ~ 5.5V 55ns 6µA(LL) 30mA FUNCTIONAL BLOCK DIAGRAM DECODER I/O DATA CIRCUIT CONTROL CIRCUIT 1024K x8 MEMORY ARRAY COLUMN I/O A0-A19 Vcc Vss DQ0-DQ7 CE# WE# OE# CE2 PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Conne ction 512KX8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 1 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

CE# WE# CE2 OE TFBGA NCNC A10 A9 A11 A14 A8 A19 WE DQ DQ NC A18 Vss CE2 A13 NC Vcc Vcc A15 Vss CE NC DQ DQ NC A2OE# A1 A6 A5 A4NC 1 2 3 4 5 6 H G C D E F A B A12 NC A17 A7 A16 NC DQ DQ NC NC DQ6 DQ5 NC 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 2 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 6.5 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) ℃ Storage Temperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260 ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# CE2 OE# WE# I/O OPERATION S UPPLY CUR RENT H X X X High-Z ISB1 Standby X L X X High-Z ISB1 Output Disable L H H H High-Z ICC,ICC1 Read L H L H DOUT ICC,ICC1 Write L H X L DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . *4 MAX. UNIT Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage V IH Input Low Voltage V IL *2 - 0.2 - 0.6 V Input Leakage Current I LI V CC VIN VSS - 1 - 1 µA Output Leakage Current ILO VCC VOUT VSS Output Disabled - 1 - 1 µA Output High Voltage V OH I OH = -1mA 2.4 2.7 - V Output Low Voltage V OL I OL = 2mA - - 0.4 V - 55 - 30 60 mAICC Cycle time = Min. CE# = VIL and CE2 = VIH II/O = 0mA Other pins at VIL or VIHAverage Operating Power supply Current ICC1 Cycle time = 1µs CE#≦0.2V and CE2≧ VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V - 4 12 m A Standby Power Supply Current ISB1 CE# V CC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V - 6 50 µA 512KX8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 3 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns. Over/Undershoot specifications are characterized, not 100% tested. Typical values are included for reference only and are not guaranteed or tested. T ypical valued are measured at VCC = VCC(TYP.) and TA = 25℃ ?CAPACITANCE (TA = 25 , f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE AS 6C8008PARAMETER SY M. SY UNIT Read Cycle Time tRC Address Access Time tAA Chip Enable Access Time tACE Output Enable Access Time t OE Chip Enable to Output in Low-Z t CLZ Output Enable to Output in Low-Z t OLZ Chip Disable to Output in High-Z t CHZ Output Disable to Output in High-Z t OHZ Output Hold from Address Change t OH (2) WRITE CYCLE AS 6C8008 UNITPARAMETER Write Cycle Time tWC Address Valid to End of Write t AW Chip Enable to End of Write t CW Address Set-up Time tAS Write Pulse Width tWP Write Recovery Time tWR Data to Write Time Overlap t DW Data Hold from End of Write Time t DH Output Active from End of Write t OW Write to Output in High-Z tWHZ *These parameters are guaranteed by device characterization, but not production tested. 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 4 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Dout Data Valid tOH OE# High-ZHigh-Z tCLZ tOLZ tOE tCHZ tOHZ CE2 tACE CE# tAA Address tRC Notes : WE# is high for read cycle. Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 5 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Di n Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) T OW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) Dout Di n Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW CE# tWRtAS tAW Address tWC CE2 Notes : WE#, CE# must be high or CE2 must be low during all address transitions. A write occurs during the overlap of a low CE#, high CE2, low WE#. During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be pl aced on the bus. During this period, I/O pins are in the output state, and input signals must not be applied. If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high im pedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 6 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

DATA RETENTION CHARAC TERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . MAX. UNIT VCC for Data Retention V DR CE# V CC - 0.2V or CE2 0.2V 1.5 - 5.5 V Data Retention Current I DR VCC = 1.5V CE# V CC - 0.2V or CE2 0.2V Other pins at 0.2V or VCC - 0.2V - 4 50 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR 1.5V CE# Vcc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR 1.5V CE2 0.2V Vcc(min.) VIL tRtCDR VIL Vcc(min.) 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 7 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

44-pin 400mil TSOP-II Package Outline Dimension θ b 0.30 - 0.45 11.8 - 17 .7 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 y - - 0.076 - - 3 Θ 0 o 3 o 6 o 0 o 3 o 6 o 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 8 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

48-ball 6mm × 8mm TFBGA Package Outline Dimension 512K X 8 BIT LOW POWER CMOS SRAM January 2007JANUARY 2008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 9 of 11 AS6C8008 1024K X 8 BIT SUPER LOW POWER CMOS SRAM

ORDERING INFORMATION

512K X 8 BIT LOW POWER CMOS SRAM January 2007 1024K X 8 BIT LOW POWER CMOS SRAM JANUARY 2008 AS6C8008 JANUAR/2008, V 1.0 Alliance Memory Inc. Page 10 of 11 Alliance Organization VCC Range Package Operating Temp Speed ns AS6C8008-55ZIN 1024K x 8 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C8008-55BIN 1024K x 8 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C 8008 -55 X X N Device Number Package Option Temperature Range 380 =8M Z - 44pin TSOP I = Industriallow power S RAM prefix 08 = x8 Access Tim e B = 48ball TFBGA (-40 to + 85 C) N = Lead Free RoH S compliant part

512K X 8 BIT LOW POWER CMOS SRAM January 2007 1024K X 8 BIT LOW POWER CMOS SRAM JANUARY 2008 AS6C8008 JANUARY/2008, V 1.0 Alliance Memory Inc. Page 11 of 11 Copyright © Alliance Memory All Rights Reserved Alliance Memory, Inc

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