AS6C6264-55SIN

AS6C6264_V01 ALSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 13

Technical content

8K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc. reserves the rights to change the specifications and products without notice. Alliance Memory, Inc., 511 Taylor Way, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 AS6C6264

REVISION HISTORY

1.0 Feb 2007

2.0

Description

Add-in industrial temperature option for 28-pin 600 mil PDIP. Standby current(Isb1) reduced to be 20uA for I-grade and 10uA for C grade July 2017

FEATURES

Access time :55ns Low power consumption: Operation current : 15mA (TYP .), VCC = 3.0V Standby current : 1µA (TYP .), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully static operation Tri-state output Data retention voltage :1.5V (MIN.) All products ROHS Compliant Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mm x 13.4mm sTSOP GENERAL DESCRIPTION The AS6C6264 is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C6264 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C6264 operates with wide range power supply. FUNCTIONAL BLOCK DIAGRAM DECODER I/O DATA CIRCUIT CONTROL CIRCUIT 8Kx8 MEMORY ARRAY COLUMN I/O A0-A12 Vcc Vss DQ0-DQ7 CE# WE# OE# CE2 PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A12 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection 8K X 8 BIT LOW POWER CMOS SRAM Fully Compatible with all Competitors 5V product Fully Compatible with all Competitors 3.3V product All inputs and outputs TTL compatible February 2007 Updated July 2017 AS6C6264 July 2017, v2.0 Alliance Memory Inc Page 1 of 12

8K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A12 DQ0 DQ1 DQ2 Vss NC Vcc A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 AS6C6264 PDIP/SOP CE2 CE# OE# WE# sTSOP DQ3 A11 CE2 DQ2 A10 NC A12 Vcc DQ7 DQ6 DQ5 DQ4 Vss DQ1 DQ0 AS6C6264 OE# WE# CE# ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Terminal Voltage with Respect to VSS VTERM -0.5 to 7.0 V 0 to 70(C grade) T e r u t a r e p m e T g n i t a r e p OA -40 to 85(I grade) ºC T e r u t a r e p m e T e g a r o t SSTG -65 to 150 ºC P n o i t a p i s s i D r e w o PD 1 W I t n e r r u C t u p t u O C DOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260 ºC *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# CE2 OE# WE# I/O OPERATION SUPPLY CURRENT H X X X High-Z ISB,ISB1 Standby X L X X High-Z ISB,ISB1 Output Disable L H H H High-Z ICC,ICC1 Read L H L H DOUT ICC,ICC1 Write L H X L DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care. Page 2 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. *5 MAX. UNIT Supply Voltage VCC V5.2.7 3.0 5 Input High Voltage V IH *1 V - V 2.4CC+0.3 V Input Low Voltage V IL *2 V 6 . 0 - 5 . 0 - Input Leakage Current I LI VCC >= IN VSS - 1 - 1 µA Output Leakage Current ILO VCC VOUT VSS, Output Disabled - 1 - 1 µA Output High Voltage V OH IOH V- 0 . 3 4 . 2A m 1 - = Output Low Voltage V OL IOL = 2mA - - 0.4 V - 55 - 15 45 mAICC Cycle time = Min. CE# = VIL and CE2 = VIH, II/O = 0mAAverage Operating Power supply Current I CC1 Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V, II/O = 0mA other pins at 0.2V or VCC-0.2V - 3 10 mA -C 1 10 µAStandby Power Supply Current I SB1 CE# V CC-0.2V or CE2≦0.2V -I - 1 20* 4 µA Notes: C = Commercial Temperature I = Industrial temperature 1. VIH(max) =VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) =VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not100% tested. 4. 10µA fors pecial request 5. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25ºC ºCCAPACITANCE (TA= 25 , f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note :These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS V o t V 2 . 0s l e v e L e s l u P t u p n I CC - 0.2V s n 3s e m i T l l a F d n a e s i R t u p n I Input and Output Timing Reference Levels 1.5V Cd a o L t u p t u O L = 50pF + 1TTL, IOH/IOL = -1mA/2mA Alliance Memory Inc Page 3 of 12July 2017, v2.0 February2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE AS6C6264-55PARAMETER SYM. MIN. MAX. UNIT Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time t OE 30 ns Chip Enable to Output in Low-Z t CLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z t CHZ* - 20 ns Output Disable to Output in High-Z tOHZ* 20 ns Output Hold from Address Change tOH 10 - ns (2) WRITE CYCLE AS6C6264-55PARAMETER SYM. MIN. MAX. UNIT Write Cycle Time tWC 55 - ns Address Valid to End of Write t AW 50 - ns Chip Enable to End of Write t CW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap t DW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write t OW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns *These parameters are guaranteed by device characterization, but not production tested. Page 4 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Dout Data Valid tOH OE# High-ZHigh-Z tCLZ tOLZ tOE tCHZ tOHZ CE2 tACE CE# tAA Address tRC Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Page 5 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) TOW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW CE# tWRtAS tAW Address tWC CE2 Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.t OW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Page 6 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . MAX. UNIT VCC for Data Retention V DR CE# V≧ CC - 0.2V or CE2 ≦ 0.2V 1.5 - 5.5 V Data Retention Current I DR VCC = 1.5V CE# V≧ CC - 0.2V or CE2 ≦ 0.2V - 0.5 10 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR t RC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ≧ 1.5V CE# V≧ cc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR ≧ 1.5V CE2 ≦ 0.2V Vcc(min.) VIL tRtCDR VIL Vcc(min.) Page 7 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 28 pin 600 mil PDIP Package Outline Dimension UNIT SYM. INCH.(BASE) MM(REF) A1 0.010 (MIN) 0.254 (MIN) A2 0.150±0.005 3.810±0.127 B 0.020 (MAX) 0.508(MAX) B1 0.055 (MAX) 1.397(MAX) c 0.012 (MAX) 0.304 (MAX) D 1.430 (MAX) 36.322 (MAX) E 0.6 (TYP) 15.24 (TYP) E1 0.52 (MAX) 13.208 (MAX) e 0.100 (TYP) 2.540(TYP) eB 0.625 (MAX) 15.87 (MAX) L 0.180(MAX) 4.572(MAX) S 0.06 (MAX) 1.524 (MAX) Q1 0.08(MAX) 2.032(MAX) Θ 15 o(MAX) 15 o(MAX) Page 8 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM 28 pin 330 mil SOP Package Outline Dimension UNIT SYM. INCH(BASE) MM(REF) A 0.120 (MAX) 3.048 (MAX) A1 0.002(MIN) 0.05(MIN) A2 0.098±0.005 2.489±0.127 b 0.016 (TYP) 0.406(TYP) c 0.010 (TYP) 0.254(TYP) D 0.728 (MAX) 18.491 (MAX) E 0.340 (MAX) 8.636 (MAX) E1 0.465±0.012 11.811±0.305 e 0.050 (TYP) 1.270(TYP) L 0.05 (MAX) 1.270 (MAX) L1 0.067±0.008 1.702 ±0.203 S 0.047 (MAX) 1.194 (MAX) y 0.003(MAX) 0.076(MAX) Θ 0o～10o 0 o～10o Page 9 of 12 July 2017, v2.0 Alliance Memory Inc February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM 28 pin 8mm x 13.4mm sTSOP Package Outline Dimension UNIT SYM. INCH(BASE) MM(REF) A 0.047 (MAX) 1.20 (MAX) A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.006 (TYP) 0.15(TYP) c 0.010 (TYP) 0.254(TYP) Db 0.465±0.004 11.80±0.10 e 0.022 (TYP) 0.55(TYP) D 0.528±0.008 13.40±0.20 L1 0.0315±0.004 0.80±0.10 y 0.08(MAX) 0.003(MAX) Θ 0o～5o 0 o～5o Note：E dimension is not including end flash. The total of both sides’ end flash is not above 0.3mm. July 2017, v2.0 Alliance Memory Inc Page 10 of 12February 2007 Updated July 2017 AS6C6264

8K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

Package Options: P = 28 pin 600 mil P-DIP S = 28 pin 330 mil SOP ST = 28 pin sTSOP (8mm x 13.4 mm) Tempera ture Range: C = Commercial (0ºC to +70º C) I = Industrial (-40º to +85º C) N = Lead Free ROHS Compliant Part July 2017, v2.0 Alliance Memory Inc Page 11 of 12 Alliance Organization VCC range Package Operating Temp Speed ns AS6C6264-55PCN 8k x 8 2.7-5.5V 28pin 600mil PDIP Commercial ~ 0º C to 70º C 55 AS6C626 4-55SCN 8k x 8 2.7-5.5V 28pin 330mil SOP Commercial ~ 0º C to 70º C 55 AS6C626 4-55SIN 8k x 8 2.7-5.5V 28pin 330mil SOP Industrial ~ -40ºC to 8 5º C 55 AS6C626 4-55STCN 8k x 8 2.7-5.5V 28pin sTSOP (8 x 13.4 mm) Commercial ~ 0º C to 70º C 55 AS6C6264-55STIN 8k x 8 2.7-5.5V 28pin sTSOP (8 x 13.4 mm) Industrial ~ -40ºC to 85º C 55 AS6C6264-55PIN 8k x 8 2.7-5.5V 28pin 600mil PDIP 55 Industrial ~ -40ºC to 85º C February 2007 Updated July 2017 AS6C6264

Alliance Memory, Inc.

511 Taylor Way,

San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS6C6264 Document Version: v. 2.0 © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or re gistered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to chang e or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are pos sible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. July 2017, v2.0 Alliance Memory Inc Page 12 of 12 February 2007 Updated July 2017 AS6C6264