AS6C4008-55STIN

AS6C4008_V01 ALLIANCE | Alldatasheet

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• Manufacturer or author: AlbertC
• PDF pages: 14

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512K X 8 BIT LOW POWER CMOS SRAM SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection CONTROL CIRCUIT FEATURES GENERAL DESCRIPTION A ccess time : 55 ns L ow power consumption : Operating current : 30 mA (TY P .) Standby cu rrent : 4 µA (TY P .) Single 2.7V ~ 5.5V power supp ly All o utputs TTL compatible Fully static operation Tri-state output Data rete ntion voltage :1.5V (MIN.) A ll products R OHS Compliant Package : 32-pin 450 mil SOP;32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP 36-ball 6mm x 8mm TFBGA 32-pin 400 mil TSOP-II The A S6C4008 is a 4,194,304-bit low powe r CMOS static random access memory organized a s 524,288 words by 8 bits. It is fabrica ted using ver y high performance, high re liability CMOS technology . Its standb y current is stable within th e rang e o f operating temperature. The A S6C4008 is well designed fo r very low powe r system a pplications, and particularly well sui ted fo r battery back-up non-volatile memory application. The A S6C400 8 op erate s from a sing le p owe r sup p ly of 2.7V~ 5.5Vand all inputs and outputs ar e fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby(ISB1TYP.) Operating(Icc,TYP.) AS6C4008 -40 ~ +85 ℃ 2.7 ~ 5.5V 55ns 4µA(LL) 30mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION** Vcc Vss A0-A18 DECODER 512Kx8 MEMORY ARRAY DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# WE# OE# Page 1 of 14 AUG/09, v 1.4 Alliance M emory I nc

512K X 8 BIT LOW POWER CMOS SRAM AS6C4008 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25

10 AS6C4008 23

A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE# A2 10 23 A10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 SOP/ P-DIP PIN CONFIGURATION A11 A13 WE# A17 A15 Vcc A18 9 A16 A14 A12 12 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3

24 Vss

A12 W E# A7 A13 A6 A8 A5 A9 A4 A11 DQ 0 DQ 1 OE# A10 CE# DQ 7 DQ 6 DQ 5 A A0 B DQ4 C DQ5 D Vss E Vcc F DQ6 NC A2 WE# NC A18 A17 A7 DQ0 DQ1 Vcc Vss DQ2 DQ 2 DQ 4 G DQ7 OE# CE# A16 A15 DQ3 VSS DQ 3 H A A10 A11 A12 A13 A14 TSOP-II 1 2 3 4 5 6 TFBGA Page 2 of 14 AUG/09, v 1.4 Alliance M emory I nc

512K X 8 BIT LOW POWER CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Terminal Voltage with Respect to VSS VTERM -0.5 to 6.5 V Operating Temperature TA 0 to 70(C grade) C o -40 to 85(I grade) Storage Temperature TSTG -65 to 150 C o Power Dissipation PD 1 W DC Output Current IOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260 C o *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating on ly and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# OE# WE# I/O OPERATION SUPPLY CURRENT Standby H X X High-Z ISB1 Output Disable L H H High-Z ICC,ICC1 Read L L H DOUT ICC,ICC1 Write L X L DIN ICC,ICC1 Note: H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. *3 MAX. UNIT Supply Voltage VCC 2.7 3.0 5.5 V Input High Voltage VIH*1 Vcc: 4.5 ~ 5.5V 2.4 - VCC+0.3 V Vcc: 2.7 ~ 4.5V 2.2 - VCC+0.3 V Input Low Voltage Input Leakage Current ILI VCC ≧ VIN ≧ VSS - 1 - 1 µA Output Leakage Current ILO VCC ≧ VOUT ≧ VSS, Output Disabled - 1 - 1 µA Output High Voltage VOH IOH = -1mA 2.4 - - V Output Low Voltage VOL IOL = 2mA - - 0.4 V Average Operating Power supply Current ICC Cycle time = Min. CE# = 0.2V, II/O = 0mA other pins at 0.2V or VCC - 0.2V - 55 - 30 60 mA ICC1 Cycle time = 1µs CE# = 0.2V, II/O = 0mA other pins at 0.2V or VCC - 0.2V - 4 10 mA Standby Power Supply Current ISB1 CE# ≧VCC - 0.2V -LL - 4 50 *4 µA -LLE/-LLI - 4 50 *4 µA 2. Over/Undershoot specifications are characterized, not 100% tested. 3. Typical values are included for reference only and are not guaranteed or tested. Typi cal valued are measured at VCC = VCC(TYP.) and TA = 25? 4. 25µA for special request Page 3 of 14 AUG/09, v 1.4 Alliance M emory I nc

512K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. AS6C4008-55 UNIT MIN. MAX. Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time tOE - 30 ns Chip Enable to Output in Low-Z tCLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 ns Output Disable to Output in High-Z tOHZ* - 20 ns Output Hold from Address Change tOH 10 - ns (2) WRITE CYCLE PARAMETER SYM. AS6C4008-55 UNIT MIN. MAX. Write Cycle Time tWC 55 - ns Address Valid to End of Write tAW 50 - ns Chip Enable to End of Write tCW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap tDW 25 - ns Data Hold from End of Write Time tDH 0 ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns *These parameters are guaranteed by device characterization, but not production tested. AUG09 v1.4 Alliance Memory Inc Page 4 of 14

512K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# Dout High-Z tCLZ tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z Notes : 1. WE# is high for read cycle. 2. Device is continuously selected OE# = low, CE# = low. 3. Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF . Transition is measured ±500mV from steady state. 5.At any gi ven te mperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. AUG09 v1.4 Alliance Memory Inc Page 5 of 14

512K X 8 BIT LOW POWER CMOS SRAM W RITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tAS tCW tWP tWR WE# Dout tWHZ (4) High-Z TOW (4) tDW tDH Din Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tWP tCW WE# Dout tWHZ (4) High-Z tDW tDH Din Data Valid Notes : 1. WE#, CE# must be high during all address transitions. 2. A write occurs during the overlap of a low CE#, low WE#. 3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. AUG09 v1.4 Alliance Memory Inc Page 6 of 14

512K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR CE# ≧ VCC - 0.2V 1.5 - 5.5 V Data Retention Current IDR VCC = 1.5V CE# ≧ VCC - 0.2V -LL - 2 30 µA -LLE/-LLI - 2 30 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Vcc CE Vcc(min.) tCDR VIH VDR ≧ 1.5V CE# ≧ Vcc-0.2V Vcc(min.) tR VIH AUG09 v1.4 Alliance Memory Inc Page 7 of 14

512K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 32 pin 450 mil SOP Package Outline Dimension UNIT SYM. INCH.(BASE) MM(REF) A 0.118 (MAX) 2.997 (MAX) A1 0.004(MIN) 0.102(MIN) A2 0.111(MAX) 2.82(MAX) b 0.016(TYP) 0.406(TYP) c 0.008(TYP) 0.203(TYP) D 0.817(MAX) 20.75(MAX) E 0.445 ±0.005 11.303 ±0.127 E1 0.555 ±0.012 14.097 ±0.305 e 0.050(TYP) 1.270(TYP) L 0.0347 ±0.008 0.881 ±0.203 L1 0.055 ±0.008 1.397 ±0.203 S 0.026(MAX) 0.660 (MAX) y 0.004(MAX) 0.101(MAX) Θ 0o -10o 0o -10o AUG09 v1.4 Alliance Memory Inc Page 8 of 14

512K X 8 BIT LOW POWER CMOS SRAM pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. INCH(BASE) MM(REF) A 0.047 (MAX) 1.20 (MAX) A1 0.004 ±0.002 0.10 ±0.05 A2 0.039 ±0.002 1.00 ±0.05 b 0.008 + 0.002 - 0.001 0.20 + 0.05 -0.03 c 0.005 (TYP) 0.127 (TYP) D 0.724 ±0.004 18.40 ±0.10 E 0.315 ±0.004 8.00 ±0.10 e 0.020 (TYP) 0.50 (TYP) HD 0.787 ±0.008 20.00 ±0.20 L 0.0197 ±0.004 0.50 ±0.10 L1 0.0315 ±0.004 0.08 ±0.10 y 0.003 (MAX) 0.076 (MAX) Θ 0o～5o 0o～5o AUG09 v1.4 Alliance Memory Inc Page 9 of 14

512K X 8 BIT LOW POWER CMOS SRAM A A1 A2 c e b E 0.254 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 12° (2x) 1 32 16 17 D "A" Seating Plane y 12° (2X) 16 17 GAUGE PLANE SEATING PLANE 12° (2X) L "A" DETAIL VIEW 1 32 UNIT SYM. INCH(BASE) MM(REF) A 0.049 (MAX) 1.25 (MAX) A1 0.005 ±0.002 0.130 ±0.05 A2 0.039 ±0.002 1.00 ±0.05 b 0.008 ±0.01 0.20±0.025 c 0.005 (TYP) 0.127 (TYP) D 0.465 ±0.004 11.80 ±0.10 E 0.315 ±0.004 8.00 ±0.10 e 0.020 (TYP) 0.50 (TYP) L 0.0197 ±0.004 0.50 ±0.10 L1 0.0315 ±0.004 0.8 ±0.10 y 0.003 (MAX) 0.076 (MAX) Θ 0o～5o 0o～5o AUG09 v1.4 Alliance Memory Inc Page 10 of 14

512K X 8 BIT LOW POWER CMOS SRAM 36 ball 6mm × 8mm TFBGA Package Outline Dimension AUG09 v1.4 Alliance Memory Inc Page 11 of 14

512K X 8 BIT LOW POWER CMOS SRAM -pin 400mil TSOP-Ⅱ Package Outline Dimension AUG/09, v 1.0.a Alliance Memory Inc Page 12 of 14

512K X 8 BIT LOW POWER CMOS SRAM 32 pin 600 mil P-DIP Package Outline Dimension UNIT SYM. INCH(BASE) MM(REF) A1 0.015 (MIN) 0.381 (MIN) A2 0.155 ± 0.005 3.937 ± 0.127 B 0.018 ± 0.005 0.457 ± 0.127 D 1.650 ± 0.005 41.910 ± 0.127 E 0.600 ± 0.010 15.240 ± 0.254 E1 0.545 ± 0.005 13.843 ± 0.127 e 0.100 (TYP) 2.540 (TYP) L 0.130 ± 0.010 3.302 ± 0.254 S 0.075 ± 0.010 1.905 ± 0.254 Q1 0.070 ± 0.005 1.778 ± 0.127 Note : D/E1/S dimension do not include mold flash. AUG09 v1.4 Alliance Memory Inc Page 13 of 14

512K X 8 BIT LOW POWER CMOS SRAM

ORDERING INFORMATION

Alliance Organization VCC Package Operating Temp Speed ns AS6C4008-55PCN 512k x 8 5V 32pin 600mil DIP Commercial ~ 0º C to 70º C 55 AS6C4008-55SIN 512k x 8 5V 32pin 450mil SOP Industrial ~ -40ºC to 85º C 55 AS6C4008-55TIN 512k x 8 5V 32pin TSOP 1 (8 x 20 mm) Industrial ~ -40ºC to 85º C 55 AS6C4008-55STIN 512k x 8 5V 32pin sTSOP (8 x 13.4 mm) Industrial ~ -40ºC to 85º C 55 AS6C4008-55BIN 512k x 8 5V 36pin TFBGA (6mm x 8mm) Industrial ~ -40ºC to 85º C 55 AS6C4008-55ZIN 512k x 8 5V 32-pin 400mil TSOP 11 Industrial ~ -40ºC to 85º C 55 PART NUMBERING SYSTEM AS6C 4008 - 55 X X N low Device Access Package Options: Temperature Range: N = Lead P = 32 pin 600 mil P-DIP S = 32 pin 450 mil SOP T = 32 pin TSOP 1 (8mm x 20 mm) C = Commercial power Number Z = 32-pin 400mil TSOP 11 (0ºC to +70º C) Free ROHS SRAM 40 = 4M ST = 32 pin sTSOP (8mm x 13.4 mm) I = Industrial Compliant prefix 08 = by 8 Time B = 36 pin TFBGA (6mm x 8mm) (-40º to +85º C) Part AUG09 v1.4 Alliance Memory Inc Page 14 of 14