AS6C1616-70XXN

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FEATURES

Fast access time : 55/70ns Low power consumption: Operating current : 45/30mA (TYP .) Standby current : 4μA (TYP .) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.2V (MIN.) Lead free and green package available Package : 48-ball 6mm x 8mm TFBGA GENERAL DESCRIPTION The AS6C1616 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1616 operates from a singlepower supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Power DissipationProduct Family Operating Temperature Vcc Range Speed Standby(ISB1,TYP.) Operating (Icc,TYP .) AS6C1616(I) -40 ~ 85 C 2.7 ~ 3.6V 55/70ns 4µA 45/30mA FUNCTIONAL BLOCK DIAGRAM CONTROL CIRCUIT DECODER 1024Kx16 MEMORY ARRAY COLUMN I/O A0-A19 Vcc Vss DQ8-DQ15 Upper Byte DQ0-DQ7 Lower Byte I/O DATA CIRCUIT CE2 WE# OE# LB# UB# CE# PIN DESCRIPTION S YMB OL DE S C R IP TION A0 - A19 Address Inputs DQ0 – DQ15 Data Inputs/Outputs C E #, C E 2 C hip E nable Input WE # Write E nable Input OE # LB# UB# VC C P ower S upply VS S G round Output E nable Input Lower Byte C ontrol Upper Byte C ontrol o 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 AS6C1616 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 1 of 11

WE # DQ9 DQ1 4 DQ1 5 A18 Vss C E 2 A13 DQ8 Vcc Vcc DQ7 A15 Vss C E # LB# DQ6 DQ2 DQ0 A2OE # A1

5 A 6 A

A4UB# 123 4 5 6 H G C D E F A B A12 NC A17 A7 A16 DQ1 0 DQ1 1 DQ1 2 DQ13 DQ5 DQ4 DQ3 DQ1 ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 4.6 V Voltage on any other pin relative to VSS VT2 -0.5 to VC C+0.5 V Operating T emperature TA -40 to 85 (I grade) ℃ Storage T emperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA Soldering Temperature (under 10 sec) TSOLDER 260 ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 2 of 11 AS6C1616

I/O OPERATION MODE CE# CE2 OE# WE# LB# UB# DQ0-DQ7 DQ8-DQ15 SUPPLY CURRENT S tandby H X X X L X X X X X X X X X H X X H High – Z High – Z High – Z High – Z High – Z High – Z I SB,ISB1 Output Disabl e L L H H H H H H L X X L High – Z High – Z High – Z High – Z I C C,ICC1 Read L L L H H H L L L H H H L H L H L L D OUT High – Z DOUT High – Z DOUT DOUT IC C,ICC1 Write L L L H H H X X X L L L L H L H L L D IN High – Z DIN High – Z DIN DIN IC C,ICC1 Note: H = V IH, L = V IL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . *4 MAX. UNIT Supply V oltage VC C 2.7 3.0 3.6 V Input High V oltage V IH *1 2.2 - V C C+0.3 V Input Low V oltage V IL *2 - 0.2 - 0.6 V Input Lea kage Curre nt I LI V C C ≧ VIN ≧ VSS - 1 - 1 µA Output Lea kage Cur rent ILO VC C ≧ VOUT ≧ VSS Output Disabl ed - 1 - 1 µA Output High V oltage V OH I OH = -1mA 2.2 2.7 - V Output Lo w V oltage V OL I OL = 2mA - - 0.4 V -55 45 60 mA IC C Cycle time = Min. CE# = V IL and C E 2 = VIH II/O = 0mA -70 - 30 45 mA Other pin s at VIL or VIH Average Operating Powe r supply Current I CC1 Cyc le time = 1µs CE#≦0.2V a nd CE2≧VC C-0.2V II/O = 0mA Other pin s at 0.2V or VC C-0.2V - 8 16 mA ISB CE# = VIH or CE2 = VIL Other pin s at VIL or VIH - 0.3 2 mA -SLI - 6 40 µA S tandby Power Supply Cu rrent I SB1 CE# V ≧C C -0. 2V or CE2≦0.2V Other pin s at 0.2V or VC C-0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 3 of 11 AS6C1616

READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Dout Data Valid High-ZHigh-Z tCLZ tOLZ tCHZ tOHZ tOH OE# tOE LB#,UB# tBHZ tACE tBA tBLZ CE# tAA Address tRC CE2 Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low . 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.t CLZ , tBLZ, tOLZ , tCHZ, tBHZ and tOHZ are speci/f_ied with C L = 5pF . Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than t CLZ , t BHZ is less than t BLZ, tOHZ is less than t OLZ. 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 5 of 11 AS6C1616

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) TOW LB#,UB# tBW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# an d CE2 Co ntrolled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW tWP tBW CE# Address tWRtAS tAW tWC CE2 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 6 of 11 AS6C1616

WRITE CYCLE 3 (LB#,UB # Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCWtAS tWP tBW CE# Address tWRtAW tWC CE2 Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 7 of 11 AS6C1616

DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . MAX. UNIT VCC for Data Retention V DR CE# V≧ CC - 0.2V or CE2≦0.2V 1.2 - 3.6 V -SLI - 4 40 µA Data Retention Current IDR VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V other pins at 0.2V or VCC-0.2V Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR t RC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ≧ 1.2V C E# V≧ cc-0.2V Vcc(min.) VIH tRtC DR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR ≧ 1.2V CE2 ≦ 0.2V Vcc (min.) VIL tRtC DR VIL Vcc(min.) Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) Vcc LB# ,U B# VDR ≧ 1.2V LB#,UB# V≧ cc-0.2V Vcc (min.) VIH tRtC DR VIH Vcc(min.) 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 8 of 11 AS6C1616

48-ball 6mm × 8mm TFBGA Package Outline Dimension 512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 9 of 11 AS6C1616

1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY/2009, V1.a Alliance Memory Inc. Page 10 of 11

Ordering Information

Range Package Operating Temp Speed ns AS6C1616-70BIN 1024K x 16 2.7 - 3.6V 48ball TFBGA Industrial ~ -40 C – 85 C) 70 AS6C1616-55BIN 1024K x 16 2.7 - 3.6V 48ball TFBGA Industrial ~ -40 C – 85 C) 55 Part Numbering System AS6C 1616 -70 X X N low power SRAM prefix Device Number 16 = 16M 16 = x16 Access Time Package Option 48ball TFBGA Temperature Range I = Industrial (-40 to + 85 C) N = Lead Free RoHS compliant part

512K X 8 BI T LOW POWER CMOS SRAM January 2007 1024K X 16 BIT LOW POWER CMOS SRAM FEBRUARY 2009 FEBRUARY/2009, V 1.a Alliance Memory Inc. Page 11 of 11 AS6C1616 Alliance Memory, Inc

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