AS6C1608

AS6C1608 ALSC | Alldatasheet

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Technical content

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc.

551 Taylor Way, Suite #1, San Carlos, CA 94070, USA

Tel: +1 650 610 6800 Fax: +1 650 620 9211

REVISION HISTORY

Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package “48-ball 8mm × 10mm TFBGA” Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211

FEATURES

 Fast access time : 55/70ns  Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 4A (TYP .) SL-version  Single 2.7V ~ 3.6V power supply  All inputs and outputs TTL compatible  Fully static operation  Tri-state output  Data retention voltage : 1.2V (MIN.)  Green package available  Package : 44-pin 400 mil TSOP-II 48-ball 8mm x 10mm TFBGA GENERAL DESCRIPTION The AS6C1608 is a 16,777,216-bit low power CMOS static random access memory organized as 2,097,152 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C1608 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1608 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP .) AS6C1608(I) -40 ~ 85℃ 2.7 ~ 3.6V 55/70ns 4µA(SL) 45/30mA FUNCTIONAL BLOCK DIAGRAM DECODER I/O DATA CIRCUIT CONTROL CIRCUIT 2048Kx8 MEMORY ARRAY COLUMN I/O A0-A20 Vcc Vss DQ0-DQ7 CE# WE# OE# CE2 PIN DESCRIPTION SYMBOL DESCRIPTION A0 – A20 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection PIN CONFIGURATION

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 44-pin TSOP(Type II) 48-ball 8mmx10mm TFBGA TFBGA NCA20 A10A9 A11 A14 A8 A19 WE# DQ0 DQ3 NC A18 Vss CE2 A13 NC Vcc Vcc A15 Vss CE# NC DQ7 DQ4 NC A2OE# A1 A6A5 A4NC 1 2 3 4 5 6 H G C D E F A B A12 NC A17 A7 A16 NC DQ1 DQ2 NC NC DQ6 DQ5 NC

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1 -0.5 to 4.6 V Voltage on any other pin relative to VSS VT2 -0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) ℃ Storage Temperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# CE2 OE# WE# I/O OPERATION SUPPLY CURRENT Standby H X X X High-Z ISB,ISB1 X L X X High-Z ISB,ISB1 Output Disable L H H H High-Z ICC,ICC1 Read L H L H DOUT ICC,ICC1 Write L H X L DIN ICC,ICC1 Note: H = V IH, L = VIL, X = Don't care.

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . *4 MAX. UNIT Supply Voltage VCC 2.7 3.0 3.6 V Input High Voltage VIH *1 2.2 - VCC+0.3 V Input Low Voltage VIL *2 - 0.2 - 0.6 V Input Leakage Current ILI VCC ≧ VIN ≧ VSS - 1 - 1 µA Output Leakage Current ILO VCC ≧ VOUT ≧ VSS Output Disabled - 1 - 1 µA Output High Voltage VOH IOH = -1mA 2.2 2.7 - V Output Low Voltage VOL IOL = 2mA - - 0.4 V Average Operating Power supply Current ICC Cycle time = Min. CE# = VIL and CE2 = VIH II/O = 0mA Other pins at VIL or VIH - 55 - 45 60 mA - 70 - 30 45 mA ICC1 Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V - 8 16 mA Standby Power Supply Current ISB CE# = VIH or CE2 = VIL Other pins at VIL or VIH - 0.3 2 mA ISB1 CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V SL*5 SLI*5 25℃ - 4 10 µA 40℃ - 4 10 µA SL - 4 30 µA SLI - 4 40 µA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP .) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pF Input/Output Capacitance CI/O - 8 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. AS6C1608-55 AS6C1608-70 UNIT MIN. MAX. MIN. MAX. Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Enable Access Time tACE - 55 - 70 ns Output Enable Access Time tOE - 30 - 35 ns Chip Enable to Output in Low-Z tCLZ* 10 - 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 - 25 ns Output Disable to Output in High-Z tOHZ* - 20 - 25 ns Output Hold from Address Change tOH 10 - 10 - ns (2) WRITE CYCLE PARAMETER SYM. AS6C1608-55 AS6C1608-70 UNIT MIN. MAX. MIN. MAX. Write Cycle Time tWC 55 - 70 - ns Address Valid to End of Write tAW 50 - 60 - ns Chip Enable to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Write Pulse Width tWP 45 - 55 - ns Write Recovery Time tWR 0 - 0 - ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from End of Write Time tDH 0 - 0 - ns Output Active from End of Write tOW* 5 - 5 - ns Write to Output in High-Z tWHZ* - 20 - 25 ns *These parameters are guaranteed by device characterization, but not production tested.

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOHtAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Dout Data Valid tOH OE# High-ZHigh-Z tCLZ tOLZ tOE tCHZ tOHZ CE2 tACE CE# tAA Address tRC Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWRtAS (4) TOW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW CE# tWRtAS tAW Address tWC CE2 Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP . MAX. UNIT VCC for Data Retention VDR CE# ≧ VCC - 0.2V or CE2≦0.2V 1.2 - 3.6 V Data Retention Current IDR VCC = 1.2V CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V SL SLI 25℃ - 2.5 10 µA 40℃ - 2.5 10 µA SL - 2.5 30 µA SLI - 2.5 40 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) Vcc CE# VDR ¡Ù 1.2V CE# ¡Ù Vcc-0.2V Vcc(min.) VIH tRtCDR VIH Vcc(min.) Low Vcc Data Retention Waveform (2) (CE2 controlled) Vcc CE2 VDR ¡Ù 1.2V CE2 ¡Ø 0.2V Vcc(min.) VIL tRtCDR VIL Vcc(min.)

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-II Package Outline Dimension SYMBOLS DIMENSIONS IN MILLMETERS DIMENSIONS IN MILS b 0.30 - 0.45 11.8 - 17.7 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 y - - 0.076 - - 3 Θ 0o 3o 6o 0o 3o 6o

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 48-ball 8mm × 10mm TFBGA Package Outline Dimension

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211

ORDERING INFORMATION

Alliance Part no Organisation Vcc Range Package Operating Temp Speed ns AS6C1608-XXBIN - Tray 2048 x 8 2.7V – 3.6V 48-ball 8mm x 10mm TFBGA -40℃~85℃ 55/70 AS6C1608-XXBINTR – Tape & Reel 2048 x 8 2.7V – 3.6V 48-ball 8mm x 10mm TFBGA -40℃~85℃ 55/70 AS6C1608-XXTIN – Tray 2048 x 8 2.7V – 3.6V 44-pin 400mil TSOP-II -40℃~85℃ 55/70 AS6C1608-XXTINTR – Tape & Reel 2048 x 8 2.7V – 3.6V 44-pin 400mil TSOP-II -40℃~85℃ 55/70 PART NUMBERING SYSTEM AS6C 1608 -55/70 B or T I N LOW POWER SRAM PREFIX DEVICE NUMBER 16 = 16M 08 = by 8 Access Time B = 48ball TFBGA (8mm x 10mm) Or T = 44-pin 400mil TSOP-II Temperature range: I = Industrial (-40°C to 85°C) N = Lead Free ROHS Compliant Part

Rev. 1.1 2048K X 8 BIT LOW POWER CMOS SRAM Alliance Memory Inc.reserves the rights to change the specifications and products without notice. Alliance Memory, Inc. Tel: +1 650 610 6800 Fax: +1 650 620 9211 THIS PAGE IS LEFT BLANK INTENTIONALLY .