AS4LC4M4F1 ALSC | Alldatasheet

Document overview

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  • PDF pages: 14

Technical content

Features

  • Organization: 4,194,304 words × 4 bits
  • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time
  • Low power consumption - Active: 500 mW max - Standby: 3.6 mW max, CMOS I/O
  • Fast page mode
  • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh
  • TTL-compatible, three-state I/O
  • JEDEC standard package - 300 mil, 24/26-pin SOJ
  • 3.3V power supply
  • Latch-up current ≥ 200 mA
  • ESD protection ≥ 2000 volts
  • Industrial and commercial temperature available Pin arrangement A10 VCC GND GND I/O3 I/O2 CAS OE VCC I/O0 I/O1 WE RAS NC SOJ AS4LC4M4F1 A10 VCC GND GND I/O3 I/O2 CAS OE VCC I/O0 I/O1 WE RAS NC TSOP* AS4LC4M4F1 *TSOP availability to be determined Pin designation Pin(s)

Description

Maximum column address access time tCAA ns Maximum CAS access time tCAC ns Maximum output enable (OE) access time tOEA ns Minimum read or write cycle time tRC 100 ns Minimum fast page mode cycle time tPC ns Maximum operating current ICC1 120 110 mA Maximum CMOS standby current ICC5 1.0 1.0 mA

5/16/01; v.1.0 Restored Alliance Semiconductor P. 2 of 14 Functional description The AS4LC4M4F1 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 4,194,304 words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in PC, workstation, router and switch applications. This device features a high speed page-mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion. Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:

  • RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
  • Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data.
  • CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care).
  • Normal read or write cycles refresh the row being accessed.
  • Self-refresh cycles The AS4LC4M4F1 is available in the standard 24/26-pin plastic SOJ. TSOP 24/26-pin availability is to be determined. The AS4LC4M4F1 operates with a single power supply of 3.3V ± 0.3V and provides TTL compatible inputs and outputs. Logic block diagram for 2K refresh Recommended operating conditions †VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. Parameter Symbol Min Nominal Max Unit Supply voltage VCC 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V Input voltage VIH 2.0 VCC+0.5V V VIL –0.5† 0.8 V Ambient operating temperature Commercial TA Industrial -40 RAS clock generator Refresh controller 2048 × 2048 × 4 Array (16,777,216) Sense amp VCC GND Address buffers Row decoder Column decoder Substrate bias generator Data I/O buffers OE RAS CAS WE clock generator WE I/O0 to I/O3 CAS clock generator A10

5/16/01; v.1.0 Restored Alliance Semiconductor P. 3 of 14 Absolute maximum ratings DC electrical characteristics Parameter Symbol Min Max Unit Input voltage Vin -1.0 4.6 V Input voltage (DQs) VDQ -1.0 4.6 V Power supply voltage VCC -1.0 4.6 V Storage temperature (plastic) TSTG -55 150 Soldering temperature × time TSOLDER 260 × 10 oC × sec Power dissipation PD 0.432 W Short circuit output current Iout mA Parameter Symbol Test conditions -50 -60 Unit Notes Min Max Min Max Input leakage current IIL 0V ≤ Vin ≤ +Vcc(max) Pins not under test = 0V µA Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ + Vcc(max) µA Operating power supply current ICC1 CAS, Address cycling; tRC=min 120 110 mA 1,2 TTL standby power supply current ICC2 RAS = CAS ≥ VIH 2.0 2.0 mA Average power supply current, RAS refresh mode or CBR ICC3 RAS cycling, CAS ≥ VIH, tRC = min of RAS low after CAS low. 120 110 mA Fast page mode average power supply current ICC4 RAS = VIL, CAS, address cycling: tHPC = min mA 1, 2 CMOS standby power supply current ICC5 RAS = CAS = VCC - 0.2V 2.0 2.0 mA Output voltage VOH IOUT = -2.0 mA 2.4 2.4 V VOL IOUT = 2.0 mA 0.4 0.4 V CAS before RAS refresh current ICC6 RAS, CAS cycling, tRC = min 120 110 mA Self refresh current ICC7 RAS = CAS ≤ 0.2v, WE - OE ≥ VCC - 0.2V, all other inputs at 0.2V or VCC - 0.2V 0.6 0.6 mA

5/16/01; v.1.0 Restored Alliance Semiconductor P. 4 of 14 AC parameters common to all waveforms Read cycle Symbol Parameter -50 -60 Unit Notes Min Max Min Max tRC Random read or write cycle time 100 ns tRP RAS precharge time ns tRAS RAS pulse width 10K 10K ns tCAS CAS pulse width 10K 10K ns tRCD RAS to CAS delay time ns tRAD RAS to column address delay time ns tRSH CAS to RAS hold time ns tCSH RAS to CAS hold time ns tCRP CAS to RAS precharge time ns tASR Row address setup time ns tRAH Row address hold time ns tT Transition time (rise and fall) ns 4,5 tREF Refresh period ms tCP CAS precharge time ns tRAL Column address to RAS lead time ns tASC Column address setup time ns tCAH Column address hold time ns Symbol Parameter -50 -60 Unit Notes Min Max Min Max tRAC Access time from RAS ns tCAC Access time from CAS ns 6,13 tAA Access time from address ns 7,13 tRCS Read command setup time ns tRCH Read command hold time to CAS ns tRRH Read command hold time to RAS ns

5/16/01; v.1.0 Restored Alliance Semiconductor P. 5 of 14 Write cycle Read-modify-write cycle Refresh cycle Symbol Parameter -50 -60 Unit Notes Min Max Min Max tWCS Write command setup time ns tWCH Write command hold time ns tWP Write command pulse width ns tRWL Write command to RAS lead time ns tCWL Write command to CAS lead time ns tDS Data-in setup time ns tDH Data-in hold time ns Symbol Parameter -50 -60 Unit Notes Min Max Min Max tRWC Read-write cycle time 113 135 ns tRWD RAS to WE delay time ns tCWD CAS to WE delay time ns tAWD Column address to WE delay time ns Symbol Parameter -50 -60 Unit Notes Min Max Min Max tCSR CAS setup time (CAS-before-RAS) ns tCHR CAS hold time (CAS-before-RAS) ns tRPC RAS precharge to CAS hold time ns tCPT CAS precharge time (CBR counter test) ns

5/16/01; v.1.0 Restored Alliance Semiconductor P. 6 of 14 Fast page mode cycle Output enable Self-refresh cycle Symbol Parameter -50 -60 Unit Notes Min Max Min Max tCPA Access time from CAS precharge tRASP RAS pulse width 100K 100K tPC Read-write cycle time tCP CAS precharge time (fast page) tPCM Fast page mode RMW cycle tCRW Page mode CAS pulse width (RMW) Symbol Parameter -50 -60 Unit Notes Min Max Min Max tCLZ CAS to output in Low Z ns tROH RAS hold time referenced to OE ns tOEA OE access time ns tOED OE to data delay ns tOEZ Output buffer turnoff delay from OE ns tOEH OE command hold time ns tOLZ OE to output in Low Z ns tOFF Output buffer turn-off time ns 8,10 Std Symbol Parameter -50 -60 Unit Notes Min Max Min Max tRASS RAS pulse width (CBR self refresh) 100 100 µs tRPS RAS precharge time (CBR self refresh) 105 ns tCHS CAS hold time (CBR self refresh) nx

5/16/01; v.1.0 Restored Alliance Semiconductor P. 7 of 14 Notes ICC1, ICC3, ICC4, and ICC6 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC ≥ tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. AC test conditions Key to switching waveforms - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.0V and VIL = 0.8V - Input rise and fall times: 2 ns *including scope and jig capacitance 50 pF* R2 = 295Ω R1 = 828Ω Dout GND +3.3V Figure A: Equivalent output load (AS4LC4M4F1) Undefined output/don’t care Falling input Rising input

5/16/01; v.1.0 Restored Alliance Semiconductor P. 8 of 14 Read waveform Early write waveform tRAS tRC tRP tRSH tRAD tRCH tROH tCAC tOEA tOFF (see note 11) tOEZ RAS CAS Address WE OE DQ Column address tCRP tCSH tRCD tASC tCAH tCAS tRAL tRAH tRCS tAA tCLZ tRRH Data out tRAC tASR Row address tROH tWEZ tOLZ tREZ tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAD tASC tCAH tWCS tCWL tRWL tWCH tWP tDS tDH Data in RAS CAS Address WE OE DQ Row address tRAL Column address tRAH tASR

5/16/01; v.1.0 Restored Alliance Semiconductor P. 9 of 14 Write waveform OE controlled Read-modify-write waveform Row address tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAH tRAL tRAD tCAH tCWL tRWL tOEH tDS tDH Data in RAS CAS Address WE OE DQ Column address tWP tASC tASR tOED tRAS tRWC tRP tCRP tRSH tRCD tCSH tCAS tRAD tRAL tAR tCAH tCWL tCWD tRWL tAWD tWP tOEA tCLZ tCAC tAA tDS tDH Row address Column address Data in Data out RAS CAS Address WE OE DQ tRAH tRWD tRCS tRAC tOEZ tOED tASC tASR tOLZ

5/16/01; v.1.0 Restored Alliance Semiconductor P. 10 of 14 Fast page mode read waveform Fast page mode byte write waveform Row tRASP tRP tCRP tRCD tCAS tCSH tRSH tPC tASR tRAD tRCH tRCS tRRH tRCH tOEA tOEA tAA tRAC tOEZ tCAC Data out Data out Data out Column Column Column RAS CAS Address WE OE I/O tAR tRAH tASC tCAH tRAL tRCS tCLZ tCP tOFF tCAP tRASP tRP tRCD tCSH tCAS tCP tCRP tASR tCAH tCAH tRAL tCAH tCWD tAWD tCWD tCWL tCWD tAWD tRWL tWP tOEZ tOEA tRAC tDS tCLZ tCAC tCAP Row Column Column Column Data out Data in Data in Data out Data out Data in RAS CAS Address WE OE I/O tRAD tRAH tRWD tRCS tCWL tOEA tAA tDH tDS tCLZ tCAC tCLZ tCAC tOED tPCM

5/16/01; v.1.0 Restored Alliance Semiconductor P. 11 of 14 Fast page mode early write waveform CAS before RAS refresh waveform WE = VIH RAS only refresh waveform WE = OE = VIH or VIL tRASP tRWL tASC tWCS tCP tRAL tWCH tCWL tWP tDS tDH tCAS Row Column Column Column Data In Data in Data in RAS CAS Address WE OE I/O tPC tCAH tCSH tRCD tOEH tHDR tAR tRAD tASR tCRP tRAH tRSH tOED tRP tRC tRAS tRPC tCP tCSR tCHR RAS CAS DQ OPEN tRAS tRP tRC tCRP tRPC tASR tRAH Row address RAS Address CAS

5/16/01; v.1.0 Restored Alliance Semiconductor P. 12 of 14 Hidden refresh waveform (read) Hidden refresh waveform (write) tRAS tRC tRP tRAS tRC tRP tCRP tRCD tRSH tCRP tCHR tASR tRAD tASC tRRH tOEA tCLZ tCAC tOEZ Col address Row Data out RAS CAS Address WE OE DQ tAR tRAH tRAC tAA tRCS tCAH tOFF tRAS tRC tRP tCRP tRCD tRSH tASR tRAH tRAD tAR tCAH tWCS tWCH tDS tDH Data in Col address Row address RAS CAS Address WE DQ OE tASC tRWL tWCR tWP tDHR tRAL tCHR

5/16/01; v.1.0 Restored Alliance Semiconductor P. 13 of 14 CAS before RAS refresh counter test waveform tRAS tRSH tRP tCSR tCHR tCPT tCAS tCAH tCLZ tCAC tRCH tRRH tROH tOEA tRWL tCWL tWCS tWP tWCH tDS tDH tRCS tOEA tDS tDH Col address Data out Data in Data out Data in RAS CAS Address DQ WE OE WE DQ OE WE OE DQ tOED t AA tCLZ tCAC tOEZ tWP tCWL tRCS tAA tOEZ tAWD tCWD tRAL Read cycle Write cycle Read-Write cycle tASC tOFF tRWL

5/16/01; v.1.0 Restored Alliance Semiconductor P. 14 of 14 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. CAS-before-RAS self refresh cycle Capacitance 15 ƒ = 1 MHz, Ta = Room temperature AS4LC4M4F1 ordering information AS4LC4M4F1 family part numbering system Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN1 A0 to A10 Vin = 0V pF CIN2 RAS, CAS, WE, OE Vin = 0V pF DQ capacitance CDQ DQ0 to DQ03 Vin = Vout = 0V pF Package \\ RAS access time 50 ns 60 ns Plastic SOJ, 300 mil, 24/26-pin 3.3V AS4LC4M4F1-50JC AS4LC4M4F1-50JI AS4LC4M4F1-60JC AS4LC4M4F1-60JI Plastic TSOP, 300 mil, 24/26-pin* * Shading indicates availability is TBD. 3.3V AS4LC4M4F1-50TC AS4LC4M4F1-50TI AS4LC4M4F1-60TC AS4LC4M4F1-60TI AS4 LC 4M4 –XX X X DRAM prefix LC = 3.3V CMOS 4M×4 F1=2K refresh RAS access time Package: J = SOJ 300 mil, 24/26 T = TSOP 300 mil, 24/26* Temperature range C=Commercial, 0°C to 70 °C I=Industrial, -40°C to 85°C tRP tRASS tRPC tCP tCHS tCEZ RAS CAS DQ CAS tRPS tCSR tRPC