AS4LC4M16S0

AS4LC8M8S0 ALSC | Alldatasheet

Document overview

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Technical content

Features

• PC100/133 compliant
• Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous - All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
• H i g h s p e e d - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption - Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function - 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3) Pin arrangement VCC V SS VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM VSS DQ15 VSSQ DQ14 DQ13 V CCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE 54-pin TSOP WE CAS RAS CS BA0 BA1 A10 NC A11 NC DQ1 NC DQ2 NC DQ3 NC NC DQ7 NC DQ6 NC DQ5 NC DQ4 NC DQM 4LC4M16S0 VCC VCC DQ0 VCCQ VSSQ VCCQ VSSQ VCC WE CAS RAS CS BA0 BA1 A10 VSS VSS VSSQ VCCQ VSSQ VCCQ VSS NC CLK CKE NC A11 A5AS4LC4M16S0 AS4LC4M16S0 Pin designation Pin(s) Description DQM (8M×8) UDQM/LDQM (4M×16) Output disable/write mask A0 to A11 Address inputs BA0, BA1 Bank select inputs DQ0 to DQ7 (8M×8) DQ0 to DQ15 (4M×16) Input/output RAS Row address strobe CAS Column address strobe WE Write enable CS Chip select VCC, VCCQ Power (3.3V ± 0.3V) VSS, VSSQ Ground CLK Clock input CKE Clock enable Selection guide Symbol -75 (PC133) -8 -10F (PC100) -10 (PC100) Unit Bus frequency f max 133 125 100 100 MHz Minimum clock access time CL = 2 t AC ––6– n s CL = 3 t AC 5.4 6 – 6 ns Minimum setup time t S 1.5 2 2 2 ns Minimum hold time t H 0 . 81 . 01 . 01 . 0 n s Minimum RAS to CAS delay t RCD 3323 c y c l e s Minimum RAS precharge time t RP 3323 c y c l e s Remarks: (CL/tRCD/tRP) 3/3/3 3/3/3 2/2/2 3/3/3

2 ALLIANCE SEMICONDUCTOR 7/5/00

The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively . V ery high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a new column address. The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. This provides a significant advantage over asynchronous EDO and fast page mode devices. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. DRAM commands and functions are decoded from control inputs. Basic commands are as follows: The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both devices operate with a power supply of 3.3V ± 0.3V . Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL-compatible. Logic block diagram † For AS4LC8M8S0, Banks A-D will read 8M×8 (4096×512×8). ‡For AS4LC4M16S0, DQM will be UDQM and LDQM.

• Mode register set • Deactivate bank • Deactivate all banks • Select row; activate bank
• Select column; write • Select column; read • Deselect; power down • CBR refresh
• Auto precharge with read/write • Self-refresh RAS CAS WE CLK CKE Clock generator Mode register Command decoder Control logic Row address buffer Refresh counter Column address buffer Burst counter Row decoder Column decoder and latch circuit Data control circuit Latch circuit Input and output buffer DQ A[11:0] DQM‡CS Bank selectBA0, BA1 Bank A† 1M×16 (4096×256×16) Bank B† 1M×16 (4096×256×16) Bank C† 1M×16 (4096×256×16) Bank D† 1M×16 (4096×256×16) Sense amplifier

7/5/00 ALLIANCE SEMICONDUCTOR 3 Pin descriptions Pin Name Description CLK System clock All operations synchronized to rising edge of CLK. It also increments the burst counters. CKE Clock enable Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. Pulling CKE low has the following effects: all banks idle: Precharge power down and Self refresh. row active in any bank: Active power down. burst/access in progress: Clock suspend. When in Power down or Self refresh mode, CKE becomes asynchronous until exiting the mode. CS Chip select Enables or disables device operation by masking or enabling all inputs except CLK, CKE, UDQM/LDQM (×16), DQM (×8). A0~A11 Address Row and column addresses are multiplexed. Row address: A0~A11. Column address (8M×8): A0~A8. Column address (4M×16): A0~A7. BA0, BA1 Bank select Memory cell array is organized in 4 banks. BA0 and BA1 select which internal bank will be active during activate, read, write, and precharge operations. RAS Row address strobe Enables row access and precharge operation. When RAS is low, row address is latched at the rising edge of CLK. CAS Column address strobe Enables column access. When CAS is low, starting column address for the burst access operation is latched at the rising edge of the CLK. WE Write enable Enables write operation and row precharge operation. ×8: DQM ×16: UDQM/LDQM Output disable/ write mask Controls I/O buffers. When DQM is high, output buffers are disabled during a read operation and input data is masked during a write operation. DQM latency is 2 clocks for Read and 0 clocks for Write. For ×16, LDQM controls lower byte (DQ0–7) and UDQM controls upper byte (DQ8–15). For ×8, only one DQM controls the 8 DQs. UDQM and LDQM are considered same state when referenced as DQM. DQ0~DQ15 Data input/output Data inputs/outputs are multiplexed. Data bus for 8M ×8 is DQ0~DQ7 only . VDD/VSS Power supply/ground Power and ground for core logic and input buffers. VDDQ/VSSQ Data output power/ ground Power and ground for data output buffers.

4 ALLIANCE SEMICONDUCTOR 7/5/00

1 OP = operation code. A0~A11 and BA0~BA1 program keys. 2 MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS. 3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after all banks are precharged. 4 BA0~BA1: bank select addresses. If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected. During read, write, row active, and prechage: If BA0 and BA1 are Low, Bank A is selected. If BA0 = Low and BA1 = High, Bank B is selected. If BA0 = High and BA1 = Low, Bank C is selected. If BA0 and BA1 are High, Bank D is selected. 5 A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after t(t RP/tCK + BL +) cycles. 6 Burst stop command valid at every burst length. 7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). Command CKE n-1 CKEn CS RAS CAS WE DQM BA0/ BA1 A10 A9–A0 DQ Note Register Mode register set H * HLL L L X O p c o d e X1 , 2 Refresh Auto refresh H H L L L H X – X X Self refresh Entry H L L L L H X – – 3 Exit L H LHHH X – – 3 H XXX X – – 3 Bank activate H H L L H H X V row address X Read Auto precharge disable HH L H L H XV L column address X Auto precharge enable H 4,5 Write Auto precharge disable HH L H L LXV L column address Valid 4 Auto precharge enable H 4,5 Burst stop H H L H H L X X Active 6 Precharge Selected bank HH L L H LX VL XX 4All banks X H Clock suspend or active power down Entry H L H XXX XX X X XL VVV E x i t L H X XXX Precharge power down mode Entry H L H XXX XX X X XLHHH Exit L H H XXX L VVV DQM Write enable/output enable HH X XXX H XX X X7 Write inhibit/Output High-Z No operation command H X H XXX X XX X X LHHH X

7/5/00 ALLIANCE SEMICONDUCTOR 5 Mode register fields † RFU = 0 during MRS cycle. Register programmed with MRS Address A 1 1 ~ A 1 0 A 9A 8A 7A 6A 5A 4A 3 A 2 A 1 A 0 Function RFU † WBL TM CAS latency BT Burst length Write burst length Burst type A9 Length A3 Type

0 Programmed

1 Interleaved

01 R e s e r v e d

10 R e s e r v e d

A6 A5 A4 Latency A2 A1 A0 BT = 0 BT = 1 0 0 0 Reserved 0 0 0 1 1 0 0 1 Reserved 0 0 1 2 2 01 0 2 0 1 0 4 4 01 1 3 0 1 1 8 8

1 X X Reserved 1 0 0 Reserved Reserved

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Recommended operating conditions † VIL min = –1.5V for pulse widths less than 5 ns. ‡ IOH = –2mA, and IOL = 2mA. Recommended operating conditions apply throughout this document unless otherwise specified. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilit y. Capacitance Notes 1 This parameter is sampled. V CC = VCCQ = 3.3V; f = 1MHz; TA = 23° C; pin under test biased at 1.4 V. 2 Max value is specified for –10, –10F, and –8. 3 For –75 part, Max = 3.5 pF. 4 For –75 part, Max = 3.8 pF. 5 For –75 part, Max = 6.0 pF. Parameter Symbol Min Max Unit Supply voltage VCC,VCCQ 3.0 3.6 V GND 0.0 0.0 V Input voltage VIH 2.0 V CC + 0.3 V VIL –0.3† 0.8 V Output voltage‡ VOH 2.4 – V VOL –0 . 4 V Input leakage current Any input 0V ≤ VIN ≤ VCC IL –5 +5 uA Output leakage current DQs are disabled ≤ VOUT ≤ VCCQ IOZ –5 +5 uA Ambient operating temperature T A 07 0 ° C Parameter Symbol Min Max Unit Input voltage V IN,VOUT –1.0 +4.6 V Power supply voltage V CC,VCCQ –1.0 +4.6 V Storage temperature (plastic) T STG –55 +150 °C Power dissipation P D –1 W Short circuit output current I OUT –5 0 m A Parameter Symbol Min Max Unit Notes Input capacitance: CLK C i1 2.5 4 pF 1, 2, 3 Input capacitance: All other input-only pins Ci2 2.5 5 pF 1, 2, 4 Input/output capacitance C I/O 4.0 6.5 pF 1, 2, 5

7/5/00 ALLIANCE SEMICONDUCTOR 7 IDD specifications and conditions□□□□□ (0° C ≤ TA ≤ 70° C, VDD, VDDQ = +3.3V ± 0.3V) Notes 1I DD specifications are tested after proper initialization of the device. 2I DD is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open. 3I DD tests have VIL = 0V and VIH = 3V . 4I DD current will decrease at lower CAS latencies. This is because the lower the latency , the lower the clock cycle time. 5 Address transitions average one transition every two clock cycles. Parameter Symbol Max Units Notes–75 –8 –10F/10 Operating current: active mode; burst = 2; READ or WRITE; tRC = tRC(min); CAS latency = 3 IDD1 115 95 95 mA 4, 5 Standby current: power-down mode; all banks idle; CKE = low IDD2 222 m A 4 , 5 Standby current: active mode; CKE = high; CS# = high; all banks active after tRCD met; no accesses in progress IDD3 45 35 35 mA 4, 5 Operating current: burst mode; continuous burst; READ or WRITE; all banks active; CAS latency = 3 IDD4 140 130 120 mA 4,5 Auto refresh current: CKE = high; CS# = high tRFC = tRFC(min); CL = 3 IDD5 210 210 190 mA 4, 5 tRFC = 15.625ms; CL = 3 IDD6 50 50 40 mA 4,5 Self-refresh current: CKE ≤ 0.2V I DD7 111 m A 4 , 5

8 ALLIANCE SEMICONDUCTOR 7/5/00

AC parameters common to all waveforms Sym Parameter CAS latency -75 -8 -10F -10 Unit NotesMin Max Min Max Min Max Min Max tRRD Row active to row active delay 15 – 20 – 20 – 20 – ns 1 tRCD RAS to CAS delay time 20 – 20 – 20 – 30 – ns 1 tRP Row precharge 20 – 20 – 20 – 30 – ns 1 tRAS Row active 44 – 50 – 50 – 60 – ns 1 tRC Row cycle time 66 – 70 – 70 – 90 – ns 1 tCDL Last data in to new column address delay 1 – 1 –1–1– C L K 2 tRDL Last data in to row precharge 2 – 2 – 2 – 2 – CLK 2 tBDL Last data in to burst stop 1 – 1 – 1 – 1 – CLK 2 tCCD Column address to column address delay 1 – 1 –1–1– C L K 3 tCK CLK cycle time 37 . 5 –8 – 1 0 – 1 0 – ns 4 21 0 – 1 0– 1 5 – 1 5 – 4 tAC CLK to valid output delay @ 50pF ns 4,5,7 26 – 6– 6 – 6 – 4 , 5 , 7 tOH Output data hold time @ 50 pF 32 . 7 –3 – 3 – 3 – ns 4,5,7 23 – 3– 3 – 3 – 4 , 5 , 7 tCH CLK high pulse width 2.5 – 3 – 3 – 3 – ns 6 tCL CLK low pulse width 2.5 – 3 – 3 – 3 – ns 6 tAS Add setup time 1.5 – 2 – 2 – 2 – ns 6 tAH Add hold time 0.8 – 1 – 1 – 1 – ns 6 tSLZ CLK to output in low Z 1 – 1 – 1 – 1 – ns 5 tSHZ CLK to output in high Z 3– 6 –7 – 7 – 7 ns2– 6 –7 – 7 – 7 tCKH C K E h o l d t i m e 0 . 8 – 1 –1–1– n s tCKS CKE setup time 1.5 – 2 – 2 – 2 – ns tCMH CS, RAS, CAS, WE, DQM hold time 0 . 8 – 1 –1–1– n s tCMS CS, RAS, CAS, WE, DQM setup time 1 . 5 – 2 –2–2– n s tDH Data in hold time 0.8 – 1 – 1 – 1 – ns tDS Data in setup time 1.5 – 2 – 2 – 2 – ns

7/5/00 ALLIANCE SEMICONDUCTOR 9 AC parameters common to all waveforms (continued) Notes 1 Minimum clock cycles = (Minimum time / clock cycle time) rounded up. 2 Minimum delay required to complete write. 3 Column address change allowed every cycle. 4 Parameters dependent on CAS latency . 5I f c l o c k r i s i n g t i m e > 1ns, (tr/2-0.5)ns should be added to parameter. 6 If (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter. 7 Outputs measured at 1.5V with 50pF load only without resistive termination. Burst sequence (BL = 4) Burst sequence (BL = 8) Sym Parameter CAS latency -75 -8 -10 F -10 Unit NotesMin Max Min Max Min Max Min Max tDQD DQM to input data delay 1 – 1 – 1 – 1 – CLK tDQM DQM to data mast during writes 0 – 0 – 0 – 0 – CLK tDQZ DQM to data high Z during reads 2 – 2 –2–2– C L K tDWD Write command to input data delay 0 – 0 –0–0– C L K tDAL Data-in to active command 5 – 5 – 5 – 5 – CLK tMRD Load mode register to active/ refresh command 1 – 1 –1–1– C L K tROH Data-out high Z from precharge/burst stop command 33 –3 – 3 – 3 – C L K 4 22 –2 – 2 – 2 – C L K 4 tCKED CKE to CLOCK disable or power- down entry mode 1 – 1 –1–1– C L K tPED CKE to clock enable or power- down exit mode 1 – 1 –1–1– C L K Initial address Sequential InterleaveA1 A0 0 0 01230123 0 1 12301032 1 0 23012301 1 1 30123210 Initial address Sequential InterleaveA2 A1 A0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210

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Command Pin settings Description Power up The following sequence must be performed prior to normal operation. 1. Apply power, start clock, and assert CKE and DQM high. All other signals are NOP . 2. After power-up, pause for a minimum of 200µs. CKE/DQM = high; all others NOP . 3. Precharge both banks. 4. Perform Mode Register Set command to initialize mode register. 5. Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry . (Steps 4 and 5 may be interchanged.) Mode register set CS = RAS = CAS = WE = low; A0~A11 = opcode The mode register stores the user selected opcode for the SDRAM operating modes. The CAS latency , burst length, burst type, test mode and other vendor specific functions are selected/programmed during the Mode Register Set command cycle. The default setting of the mode register is not defined after power-up. The power-up and mode register set cycle must be executed prior to normal SDRAM operation. Refer to the Mode Register Set table and timing for details. Device deselect and no operation CS = high The SDRAM performs a “no operation” (NOP) when RAS, CAS, and WE = high. Since the NOP performs no operation, it may be used as a wait state in performing normal SDRAM functions. The SDRAM is deselected when CS is high. CS high disables the command decoder such that RAS , CAS, WE and address inputs are ignored. Device deselection is also considered a NOP . Bank activation CS = RAS = low; CAS = WE = high; A0~A10 = row address; BA0~BA1 = bank select The SDRAM is configured with four internal banks. Use the Bank Activate command to select a row in one of the idle banks. Initiate a read or write operation after t RCD(min) from the time of bank activation. Burst read CS = CAS = A10 = low; RAS = WE = high; BA0~BA1 = bank select, A0~A8 = column address; (A9 = don’t care for 8M×8; A8,A9 = don’t care for 4M×16) Use the Burst Read command to access a consecutive burst of data from an active row in an active bank. Burst read can be initiated on any column address of an active row . The burst length, sequence and latency are determined by the mode register setting. The first output data appears after the CAS latency from the read command. The output goes into a high impedance state at the end of the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. T erminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. Burst write CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don’t care for 8M×8; A8,A9 = don’t care for 4M×16) Use the Burst Write command to write data into the SDRAM on consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. UDQM/LDQM ( ×16), DQM (×8) operation Use DQM to mask input and output data on a cycle-by-cycle basis. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency).

7/5/00 ALLIANCE SEMICONDUCTOR 11 Device operation (continued) Command Pin Settings Description Burst stop CS = WE = low; RAS = CAS = high Use burst stop to terminate burst operation. This command may be used to terminate all legal burst lengths. Bank precharge CS = A10 = RAS = WE = low; CAS = high; A11 = bank select; A0~A9 = don’t care The Bank Precharge command precharges the bank specified by BA0 and BA1. The precharged bank is switched from active to idle state and is ready to be activated again. Assert the precharge command after t RAS(min) of the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. Precharge all CS = RAS = WE = low; CAS = A10 = high; BA0~BA1 = bank select; A0~A9 = don’t care The Precharge All command precharges all four banks simultaneousl y. All four banks are switched to the idle state on precharge completion. Auto precharge CS = CAS = WE (write) = low; RAS = WE (read) = A10 = high; BA0~BA1 = bank select; A0~A9 = column address; (A9 = don’t care for 2M×8; A8,A9 = don’t care for 1M×16) During auto precharge, the SDRAM adjusts internal timing to satisfy tRAS(min) and tRP for the programmed CAS latency and burst length. Couple the auto precharge with a burst read/write operation by asserting A10 to a high state at the same time the burst read/write commands are issued. At auto precharge completion, the specified bank is switched from active to idle state. Note that no new commands to the bank can be issued until the specified bank achieves the idle state. Auto precharge doesn’t work with full-page burst. Clock suspend/power down mode entry CKE = low When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. If all banks are idle and CKE goes low, the SDRAM enters power down mode at the next clock cycle. When in power down mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Clock suspend/power down mode exit CKE = high Resume internal clock operation by asserting CKE high before the rising edge of CLK. Subsequent commands can be issued one clock cycle after the end of the Exit command. Auto refresh CS = RAS = CAS = low; WE = CKE = high; A0~A11 = don’t care SDRAM storage cells must be refreshed every 64ms to maintain data integrity . Use the Auto Refresh command to refresh all rows in all banks of the SDRAM. The row address is provided by an internal counter which increments automatically . Auto refresh can only be asserted when all four banks are idle and the device is not in the power down mode. The time required to complete the auto refresh operation is t RC(min). Use NOPs in the interim until the auto refresh operation is complete. This is the most common refresh mode. It is typically performed once every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All four banks will be in the idle state after this operation. Self refresh CS = RAS = CAS = CKE = low; WE = high; A0~A11 = don’t care Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally . Self refresh entry is allowed only when all four banks are idle. The internal clock and all input buffers with the exception of CKE are disabled in this mode. Exit self refresh by restarting the external clock and then asserting CKE high. NOP’s must follow for a time of t RC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 4096 auto refresh cycles immediately after exiting self refresh.

12 ALLIANCE SEMICONDUCTOR 7/5/00

Mode register set command waveform MRS can be issued only when both banks are idle. Precharge waveforms Precharge can be asserted after t RAS (min). The selected bank will enter the idle state after t RP.. The earliest assertion of the precharge command without losing any burst data is show below. (normal write; BL = 4) (normal read; BL = 4) Auto precharge waveforms A10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; BL = 4) (read with auto precharge; BL = 4) * The row active command of the precharge bank can be issued after t RP from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal; other bank is described below. CLK CMD PRE MRS ACT tRP tRSC(min) CLK CMD DQ WE D0 D1 D2 D3 PRE CLK CMD DQ(CL2) DQ(CL3) Read data PRE Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 CLK CMD DQ WE D0 D1 D2 D3 Auto precharge starts* Auto precharge starts* CLK CMD DQ(CL2) DQ(CL3) Read data Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

7/5/00 ALLIANCE SEMICONDUCTOR 13 Concurrent Auto-P Waveforms According to Intel™’s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (A) RD-P interrupted by RD in another bank (CL = 3, BL = 4) (B) RD-P interrupted by WR in another bank (CL = 2, BL = 8) (C) WR-P interrupted by RD in another bank (CL = 2, BL = 4) * The row active command of the precharge bank can be issued after t RP from this point. CLK CMD RD-P(A) DQ A0 A1 B0 B1 B2 B3 Bank A Precharge Starts * RD (B) CLK CMD RD-P (A) DQ QA0 QA1 DN(B0) D(B1) D(B2) Bank A Precharge Starts * WR (B) DQM D(B7) CLK CMD WRP (A) DQ D(A0) D(A1) QB0 QB1 QB2 Bank A Precharge Starts * RD (B) QB3

14 ALLIANCE SEMICONDUCTOR 7/5/00

(D) WR-P Interrupted by WR in another bank (CL = 3, BL = 4) * The row active command of the precharged bank can be issued after t RP from this point. Clock suspension read waveforms (BL = 8) CLK CMD WRP(A) DQ DA0 DA1 DA2 DB0 DB1 WR (B) DB2 DB3 Bank A Precharge Starts * CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 Q6OPEN OPEN CLK external CLK internal CKE DQM DQ Q 1 Q2 Q3 Q4 Q6 OPEN CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 Q6Q5

7/5/00 ALLIANCE SEMICONDUCTOR 15 Clock suspension write waveforms (BL = 8) Read/write interrupt timing read interrupted by read (CL = 2, BL = 4) tCCD = CAS to CAS delay (= 1 CLK) CLK external CLK internal CKE DQM DQ D 1 D2 D3 DQM Mask D5 D6 CKE Mask CLK external CLK internal CKE DQM DQ DQM Mask CKE Mask D1 D2 D3 D5 D6 CLK external CLK internal CKE DQM DQ D1 D2 D3 D4 D6D5 CLK CMD ADD DQ (CL2) DQ (CL3) Read data Read data AB QA0 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3tCCD

16 ALLIANCE SEMICONDUCTOR 7/5/00

write interrupted by write (BL = 4) tCCD = CAS to CAS delay (= 1 CLK) tCDL = last address in to new column addres delay (= 1 CLK) write interrupted by read (CL = 2, BL = 4) tCCD = CAS to CAS delay (= 1 CLK) tCDL = last address in to new column addres delay (= 1 CLK) read interrupted by write (CL = 3, BL = 4) * To prevent bus contention, maintain a gap between data in and data out. Burst termination Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency . When Burst Stop is asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneousl y. Burst stop command waveform, read cycle (BL = 8) CLK CMD ADD DQ DA0 DB0 DB1 DB2 DB3 A0 B0 Write data Write data tCCD tCDL tCDL CLK CMD ADD DQ (CL2) DQ (CL3) Write data Read data AB DA0 QB0 QB1 QB2 QB3 DA0 QB0 QB1 QB2 QB3 tCCD CLK CMD DQM DQ Read data Write data* D0 D1 D2 D3Q0 CLK CMD DQ (CL = 2) DQ (CL = 3) Read data Burst stopRead data Q0 Q1 Q2 Q0 Q1 Q2

7/5/00 ALLIANCE SEMICONDUCTOR 17 write cycle Precharge command A Precharge command can be used to interrupt burst read/write operation during the read cycle. During RD, burst read is terminated and o/p goes to High Z after CAS latency . The same bank can be activated after t RP. During write, burst write operation is terminated immediately . Data written two cycles prior to the precharge command will be correctly stored. Set DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid data. read cycle (CL = 2) read cycle (CL = 3) write cycle (BL = 8) CLK CMD DQ Burst stopWrite data (CL = 2,3) Q0 Q1 Q2 Q3 CLK CMD DQ Read data PRE ACT Q0 Q1 Q2 Q3 tRP CLK CMD DQ Read data PRE ACT Q0 Q1 Q2 Q3 CLK CMD DQ Write data PRE ACT D0 D1 D2 Q4 tRP Masked DQM

18 ALLIANCE SEMICONDUCTOR 7/5/00

† If A10 = High, then BA0/BA1 = don’t care; if A10 = l ow, then BA0/BA1 = bank select. Self refresh waveform /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 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/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CLK CS RAS CAS WE BA0/BA1 A0–A9,A11 DQM CKE DQ Precharge all banks tRC Self refresh entry Self refresh exit Arbitrary cycle Self refresh cycle /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0A10 RAaRAa

7/5/00 ALLIANCE SEMICONDUCTOR 19 Power down mode waveform Enter power down mode by pulling CKE low. All input/output buffers (except CKE buffer are turned off in power down mode. When CKE goes high, command input must be equal to no operation at next CLK rising edge. Read/write waveform (BL = 8, CL = 3) Power down mode Active standby /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CLK CS RAS CAS WE BA0/BA1 A10 A0–A9,A11 DQM CKE DQ RAa RAa CAa CAxRAa RAa Bank activate Power down mode entry Power down mode exit NOP Power down mode entry Power down mode Precharge standby NOP Power down mode exit Bank activate Ab0 RAa /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CLK CS RAS CAS WE BA0/BA1 A10 A0-A9,A11 DQM CKE DQ CAa RAa CAb RAb RAb tRAS tRP tRP Aa0 Aa5Aa4Aa3Aa2Aa1 Ab5Ab4Ab3Ab2Ab1 Bank activate Read QQ Q Q QQ DD D D DD Bank activate Write Precharge tRP

20 ALLIANCE SEMICONDUCTOR 7/5/00

Burst read/single write waveform (BL = 4, CL = 3) Interleaved bank read waveform (BL = 4, CL = 3) † BA0 and BA1 together determine which bank undergoes operations. Single /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 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/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 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7/5/00 ALLIANCE SEMICONDUCTOR 21 Interleaved bank read waveform (BL = 4, CL = 3, Autoprecharge) †BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins. Interleaved bank read waveform (BL = 8, CL = 3) †BA0 and BA1 together determine which bank undergoes operations. /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 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QAc0 QAc1 Bank A Bank B Active Read Precharge Read Precharge Active PrechargeActive Read BA0/BA1† /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Bank Bank Bank Bank BankBank /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Bank BankBank

22 ALLIANCE SEMICONDUCTOR 7/5/00

Interleaved bank read waveform (BL = 8, CL = 3, Autoprecharge) † BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins. Interleaved bank write waveform (BL = 8) † BA0 and BA1 together determine which bank undergoes operations. /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 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/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CLK CS RAS CAS WE A10 A0-A9,A11 DQM CKE DQ tRC tRAS tRP tRAS tRCD tRCD tRCD CAaRAa RBb RBb CAb CAc RAa RAc RAc DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 Active Write Active WriteBank A Bank B Active WritePrecharge Precharge BA0/BA1† /i0/i0/i0 /i0/i0/i0 Bank Bank Bank Bank Bank Bank

7/5/00 ALLIANCE SEMICONDUCTOR 23 Interleaved bank write waveform (BL = 8, Autoprecharge) † BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0 /i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CLK CS RAS CAS WE A10 A0-A9.A11 DQM CKE DQ Active Write Active Write Bank A Bank B Active WriteAP Bank A AP Bank B tRC tRAS tRP tRAS tRAS tRCD tRCDtRCD CAaRAa RBb RBb CAb CAc RAa RAc RAc DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 BA0/BA1† Bank Bank BankBankBank Bank

24 ALLIANCE SEMICONDUCTOR 7/5/00

Ordering information

Part –75 –8 –10 –10F TSOP II, 400 mil, 54-pin AS4LC8M8S0-75TC AS4LC8M8S0-8TC AS4LC8M8S0-10TC AS4LC8M8S0-10FTC TSOP II, 400 mil, 54-pin AS4LC4M16S0-75TC AS4LC4M16S0-8TC AS4LC4M16S0-10TC AS4LC4M16S0-10FTC AS4 LC XXXS0 –XX T C DRAM prefix LC = 3.3V CMOS Device number for synchronous DRAM 1/frequency Package (device dependent): TSOP II 400 mil, 54 pin Commercial temperature range, 0° C to 70 ° C 54-pin TSOP II Min (mm) Max (mm) A– 1.2 A1 0.05 – A2 0.95 1.05 b0 . 3 0 0.45 c 0.12 0.21 D 22.12 22.32 E 10.03 10.29 e 0.80 (typical) He 11.56 11.96 l 0.40 0.60 D He 123456789 1 0 1 1 1 2 1 3 1 4 54 53 52 51 50 49 48 47 46 45 44 43 42 41 15 16 40 39 17 18 19 20 38 37 36 35 c l e 54-pin TSOP II 0–5° 22 23 24 25 33 32 31 30 E A b 26 27 29 28 - Input reference levels of VIH = 2.0V and VIL = 0.8V - Output reference levels = 1.4V - Input rise and fall times: 2 ns CLOAD = 50 pF DOUT +1.4V Figure A: Equivalent output load 50WZ0 = 50W