AS4LC256K16EO-35

AS4LC256K16EO ALSC | Alldatasheet

Document overview

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• PDF pages: 25

Technical content

Features

• Organization: 262,144 words × 16 bits
• High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time
• Low power consumption - Active: 280 mW max (AS4LC256K16EO-35) - Standby: 2.8 mW max, CMOS I/O (AS4LC256K16EO- 35)
• EDO page mode
• 5V I/O tolerant
• 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self refresh
• Read-modify-write
• LVTTL-compatible, three-state I/O
• JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II
• 3.3V power supply
• Latch-up current > 200 mA Pin arrangement GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 SOJ NC LCAS UCAS OE GND Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC Vcc VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE GND TSOP II AS4LC256K16EO AS4LC256K16EO Pin designation Pin(s)

Description

Column address strobe, upper byte LCAS Column address strobe, lower byte WE Read/write control VCC Power (3.3V ± 0.3V) GND Ground Selection guide Symbol AS4LC256K16EO-35 AS4LC256K16EO-45 AS4LC256K16EO-60 Unit Maximum RAS access time tRAC ns Maximum column address access time tCAA ns Maximum CAS access time tCAC ns Maximum output enable (OE) access time tOEA ns Minimum read or write cycle time tRC 100 ns Minimum EDO page mode cycle time tPC ns Maximum operating current ICC1 mA Maximum CMOS standby current ICC2 200 200 200 µA

4/11/01; V.1.1 Alliance Semiconductor P. 2 of 25 Functional description The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:

• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
• Self refresh cycles The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 3.3V ± 0.3V tolerance and direct interface with TTL logic families. Logic block diagram Recommended operating conditions (Ta = 0°C to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V Input voltage VIH 2.0 VCC + 1 V VIL –1.0 0.8 V REFRESH CONTROLLER 512×512×16 ARRAY (4,194,304) SENSE AMP VCC GND ADDRESS BUFFERS ROW DECODER COLUMN DECODER RAS CLOCK GENERATOR SUBSTRATE BIAS GENERATOR DATA I/O BUFFER OE RAS UCAS WE CLOCK GENERATOR WE LCAS I/O0 to I/O15 CAS CLOCK GENERATOR

4/11/01; V.1.1 Alliance Semiconductor P. 3 of 25 Absolute maximum ratings NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso- lute maximum rating conditions for extended periods may affect reliability. DC electrical characteristics Parameter Symbol Min Max Unit Input voltage Vin -1.0 +7.0 V Output voltage Vout -1.0 +7.0 V Power supply voltage VCC -1.0 +7.0 V Operating temperature TOPR +70 Storage temperature (plastic) TSTG -55 +150 Soldering temperature × time TSOLDER 260 × 10 oC × sec Power dissipation PD W Short circuit output current Iout mA Latch-up current 200 mA Parameter Symbol Test conditions -35 -45 -60 Unit Note Min Max Min Max Min Max Input leakage current IIL 0V ≤ Vin ≤ +5.5V pins not under test = 0V -10 -10 -10 µA Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ +5.5V -10 -10 -10 µA Operating power supply current ICC1 RAS, UCAS, LCAS, address cycling; tRC=min mA 1,2 TTL standby power supply current ICC2 RAS = UCAS = LCAS = VIH 200 200 200 µA Average power supply current, RAS refresh mode ICC3 RAS cycling, UCAS = LCAS = VIH, tRC = min mA EDO page mode average power supply current ICC4 RAS=UCAS=LCAS=VIL, address cycling: tSC = min mA 1,2 CMOS standby power supply current ICC5 RAS=UCAS=LCAS= VCC - 0.2V 400 400 400 µA CAS-before-RAS refresh power supply current ICC6 RAS, UCAS, LCAS, cycling; tRC = min mA Output Voltage VOH IOUT = -2 mA 2.4 2.4 2.4 V VOL IOUT = 2 mA 0.4 0.4 0.4 V Self refresh current ICC7 RAS = UCAS = LCAS=VIL, WE = OE = A0-A8 = VCC-0.2V, DQ0-DQ15 = VCC-0.2V, 0.2V are open 400 400 400 µA

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4/11/01; V.1.1 Alliance Semiconductor P. 5 of 25 AC parameters common to all waveforms Read cycle Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tRC Random read or write cycle time 100 ns tRP RAS precharge time ns tRAS RAS pulse width 75K 75K 75K ns tCAS CAS pulse width ns tRCD RAS to CAS delay time ns tRAD RAS to column address delay time ns tRSH(R) CAS to RAS hold time (read cycle) ns tCSH RAS to CAS hold time ns tCRP CAS to RAS precharge time ns tASR Row address setup time ns tRAH Row address hold time ns tT Transition time (rise and fall) 1.5 1.5 1.5 ns 4,5 tREF Refresh period ms tCLZ CAS to output in low Z ns Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tRAC Access time from RAS ns tCAC Access time from CAS ns 6,13 tAA Access time from address ns 7,13 tAR(R) Column add hold from RAS ns tRCS Read command setup time ns tRCH Read command hold time to CAS ns tRRH Read command hold time to RAS ns tRAL Column address to RAS Lead time ns tCPN CAS precharge time ns tOFF Output buffer turn-off time ns 8,10

4/11/01; V.1.1 Alliance Semiconductor P. 6 of 25 Write cycle Read-modify-write cycle Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tASC Column address setup time ns tCAH Column address hold time ns tAWR Column address hold time to RAS ns tWCS Write command setup time ns tWCH Write command hold time ns tWCR Write command hold time to RAS ns tWP Write command pulse width ns tRWL Write command to RAS lead time ns tCWL Write command to CAS lead time ns tDS Data-in setup time ns tDH Data-in hold time ns tDHR Data-in hold time to RAS ns Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tRWC Read-write cycle time 105 115 120 ns tRWD RAS to WE delay time ns tCWD CAS to WE delay time ns tAWD Column address to WE delay time ns tRSH(W) CAS to RAS hold time (write) ns tCAS(W) CAS pulse width (write) ns

4/11/01; V.1.1 Alliance Semiconductor P. 7 of 25 EDO page mode cycle Refresh cycle Output enable Self refresh cycle Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tPC Read or write cycle time (fast page) ns tCAP Access time from CAS precharge ns tCP CAS precharge time (fast page) ns tPCM EDO page mode RMW cycle ns tCRW Page mode CAS pulse width (RMW) ns tRASP RAS pulse width 75K 75K 75K ns Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tCSR CAS setup time (CAS-before-RAS) ns tCHR CAS hold time (CAS-before-RAS) ns tRPC RAS precharge to CAS hold time ns tCPT CAS precharge time (CAS-before-RAS counter test) ns Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tROH RAS hold time referenced to OE ns tOEA OE access time ns tOED OE to data delay ns tOEZ Output buffer turnoff delay from OE ns tOEH OE command hold time ns Std Symbol Parameter -35 -45 -60 Unit Notes Min Max Min Max Min Max tRASS RAS pulse width (CBR self refresh) 100K 100K 100K ns tRPS RAS precharge time (CBR self refresh) ns tCHS CAS hold time (CBR self refresh) ns

4/11/01; V.1.1 Alliance Semiconductor P. 8 of 25 Notes ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC ≥ tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled and not 100% tested. Key to switching waveform Read cycle waveform Undefined/don’t care Falling input Rising input tRAS tRC tRP tRSH tRAD tRCH tOFF RAS UCAS, Address WE OE I/O Col Address Row Address tCRP tCSH tRCD tASC tCAH tCAS tAR tRAL tRAH tRCS tAA tCLZ tRRH Data Out tASR tRAC tROH tOEA tCAC tOEZ LCAS

4/11/01; V.1.1 Alliance Semiconductor P. 9 of 25 Upper byte read cycle waveform Lower byte read cycle waveform tRAS tRC tRP tCRP tRCD tRSH tCSH tCRP tCRP tASR tRAH tRAD tRAL tCAH tRCS tRRH tRCH tCLZ tCAC tOEZ tOFF Row Column Data Out RAS UCAS LCAS Address WE OE Upper I/O Lower I/O tROH tASC tRAC tOEA tAA tCAS tRAS tRC tRP tCRP tRCD tRSH tCRP tCRP tASR tRAH tRAD tRAL tCAH tRRH tRCH tCLZ tCAC tRAC tOEZ tOFF Row Column Data Out RAS LCAS UCAS Address WE OE Upper I/O Lower I/O tCSH tASC tRCS tROH tOEA tAA tCAS

4/11/01; V.1.1 Alliance Semiconductor P. 10 of 25 Early write cycle waveform Upper byte early write cycle waveform tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAH tRAD tASC tAWR tCAH tWCS tCWL tRWL tWCH tWP tDS tDH tDHR Col Address Data In RAS UCAS, Address WE OE I/O Row Address tWCR tRAL tASR LCAS tRAS tRC tRP tRAH tRAD tAWR tCRP tASC tCAH tRSH tRCD tCSH tCRP tCRP tRPC tRWL tWCS tWP tDS tDH tDHR Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tASR tRAL tCAS tCWL tWCH tWCR

4/11/01; V.1.1 Alliance Semiconductor P. 11 of 25 Lower byte early write cycle waveform Write cycle waveform (OE controlled) tRC tRAS tRP tRAD tAWR tCRP tRPC tCRP tASC tCAH tRSH tRCD tCSH tCRP tRWL tWP tWCS tWCR tWCH tDS tDH tDHR Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tCWL tRAH tCAS tRAL tASR Row Address tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAH tRAL tRAD tCAH tCWL tRWL tWCR tOEH tOED tDS tDH Data In RAS UCAS, Address WE OE I/O Col Address tDHR tWP tASC tAWR tASR LCAS

4/11/01; V.1.1 Alliance Semiconductor P. 12 of 25 Upper byte write cycle waveform (OE controlled) Lower byte write cycle waveform (OE controlled) tRAS tRC tRP tRAL tRAD tASC tCAH tCSH tCRP tCRP tRPC tRWL tWP tOEH tDS tDH tOED Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tCRP tAWR tRAH tRCD tRSH tCWL tASR tCAS tRC tRAS tRP tRAH tRAD tACS tCAH tRSH tCSH tCRP tCRP tRPC tRWL tWP tOEH tDS tDH Row Address Column Address Data In RAS Address LCAS UCAS WE OE Upper I/O Lower I/O tCRP tRCD tCAS tCWL tAWR tRAL tASR

4/11/01; V.1.1 Alliance Semiconductor P. 13 of 25 Read-modify-write cycle waveform tRAS tRWC tRP tCRP tRSH tRCD tCSH tCAS tRAD tRAL tAR tCAH tCWL tCWD tRWL tAWD tWP tOEA tCLZ tCAC tAA tDS tDH Row Address Col Address Data In Data Out RAS UCAS, Address WE OE I/O tRAH tRWD tRCS tRAC tOEZ tOED tASC tASR LCAS

4/11/01; V.1.1 Alliance Semiconductor P. 14 of 25 Upper byte read-modify-write cycle waveform tRWC tRAS tRP tCRP tRSH tRCD tCSH tCAS tCRP tCRP tRPC tRAL tCAH tRWL tAWD tWP tCWD tOEA tDS tCLZ tAA tRAC tCAC tOEZ tOED Row Column Address Data In Data Out Data Out RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tRWD tCWL tOED tRCS tRAH tASR tACS tRAD

4/11/01; V.1.1 Alliance Semiconductor P. 15 of 25 Lower byte read-modify-write cycle waveform tWP tRWC tRAS tRP tCRP tRPC tCRP tRSH tRCD tCSH tCAS tCRP tRAL tRAD tACS tCAH tRCS tRWL tOEA tOED tDS tCLZ tOEZ Row Column Address Data In Data Out RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tRAH tAWD tCWL tCWD tCAC tRWD tASR tAA tRAC Data Out

4/11/01; V.1.1 Alliance Semiconductor P. 16 of 25 EDO page mode read cycle waveform EDO page mode byte read cycle waveform Row tRASP tRP tCRP tRCD tCAS tCSH tRSH tPC tASR tRAD tRCH tRCS tRRH tRCH tOEA tOEA tAA tRAC tCAC tCAP Data Out Data Out Col Address Col Address Col Address RAS UCAS, Address WE OE I/O tAR tRAH tASC tRAL tRCS tCLZ tCP LCAS tCAC tCAH tRASP tRP tCAS tCSH tRSH tCAS tCRP tCRP tCP tCAS tCP tRPC tRAH tRAD tASC tCAH tASC tRCS tOEA tOEZ tOFF tCAC tRAC tOFF tOEZ tCLZ tAA tCAC tCAP tOFF tOEZ Row Column 1 Column 2 Column n Data Out 1 Data Out n Data Out 2 RAS UCAS LCAS Address WE OE Lower I/O Upper I/O tCLZ tCAP tAA tCLZ tCAC tOEA tRCS tRCH tOEA tCAH tRAL tPC tPC tCAH tASC tRCD tRCH tRCS tASR tCRP tAA

4/11/01; V.1.1 Alliance Semiconductor P. 17 of 25 EDO page mode early write cycle waveform EDO page mode byte early write cycle waveform tRAH tRASP tRWL tASC tWCS tCP tRAL tWCH tCWL tWP tDS tDH tOED tCAS Row address Col address Col Address Col Address Data In Data In Data In RAS UCAS, Address WE OE I/O tPC tCAH tCSH tRCD tOEH tHDR tAR tRAD tASR tCRP LCAS tRSH tRASP tRP tCAS tCSH tRSH tCAS tCRP tCRP tCP tCP tRPC tRAD tASC tRAL tWCS tCWL tWCS tWCS tCWL tRWL tDS tDH tDS tDH tDS tDH Row Column 1 Column 2 Column n Data In 1 Data In n Data In 2 RAS UCAS LCAS Address WE OE Lower I/O Upper I/O tPC tRAH tWCH tWP tWP tCWL tWP tWCH tCAH tRCD tPC tCAH tCAH tASR tCRP tASC tASC tCAS tWCH

4/11/01; V.1.1 Alliance Semiconductor P. 18 of 25 EDO page mode read-modify-write cycle waveform CAS-before-RAS refresh cycle waveform (WE = VIH) RAS only refresh cycle waveform (WE = OE =VIH or VIL) tRASP tRP tRCD tCSH tCAS tCP tCRP tASR tCAH tCAH tRAL tCAH tCWD tAWD tCWD tCWL tCWD tAWD tRWL tWP tOEZ tOEA tRAC tDS tCLZ tCAC tCAP Row Ad Col Ad Col Address Col Ad Data Out Data In Data In Data Out Data Out Data In RAS UCAS, Address WE OE I/O tRAD tRAH tRWD tRCS tCWL tOEA tAA tDH tDS tCLZ tCAC tCLZ tCAC tOED tPCM LCAS tRP tRC tRAS tRPC tCPN tCSR tCHR tOFF RAS UCAS, I/O LCAS tRAS tRP tRC tCRP tRPC tARS tRAH Row Address RAS UCAS, Address LCAS

4/11/01; V.1.1 Alliance Semiconductor P. 19 of 25 EDO page mode byte read-modify-write cycle tRASP tRP tRCD tCAS tCSH tCRP tCP tCP tCAH tASC tCAH tASC tRAL tCWD tCWL tCWL tCWD tWP tRWL tOEA tDH tOEZ tDH tCLZ tCAC tAA tOEZ Data Out 1 Data In n Data Out n Data Out 2 Data In 2 R C 1 C 2 C n RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tPCM tCAS tRSH tCAS tAWD tASC tWP tCWL tWP tOEA tOEA tOED tDS tCAP tDS tOED tOEZ tCLZ tDS tAA tCAC tCLZ tCRP tRAD tRAH tASR tRCS tRWD tRAC Data In 1 tCAC tCAH tAWD tAWD tCWD tDH tAA tOED

4/11/01; V.1.1 Alliance Semiconductor P. 20 of 25 Hidden refresh cycle (read) waveform Hidden refresh cycle (write) waveform tRAS tRC tPR tRAS tRC tPR tCRP tRCD tRSH tCRP tCHR tASR tRAD tASC tRRH tOEA tCLZ tCAC tOEZ tOFF Col Address Row Data Out RAS CAS Address WE OE I/O tAR tRAH tRAC tAA tRCS tRAS tRC tRP tCRP tRCD tRSH tASR tRAH tRAD tAR tCAH tWCS tWCH tDS tDH Data In Col Address Row Address RAS UCAS, Address WE I/O OE tASC tRWL tWCR tWP tDHR tRAL LCAS

4/11/01; V.1.1 Alliance Semiconductor P. 21 of 25 CAS-before-RAS refresh counter test cycle waveform tRAS tRSH tRP tCSR tCHR tCPT tCAS tCAH tCLZ tCAC tRCH tRRH tROH tRWL tCWL tWCS tWP tWCH tDS tDH tRCS tOEA tDS tDH Col Address Data Out Data In Data Out Data In RAS UCAS, Address I/O WE OE WE I/O OE WE OE I/O tOED t AA tCLZ tCAC tOEZ tWP tCWL tRCS tAA tOFF tAWD tCWD tRAL Read Cycle Write Cycle Read-Write Cycle LCAS tOEA

4/11/01; V.1.1 Alliance Semiconductor P. 22 of 25 CAS-before-RAS self refresh cycle Typical DC and AC characteristics tRP tRASS tRPC tCP tCHS tCEZ RAS UCAS, DQ LCAS tRPS tCSR tRPC Supply voltage (V) 2.7 3.6 3.9 3.3 3.0 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 Normalized access time Normalized access time tRAC Ambient temperature (°C) –55 125 –10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 Normalized access time Normalized access time tRAC Load capacitance (pF) 200 250 150 100 100 Typical access time Typical access time tRAC vs. ambient temperature Ta vs. load capacitance CL vs. supply voltage VCC Ta = 25°C Supply voltage (V) 2.7 3.6 3.9 3.3 3.0 0.0 Supply current (mA) Typical supply current ICC Ambient temperature (°C) –55 125 –10 0.0 Supply current (mA) Typical supply current ICC Cycle rate (MHz) 0.0 Power-on current (mA) Typical power-on current IPO vs. ambient temperature Ta vs. cycle rate 1/tRC vs. supply voltage VCC

4/11/01; V.1.1 Alliance Semiconductor P. 23 of 25 Supply voltage (V) 2.7 3.6 3.9 3.3 3.0 Refresh current (mA) Typical refresh current ICC3 Ambient temperature (°C) 0.0 Refresh current (mA) Typical refresh current ICC3 Supply voltage (V) 2.7 3.6 3.9 3.3 3.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 Stand-by current (mA) Typical TTL stand-by current ICC2 vs. Ambient temperature Ta vs. supply voltage VCC vs. supply voltage VCC Ambient temperature (°C) 0.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 Stand-by current (mA) Typical TTL stand-by current ICC2 Output voltage (V) 0.0 1.5 2.0 1.0 0.5 0.0 Output sink current (mA) Typical output sink current IOL Output voltage (V) 0.0 3.0 4.0 2.0 1.0 0.0 Output source current (mA) Typical output source current IOH vs. output voltage VOL vs. output voltage VOH vs. ambient temperature Ta EDO page mode current (mA) Ambient temperature (°C) 0.0 EDO page mode current (mA) Typical EDO page mode current ICC4 Supply voltage (V) 2.7 3.6 3.9 3.3 3.0 0.0 Typical EDO page mode current ICC4 vs. supply voltage VCC vs. ambient temperature Ta

4/11/01; V.1.1 Alliance Semiconductor P. 24 of 25 Package dimensions Capacitance ƒ = 1 MHz, Ta = room temperature, VCC = 3.3V ± 0.3V) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN1 A0 to A8 Vin = 0V pF CIN2 RAS, UCAS, LCAS, WE, OE Vin = 0V pF I/O capacitance CI/O I/O0 to I/O15 Vin = Vout = 0V pF 44-pin TSOP II Min (mm) Max (mm) A 1.2 0.05 0.95 1.05 b 0.30 0.45 c 0.127 (typical) D 18.28 18.54 E 10.03 10.29 He 11.56 11.96 e 0.80 (typical) l 0.40 0.60 D He 9 10 13 14 44 43 42 41 40 39 38 37 36 35 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l e 44-pin TSOP II 0–5° E A b 40-pin SOJ 400 mil Min Max A 0.128 0.148 0.026 1.105 1.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.020 1.035 E 0.370 (typical) 0.395 0.405 0.435 0.445 e 0 050 (typical) e D Pin 1 b B c E Seating Plane A 40-pin SOJ

4/11/01; V.1.1 Alliance Semiconductor P. 25 of 25 Ordering codes Part numbering system Package \\ Access time 35 ns 45 ns 60 ns Plastic SOJ, 400 mil, 40-pin AS4LC256K16E0-35JC AS4LC256K16E0-45JC AS4LC256K16EO-60JC TSOP II, 400 mil, 40/44-pin AS4LC256K16EO-35TC AS4LC256K16EO-45TC AS4LC256K16EO-60TC AS4LC 256K16E0 –XX X C 3.3V DRAM prefix Device number RAS access time Package: J = SOJ T = TSOP II Commercial temperature range, 0°C to 70 °C