AS4LC1M16S0

AS4LC1M16S0 ALSC | Alldatasheet

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Technical content

Features

• Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address
• All signals referenced to positive edge of clock, fully synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed - 143/125/100 MHz - 7/8/10 ns clock access time
• Low power consumption - Active: 576 mW max - Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 32 ms refresh interval
• 4096 refresh cycles, 64 ms refresh interval LEGEND 2M × 8 1M × 16 Configuration 1M × 8 × 2 banks 512K × 16 × 2 banks Refresh Count 2K/4K 2K/4K Row Address (A0 – A10) (A0 – A10) Bank Address 2 (BA) 2 (BA) Column Address 512 (A0 – A8) 256 (A0 – A7)

5/21/01; v.1.1 Alliance Semiconductor P. 2 of 29 AS4LC2M8S1 AS4LC1M16S1 Functional description The AS4LC2M8S1, AS4LC2M8S0, and AS4LC1M16S1, AS4LC1M16S0 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288 words × 16 bits × 2 banks (2048 rows × 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data (512 bytes for 2M × 8 and 256 bytes for 1M × 16) without selecting a new column address. The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation; and (3) the capability to change column-address randomly on every clock cycle during burst access. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. SDRAM commands and functions are decoded from control inputs. Basic commands are as follows: Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1/ AS4LC2M8S0 have 44 pins, and the AS4LC1M16S1/ AS4LC1M16S0 have 50 pins. All devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL compatible. Logic block diagram † For AS4LC2M8S1/AS4LC2M8S0, Banks A and B will read 1M × 8 (2048 × 512 × 8).

• Mode register set
• Deactivate bank
• Deactivate all banks
• Select row; activate bank
• Select column; write
• Select column; read
• Deselect; power down
• CBR refresh
• Auto precharge with read/write
• Self-refresh RAS CAS WE CLK CKE Clock generator Mode register Command decoder Control logic Row address buffer Refresh counter Column address buffer Burst counter Row decoder Sense amplifier Column decoder and latch circuit Data control circuit Latch circuit Input and output buffer DQ DQMU/DQML CS Bank select A11 Bank B† Bank A† 512K × 16 (2048 × 256 × 16) 512K × 16 (2048 × 256 × 16) A[10:0]

5/21/01; v.1.1 Alliance Semiconductor P. 3 of 29 Pin descriptions Pin Name

Description

All operations synchronized to rising edge of CLK. CKE Clock enable Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. If both banks are idle and CKE goes low, the SDRAM will enter power down mode from the next clock cycle. When in power down mode and CKE is low, no input commands will be acknowledged. To exit power down mode, raise CKE high before the rising edge of CLK. CS Chip select Enables or disables device operation by masking or enabling all inputs except CLK, CKE, UDQM/LDQM (×16), DQM (×8). A0~A10 Address Row and column addresses are multiplexed. Row address: A0~A10. Column address (2M × 8): A0~A8. Column address (1M × 16): A0~A7. A11 Bank select Memory cell array is organized in 2 banks. A11 selects which internal bank will be active. A11 is latched during bank activate, read, write, mode register set, and precharge operations. Asserting A11 low selects Bank A; A11 high selects Bank B. RAS CAS WE Row address strobe Column address strobe Write enable Command inputs. RAS, CAS, and WE, along with CS, define the command being entered. ×8: DQM ×16: UDQM, LDQM Output disable/ write mask Controls I/O buffers. When DQM is high, output buffers are disabled during a read operation and input data is masked during a write operation. DQM latency is 2 clocks for Read and 0 clocks for Write. For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM controls the upper byte (DQ8 – 15). UDQM and LDQM are considered to be in the same state when referred to jointly as DQM. DQ0~DQ15 Data input/output Data inputs/outputs are multiplexed. VCC/VSS Power supply/ground Power and ground for core logic and input buffers. VCCQ/VSSQ Data output power/ground Power and ground for data output buffers.

5/21/01; v.1.1 Alliance Semiconductor P. 4 of 29 AS4LC2M8S1 AS4LC1M16S1 Operating modes OP= operation code. A0~A11 see page 5. MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS. Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after both banks are precharged. A11: bank select address. If low during read, write, row active and precharge, bank A is selected. If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge. A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after tRP from the end of the burst. Burst stop command valid at every burst length except full-page burst. DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). Command CKEn-1 CKEn CS RAS CAS WE DQM A11 A10 A9–A0 Note Mode register set H X L L L L X Op code 1,2 Auto refresh H H L L L H X X Self refresh Entry H L L L L H X X Exit L H L H H H X X H X X X X X Bank activate H X L L H H X * V = Valid. row address Read Auto precharge disable H X L H L H X V L column address Auto precharge enable H 4,5 Write Auto precharge disable H X L H L L X V L column address Auto precharge enable H 4,5 Burst stop H X L H H L X X Precharge Selected bank H X L L H L X V L X Both banks X H Clock suspend or active power down Entry H L H X X X X X L V V V X Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H X Exit L H H X X X X L H H H X DQM H X X X X X V X X X No operation command H X H X X X X X L H H H X

5/21/01; v.1.1 Alliance Semiconductor P. 5 of 29 Mode register fields † RFU = 0 during MRS cycle. Burst sequence (burst length = 4) Burst sequence (burst length = 8) Register programmed with MRS Address A11~A10 Function RFU† WBL TM CAS latency BT Burst length Write burst length Burst type Length Type Programmed burst length Sequential Interleaved Single burst Test mode Type Mode register set Reserved Reserved Reserved CAS latency Burst length Latency BT = 0 BT = 1 Reserved X X Reserved Reserved Reserved Reserved Reserved Reserved Reserved Full page Reserved Initial address Sequential Interleave Initial address Sequential Interleave

5/21/01; v.1.1 Alliance Semiconductor P. 6 of 29 AS4LC2M8S1 AS4LC1M16S1 Recommended operating conditions † VIL Min = –1.5V for pulse widths less than 5 ns. ‡ IOH = –2mA, and IOL = 2mA. Recommended operating conditions apply throughout this document unless otherwise specified. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Min Nominal Max Unit Notes Supply voltage VCC,VCCQ 3.0 3.3 3.6 V GND 0.0 0.0 0.0 V Input voltage VIH 2.0 VCC + 0.3 V VIL –0.3† 0.8 V Output voltage‡ VOH 2.4 V VOL 0.4 V Ambient operating temperature TA Parameter Symbol Min Max Unit Notes Input voltage VIN,VOUT –1.0 +4.6 V Power supply voltage VCC,VCCQ –1.0 +4.6 V Storage temperature (plastic) TSTG –55 +150 Power dissipation PD W Short circuit output current IOUT mA

5/21/01; v.1.1 Alliance Semiconductor P. 7 of 29 DC electrical characteristics CL = CAS latency. Parameter Symbol Test conditions –10 Unit Notes Min Max Min Max Min Max Input leakage current IIL 0V ≤ VIN ≤ VCC, Pins not under test = 0V µA Output leakage current IOL DOUT disabled, 0V ≤ VOUT ≤ VCCQ µA Operating current (one bank active) ICC1 tRC ≥ min, IO = 0mA, burst length = 1 CL =3 140 100 100 mA 1,3, 4,5 Precharge standby current (power down mode) ICC2P CKE ≤ VIL(max), tCK = 15 ns 2.0 2.0 2.0 mA ICC2PS CKE and CLK ≤ VIL(max), tCK = ∞ 2.0 2.0 2.0 mA Precharge standby current (non-power- down mode) ICC2N CS ≥ VIH(min), CKE ≥ VIH(min), tCK = 15 ns; input signals changed once during 30 ns mA 1,2,3 ICC2NS CLK ≤ VIL(max), CKE ≥ VIH(min), tCK = ∞; input signals stable mA 1,2,3 Active standby current (power- down mode) ICC3P CKE ≤ VIL(max), tCK = 15 ns mA 1,2,3 ICC3PS CLK, CKE ≤ VIL(max), tCK = ∞ mA 1,2,3 Active standby current (non-power- down mode, one bank active) ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15 ns; input signals changed once during 30 ns mA 1,2,3 ICC3NS CKE ≥ VIH(min), CLK ≥ VIL(max), tCK = ∞; input signals stable mA 1,2,3 Operating current (burst mode) ICC4 IO = 0 mA Page burst All banks activated tCCD = tCCD(min) CL =3 140 130 120 mA 1,2, 3,5 CL =2 125 115 100 CL =1 Refresh current ICC5 tRC ≥ tRC(min) 100 mA 1,2, 3,5 Self refresh current ICC6 CKE ≤ 0.2 V mA mA

5/21/01; v.1.1 Alliance Semiconductor P. 8 of 29 AS4LC2M8S1 AS4LC1M16S1 AC parameters common to all waveforms Sym Parameter CAS latency –10 Unit Notes Min Max Min Max Min Max tAC CLK to valid output delay 5.5 ns 8.5 ns 6,8 ns 6,8 tAH Address hold time ns tAS Address setup time ns tBDL Last data-in to burst stop tCK tCCD Read/write command to read/write command tCK tCDL Last data-in to new column address delay tCK tCH CLK high-level width 2.75 ns tCK CLK cycle time 1000 1000 1000 ns 8.7 1000 1000 1000 ns 1000 1000 1000 ns tCKED CKE to CLOCK disable or power-down entry mode tCK tCKH CKE hold time ns tCKS CKE setup time ns tCL CLK low-level width 2.75 3.5 ns tCMH CS, RAS, CAS, WE, DQM hold time ns tCMS CS, RAS, CAS, WE, DQM setup time ns tDAL Data-in to ACTIVE command tCK 5,11 tCK 5,11 tCK 5,11 tDH Data in hold time ns tDPL Data in to PRECHARGE tCK tDQD DQM to input data delay tCK tDQM DQM to data mask during writes tCK tDQZ DQM to data high Z during reads tCK tDS Data in setup time ns tDWD Write command to input data delay tCK tHZ Data-out high-impedance time 5.5 ns 8.5 ns ns tLZ Data-out low-impedance time ns

5/21/01; v.1.1 Alliance Semiconductor P. 9 of 29 Notes IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. Address transitions average one transition every two-clock period. The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced. tCK = 7 ns for –7, 8 ns for –8, and 10 ns for –10. If clock tr > 1 ns, (tr/2 – 0.5)ns should be added to the parameter. If clock (tr and tf) > 1 ns, [(tr + tf)/2 – 1] ns should be added to the parameter. VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL(min) = –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate. Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be used to reduce the data rate. Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. Timing actually specified by tWR. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going to HIGH-Z. CLK must be toggled a minimum of two times during this period. Enables on-chip refresh and address counters. All voltages referenced to VSS. The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0° C ≤ TA ≤ 70° C) is endured. tMRD Load mode register to active/refresh command tCK tOH Output data hold time @ 30 pF 2.5 ns 2.5 ns 2.5 ns tPED CKE to CLOCK enable or power-down exit mode tCK tRAS Active to precharge command 120,000 120,000 120,000 ns tRC Active command period ns tRCAR Auto refresh period ns tRCD Active to read or write delay tCK tREF Refresh period—2048 rows ms tROH Data-out high Z from precharge/burst stop command tCK tCK tCK tRP Precharge command period tCK tRRD Active Bank A to Active Bank B command ns tT Transition time 0.3 1.0 0.3 1.0 0.3 1.0 ns tWR WRITE recovery time tCK tXSR Exit SELF REFRESH to ACTIVE command ns Sym Parameter CAS latency –10 Unit Notes Min Max Min Max Min Max

5/21/01; v.1.1 Alliance Semiconductor P. 10 of 29 AS4LC2M8S1 AS4LC1M16S1 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 1 ns. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. AC timing and IDD tests have VIL = 0V and VIH = 3.0 V with timing referenced to 1.4V crossover point. IDD specifications are tested after the device is properly initialized. Minimum clock cycles = (minimum time/clock cycle time) rounded up. Device operation Command Pin settings The following sequence is recommended prior to normal operation. Apply power, start clock, and assert CKE and DQM high. All other signals are NOP. After power-up, pause for a minimum of 200µs. CKE/DQM = high; all others NOP. Precharge both banks. Perform Mode Register Set command to initialize mode register. Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (Steps 4 and 5 may be interchanged.) Mode register set CS = RAS = CAS = WE = low; A0~A11 = opcode The mode register stores the user selected opcode for the SDRAM operating modes. The CAS latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the Mode Register Set command cycle. The default setting of the mode register is not defined after power-up. Therefore, it is recommended that the power-up and mode register set cycle be executed prior to normal SDRAM operation. Refer to the Mode Register Set table and timing for details. Device deselect and no operation CS = high, or RAS, CAS, WE = high The SDRAM performs a “no operation” (NOP) when RAS, CAS, and WE = high. Since the NOP performs no operation, it may be used as a wait state in performing normal SDRAM functions. The SDRAM is deselected when CS is high. CS high disables the command decoder such that RAS, CAS, WE and address inputs are ignored. Device deselection is also considered a NOP. Bank activation CS = RAS = low; CAS = WE = high; A0~A10 = row address; A11 = bank select The SDRAM is configured with two internal banks. Use the Bank Activate command to select a row in one of the two idle banks. Initiate a read or write operation after tRCD(min) from the time of bank activation. Burst read CS = CAS = A10 = low; RAS = WE = high; A11 = bank select, A0~A8 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) Use the Burst Read command to access a consecutive burst of data from an active row in an active bank. Burst read can be initiated on any column address of an active row. The burst length, sequence and latency are determined by the mode register setting. The first output data appears after the CAS latency from the read command. The output goes into a high impedance state at the end of the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. A full-page burst does not terminate automatically at the end of the burst. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write

5/21/01; v.1.1 Alliance Semiconductor P. 11 of 29 Burst write CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) Use the Burst Write command to write data into the SDRAM on consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Burst terminate behavior for write is the same as that for read. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. DQM can also be used to mask the input data. UDQM/LDQM (×16) DQM (×8) operation Use DQM to mask input and output data. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency). Burst stop CS = WE = low; RAS = CAS = high Use burst stop to terminate burst operation. This command may be used to terminate all legal burst lengths. Bank precharge CS = A10 = RAS = WE = low; CAS = high; A11 = bank select; A0~A9 = don’t care The Bank Precharge command precharges the bank specified by A11. The precharged bank is switched from active to idle state and is ready to be activated again. Assert the precharge command after tRAS(min) of the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. Precharge all CS = RAS = WE = low; CAS = A10 = high; A11, A0~A9 = don’t care The Precharge All command precharges both banks simultaneously. Both banks are switched to the idle state on precharge completion. Auto precharge Write: CS = CAS = WE = low ; Read: CS = CAS = low; A10 = high; A11 = bank select; A0~A9 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) During auto precharge, the SDRAM adjusts internal timing to satisfy tRAS(min) and tRP for the programmed CAS latency and burst length. Couple the auto precharge with a burst read/write operation by asserting A10 to a high state at the same time the burst read/write commands are issued. At auto precharge completion, the specified bank is switched from active to idle state. Note that no new commands (RD/WR/DEAC) can be issued to the same bank until the specified bank achieves the idle state. Auto precharge does not work with full- page burst. Clock suspend/power down mode entry CKE = low When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. If both banks are idle and CKE goes low, the SDRAM enters power down mode at the next clock cycle. When in power down mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Clock suspend/power down mode exit CKE = high Resume internal clock operation by asserting CKE high before the rising edge of CLK. Subsequent commands can be issued one clock cycle after the end of the Exit command. Command Pin settings

5/21/01; v.1.1 Alliance Semiconductor P. 12 of 29 AS4LC2M8S1 AS4LC1M16S1 Initialize and load mode register * DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. † The Mode Register may be loaded prior to the auto refresh cycles if desired. ƒ Outputs are guaranteed High-Z after command is issued. Auto refresh CS = RAS = CAS = low; WE = CKE = high; A0~A11 = don’t care SDRAM storage cells must be refreshed every 64 ms to maintain data integrity. Use the auto refresh command to accomplish the refreshing of all rows in both banks of the SDRAM. The row address is provided by an internal counter which increments automatically. Auto refresh can only be asserted when both banks are idle and the device is not in the power down mode. The time required to complete the auto refresh operation is tRC(min). Use NOPs in the interim until the auto refresh operation is complete. Both banks will be in the idle state after this operation. Self refresh CS = RAS = CAS = CKE = low; WE = high; A0~A11 = don’t care Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally. Self refresh entry is allowed only when both banks are idle. The internal clock and all input buffers with the exception of CKE are disabled in this mode. Exit self refresh by restarting the external clock and then asserting CKE high. NOPs must follow for a time of tRC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 2048 auto refresh cycles immediately after exiting self refresh. Command Pin settings DQM* ADDRESS DQ Tm Tn Tp+1 Tp+2 Tp+3 tCH tCL tCK tCKS tCKH NOP AUTO REFRESH NOP tCMH tCMS AUTO REFRESH NOP NOP LOAD MODE REGISTER ACTIVE CODE tAS tAH BANK ROW NOP NOP High Z T=200µs (min) Power up: VDD and CLK stable. tRP Precharge all banks. (8 AUTO REFRESH tRCAR Program Mode Register†ƒ tMRD PRECHARGE A10=HIGH ALL AUTO REFRESH CYCLES)

5/21/01; v.1.1 Alliance Semiconductor P. 13 of 29 Read—DQM operation* * For this example, the burst length = 4, and the CAS latency = 2. † A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Write—DQM operation* * For this example, the burst length = 4. † A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. CLK CKE COMMAND DQMƒ A0–A9 A10 tCH tCL tCK *†ƒ tCKS tCKH NOP tCMH tCMS READ NOP NOP NOP NOP BA DQ tCL tCMS tCMH ACTIVE tAH tAS ROW tAH tAS ROW tAH tAS BANK Column m (A0-A7)3 ENABLE AUTOPRECHARGE DISABLE AUTOPRECHARGE BANK tRCD CAS latency tAC *†ƒ tLZ tOH tHZ tLZ DOUT m+2 tAC *†ƒ DOUT m+3 tAC *†ƒ tOH tDQZ tOH tHZ DOUT m ROW NOP NOP CLK CKE COMMAND DQMƒ A0–A9 A10 tCH tCK *†ƒ tCKS tCKH NOP NOP tCMH tCMS WRITE NOP NOP NOP NOP BA DQ tCL tCMS tCMH ACTIVE tAH tAS ROW tAH tAS ROW tAH tAS BANK Column m (A0-A7)† ENABLE AUTOPRECHARGE DISABLE AUTOPRECHARGE BANK tRCD DIN m DIN m+2 DIN m+3 tDS tDH tDS tDH tDS tDH

5/21/01; v.1.1 Alliance Semiconductor P. 14 of 29 AS4LC2M8S1 AS4LC1M16S1 Write—full-page burst * A8 and A9 = Don’t care. † DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. ƒPage left open; no tRP. Read—full-page burst* * For this example, the CAS latency = 2. † A8 and A9 = “Don’t care.” ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. ** Page left open; no tRP. A0–A9 A10 BA tAH tAS ROW tAH tAS ROW tAH tAS BANK (A0-A7)* BANK CLK CKE COMMAND DQM† Tn+1 tCH tCK *†ƒ tCKS tCKH tCMH tCMS NOP NOP NOP DQ tCL tCMS tCMH ACTIVE Column m tRCD Tn+2 DIN m DIN m+1 DIN m+3 tDS tDH tDS tDS Tn+3 WRITE NOP NOP BURST TERM NOP DIN m+2 tDS tDH tDS tDH tDH tDS DIN m+255 tDH tDH Full page completedFull-page burst does not self terminate. Can use BURST TERMINATE command. ƒ 256 locations within same row CLK Tn+1 Tn+2 Tn+3 Tn+4 tCL tCH tCK CKE tCMS tCMH Command ACTIVE NOP NOP BURST TERM NOP NOP NOP NOP NOP READ NOP DQM† tCMS tCMH A0–A9 A10 tAH tAS tAH tAS ROW COLUMN m (A0-A7)† ROW BA tAH tAS BANK BANK DQ tRCD DOUT m Full page completed tAC *†ƒ tLZ tOH tAC *†ƒ DOUT m+1 tOH tAC *†ƒ tOH tAC *†ƒ DOUT m+2 DOUT m+255 tOH tAC *†ƒ DOUT m tOH tAC *†ƒ DOUT m+1 tOH CAS Latency 256 locations within same row tHZ*†ƒ Full-page burst does not self-terminate. Can use BURST TERMINATE command.

5/21/01; v.1.1 Alliance Semiconductor P. 15 of 29 Mode register set command waveform MRS can be issued only when both banks are idle. Precharge waveforms Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP. The earliest assertion of the precharge command without losing any burst data is show below. (normal write; BL = 4) (normal read; BL = 4) Auto precharge waveforms A10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; BL = 4) (read with auto precharge; BL = 4) *The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. CLK CMD PRE MRS ACT tRP tRSC(min) Or Auto Refresh tMRD CLK CMD DQ WE PRE CLK CMD DQ(CL1) DQ(CL2) DQ(CL3) Read data PRE CLK CMD DQ WE Auto precharge starts* Auto precharge starts* CLK CMD DQ(CL1) DQ(CL2) DQ(CL3) Read data

5/21/01; v.1.1 Alliance Semiconductor P. 16 of 29 AS4LC2M8S1 AS4LC1M16S1 DQM waveforms: read (CL = 3, BL = 4) DQM waveforms: write (BL = 4) Concurrent Auto-P Waveforms According to Intel™’s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (A) RD-P interrupted by RD in another bank (CL = 3, BL = 4) (B) RD-P interrupted by WR in another bank (CL = 3, BL = 8) CLK CMD DQM DQ(CL = 3) DQ(CL = 2) Read data tDQZ tDQZ CLK CMD Ext DIN DQM Write data ignored ignored Data written CLK CMD RD-P(A) DQ tRP(A) Bank A precharge starts RD (B) CLK CMD RD-P (A) DQ QA0 DN(B0) D(B1) D(B2) tRP Bank A precharge starts WR (B) DQM D(B7) QA1

5/21/01; v.1.1 Alliance Semiconductor P. 17 of 29 (C) WR-P interrupted by RD in another bank (CL = 2, BL = 4) (D) WR-P Interrupted by WR in another bank (CL = 3, BL = 4) Clock suspension read waveforms (BL = 8) CLK CMD WRP (A) DQ D(A0) D(A1) QB0 QB1 QB2 tRP Bank A precharge starts RD (B) QB3 CLK CMD WRP (A) DQ DA0 DA1 DA2 DB0 DB1 WR (B) DB2 DB3 Bank A precharge starts CLK external CLK internal CKE DQM DQ OPEN OPEN CLK external CLK internal CKE DQM DQ CLK external CLK internal CKE DQM DQ tCKED tPED

5/21/01; v.1.1 Alliance Semiconductor P. 18 of 29 AS4LC2M8S1 AS4LC1M16S1 Clock suspension write waveforms Read/write interrupt timing read interrupted by read (BL = 4) tCCD = CAS to CAS delay (= 1 CLK). CLK external CLK internal CKE DQM DQ DQM Mask CKE Mask tCKH tCKS CLK external CLK internal CKE DQM DQ DQM Mask CKE Mask CLK external CLK internal CKE DQM DQ tCMS tCMH CKE Mask CLK CMD ADD DQ (CL1) DQ (CL2) DQ (CL3) Read data Read data A B QA0 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 tCCD tCMS tCMH

5/21/01; v.1.1 Alliance Semiconductor P. 19 of 29 write interrupted by write (BL = 4) tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). write interrupted by read (BL = 4) tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). Interrupting RD/WR can be for either the same or different banks. read interrupted by write (CL = 1, BL = 4) To prevent bus contention, maintain a gap between data in and data out. CLK CMD ADD DQ DA0 DB0 DB1 DB2 DB3 Write data Write data tCCD tCDL tCK tCH tCL tDS tDH tCDL CLK CMD ADD DQ (CL1) DQ (CL2) DQ (CL3) Write data Read data A B DA0 QB0 QB1 QB2 QB3 DA0 QB0 QB1 QB2 QB3 DA0 QB0 QB1 QB2 QB3 tCCD CLK CMD1 DQM1 DQ1 CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 Write data Read data Write data Read data Write data Read data tLZ tHZ

5/21/01; v.1.1 Alliance Semiconductor P. 20 of 29 AS4LC2M8S1 AS4LC1M16S1 read interrupted by write (CL = 2, BL = 4) To prevent bus contention, maintain a gap between data in and data out. read interrupted by write (CL = 3, BL = 4) To prevent bus contention, maintain a gap between data in and data out. Burst termination Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously. CLK CMD1 DQM1 DQ1 CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 CMD4 DQM4 DQ4 Write data Read data Write data Read data Write data Read data Write data Read data CLK CMD1 DQ1 CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 CMD4 DQM4 DQ4 Read data Write data Read data Write data Read data Write data Read data Write data DQM1 tCCD

5/21/01; v.1.1 Alliance Semiconductor P. 21 of 29 Burst stop command waveform read cycle write cycle (BL = 8) Precharge termination A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency. read cycle (CL = 1) read cycle (CL = 2) read cycle (CL = 3) CLK CMD DQ (CL = 1) DQ (CL = 2) DQ (CL = 3) Read data Burst stop tT tOH CLK CMD DQ Burst stop Write data (CL = 1,2,3) DQ CLK CMD DQ Read data PRE tRP ACT CLK CMD DQ Read data PRE ACT tRP tROH (CL = 2) CLK CMD DQ Read data PRE ACT tROH (CL = 3) tRP

5/21/01; v.1.1 Alliance Semiconductor P. 22 of 29 AS4LC2M8S1 AS4LC1M16S1 write cycle Write recovery (BL = 4) Auto refresh waveform CLK CMD DQ Write data PRE ACT tRP tWR CLK CMD DQ Write data ACT tRP tDPL This precharge is implicit in case of Auto-P Write. PRE tDAL CLK CS RAS CAS WE A10 A0–A9 DQM CKE DQ tRP tRC tRC Auto refresh Precharge both banks Auto refresh Auto refresh

5/21/01; v.1.1 Alliance Semiconductor P. 23 of 29 Self refresh waveform Power down mode waveform (CL = 3) Enter power down mode by pulling CKE low. All input/output buffers (except CKE buffer) are turned off in power down mode. When CKE goes high, command input must be equal to no operation at next CLK rising edge. CLK CS RAS CAS WE A11 A0–A10 DQM CKE DQ Precharge both banks tRC Self refresh entry Self refresh exit Self refresh Arbitrary cycle cycle Clock stable before self refresh exit Power down mode Active standby CLK CS RAS CAS WE A11 A10 A0–A9 DQM CKE DQ RAa RAa CAa CAx RAa RAa Bank activate Power down mode entry Power down mode exit NOP Power down mode entry Power down mode Precharge standby NOP Power down mode exit Bank activate Data burst

5/21/01; v.1.1 Alliance Semiconductor P. 24 of 29 AS4LC2M8S1 AS4LC1M16S1 Read/write waveform (BL = 8, CL = 3) Burst read/single write waveform (BL = 4, CL = 3) Ab0 CLK CS RAS CAS WE A11 A10 A0–A9 DQM CKE DQ CAb RAb RAb tRCD Aa0 Aa5 Aa4 Aa3 Aa2 Aa1 Ab5 Ab4 Ab3 Ab2 Ab1 Bank activate Read Q Q Q Q Q Q D D D D D D Bank activate Write Precharge tRAS CAa RAa tRP RAa Single CLK CS RAS CAS WE A11 A10 DQM CKE DQ RAa CAa RAa CAb CAc CAd Activate Read Read Write Aa0 Ac Ab Aa3 Aa2 Aa1 Ad0 Ad3 Ad2 Ad1 Q Q Q Q Q Q Q Q D D

5/21/01; v.1.1 Alliance Semiconductor P. 25 of 29 Interleaved bank read waveform (BL = 4, CL = 3) Interleaved bank read waveform (BL = 4, CL = 3, Autoprecharge) AP = internal precharge begins CLK CS RAS CAS WE A11 A10 A0–A9 DQM CKE DQ tCCD tCCD tCCD tRAS tRCD tRCD RAa RBa CAa CAb CBb CAc QAa0 QAa3 QAa2 QAa1 QBa0 QAb1 QAb0 QBa1 QAb2 QAc2 QAc1 QAc0 QBb0 QBb3 QBb2 QBb1 Bank A: Bank B: Active Read Read Read Read Precharge RAa CBa Precharge RBa Read Active tRAS CLK CS RAS CAS WE A11 A10 DQM CKE DQ tRC tRC tRAS tRP tRAS tRP tRAS tRP tRCD tRCD tRCD QAa0 QAa2 QAa1 QBb3 QBb2 QBb1 QAc2 QAc3 RAa RAa RBb RBb CAa RBd RBd tRRD tRRD tRRD Bank A: Bank B: Active Read Active AP Active Read AP Read Active AP QAa3 QBb0 RAc RAc CBb CAc QAc1 QAc0

5/21/01; v.1.1 Alliance Semiconductor P. 26 of 29 AS4LC2M8S1 AS4LC1M16S1 Interleaved bank read waveform (BL = 8, CL = 3) Interleaved bank read waveform (BL = 8, CL = 3, Autoprecharge) AP = internal precharge begins CLK CS RAS CAS WE A11 A10 DQM CKE DQ tRC tRAS tRAS tRP tRP tRCD tRCD tRCD RAa RAa CAa RBb RBb CBb RAc RAc CAc QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QBb0 QBb1 QBb4 QBb5 QBb6 QBb7 QAc0 QAc1 Bank A: Bank B: Active Read Precharge Read Precharge Active Precharge Active Read CLK CS RAS CAS WE A11 A10 DQM CKE DQ QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QBb0 QBb1 QAa7 tRC tRAS tRP tRAS tRCD tRCD tRCD CAa RAa RBb RBb CAb CAc RAa RAc RAc QBb4 QBb5 QBb6 QAc0 QAc0 tRRD tRRD Active Read Active Read Bank A Bank B AP Active Read AP

5/21/01; v.1.1 Alliance Semiconductor P. 27 of 29 Interleaved bank write waveform (BL = 8) Interleaved bank write (BL = 8, Autoprecharge) AP = internal precharge begins CLK CS RAS CAS WE A11 A10 DQM CKE DQ tRC tRAS tRP tRAS tRCD tRCD tRCD CAa RAa RBb RBb CAb CAc RAa RAc RAc DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 Active Write Active Write Bank A Bank B Active Write Precharge Precharge CLK CS RAS CAS WE A11 A10 DQM CKE DQ Active Write Active Write Bank A Bank B Active Write tRC tRAS tRP tRAS tRCD tRCD tRCD CAa RAa RBb RBb CAb CAc RAa RAc RAc DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc2 AP Bank A AP Bank B DBb1 DAc1

5/21/01; v.1.1 Alliance Semiconductor P. 28 of 29 AS4LC2M8S1 AS4LC1M16S1 Package dimensions AC test conditions Capacitance 15 ƒ = 1 MHz, Ta = 25° C, VCC = 3.3V

Ordering information

DQM, RAS, CAS, WE, CS, CLK, CKE, pF I/O capacitance CI/O DQ0 to DQ7 (2M × 8) DQ0 to DQ15 (1M × 16) pF Package \\1/ frequency –7 ns –8 ns –10 ns TSOP 2, 400 mil, 44-pin AS4LC2M8S1-7TC AS4LC2M8S1-8TC AS4LC2M8S1-10TC TSOP 2, 400 mil, 44-pin AS4LC2M8S0-7TC AS4LC2M8S0-8TC AS4LC2M8S0-10TC TSOP 2, 400 mil, 50-pin AS4LC1M16S1-7TC AS4LC1M16S1-8TC AS4LC1M16S1-10TC TSOP 2, 400 mil, 50-pin AS4LC1M16S0-7TC AS4LC1M16S0-8TC AS4LC1M16S0-10TC 44-pin TSOP 2 50-pin TSOP 2 Min (mm) Max (mm) Min (mm) Max (mm) A 1.2 1.2 0.05 0.05 0.95 1.05 0.95 1.05 b 0.30 0.45 0.30 0.45 c 0.127 (typical) 0.12 0.21 D 18.28 18.54 20.85 21.05 E 10.03 10.29 10.03 10.29 He 11.56 11.96 11.56 11.96 e 0.80 (typical) 0.80 (typical) l 0.40 0.60 0.40 0.60 D He 1 2 3 4 5 6 7 8 9 10111213 14 50 4948474645 444342 4140393837 1516 36 35 171819 20 343332 31 c l e TSOP 2 0–5° 22232425 29282726 E A b - Output reference levels = 1.4V - Input rise and fall times: 2 ns CLOAD = 50 pF DOUT +1.5V Figure A: Equivalent output load 50Ω

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