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AS4C2M32D1A - 144 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Dec 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 1 of 63 Rev.1.0 Dec 2015
The 64Mb DDR SDRAM is a high-s peed CMOS double data rate synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The device provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-t imed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 64Mb DDR features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth; result in a device particularly well suited to high performance main memory and graphics applications.
Features
- Fast clock rate: 200 MHz
- Differential Clock CK & CK
- Bi-directional DQS
- DLL enable/disable by EMRS
- Fully synchronous operation
- Internal pipeline architecture
- Four internal banks, 512K x 32-bit for each bank
- Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved
- Individual byte write mask control
- DM Write Latency = 0
- Auto Refresh and Self Refresh
- 4096 refresh cycles / 64ms
- Precharge & active power down
- Operating Temperature: - Commercial (0 ~ 70 °C) - Industrial (-40 ~ 85 °C)
- Power supplies: VDD & VDDQ = 2.5V ± 0.2V
- Interface: SSTL_2 I/O Interface
- 144-ball 12 x 12 x 1.4mm FBGA package - Pb and Halogen Free
Table 1. Ordering Information
Figure 1. Ball Assignment (Top View) Table 2. Ball Assignment by Name (FBGA 144Ball)
Figure 2. Block Diagram
Table 3. Ball Details signals are sampled on the crossing of th e positive edge of CK and negative edge of CK. BankPrecharge command is being applied. Extended Mode Register Set command. bank selection on systems with multiple banks. It is considered part of the command code. bank designated by B A is switched to the idle state after the precharge operation. "LOW". Then, the Read or Write command is selected by asserting WE "HIGH" or "LOW". to select the BankActivate or Precharge command and Read or Write command. DQS0 to DQ0-DQ7, DQS1 to DQ8 -DQ15, DQS2 to DQ16 -DQ23, DQS3 to DQ24 -DQ31. DQ15-DQ8, and DM0 masks DQ7- DQ0. negative edges of DQS0~DQS3. The I/Os are byte-maskable during Writes. VDD Supply Power Supply: 2.5V ± 0.2V. VDDQ Supply DQ Power: 2.5V ± 0.2V . Provide isolated power to DQs for improved noise immunity.
VSSQ Supply DQ Ground: Provide isolated ground to DQ s for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - No Connect: These pins should be left unconnected. AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 6 of 63 Rev.1.0 Dec 2015
truth table for the operation commands. Table 4. Truth Table (Note (1), (2))
- CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
- These are states of bank designated by B A signal.
- Device state is 2, 4, and 8 burst operation.
- Power Down Mode can not enter in the burst operation.
versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies. Table 5. Mode Register Bitmap
0 MRS 1 0 1 Reserved 1 0 1 Reserved
- Note: RFU (Reserved for future use) must be set to “0” during MRS cycle.
- Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8.
Table 6. Burst Length
- Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4 and 8.
Table 7. Addressing Mode
0 Sequential
1 Interleave
- Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 8. Burst Address ordering
2 X X 0 0, 1 0, 1
- CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. t CAC(min) ≤ CAS Latency X tCK
Table 9. CAS Latency
- Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 10. Test Mode
- ( BA0, BA1) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 9 of 63 Rev.1.0 Dec 2015
Table 11. MRS/EMRS for DLL enable or disable. "High" on B A0 is used for EMRS. Refer to the table for specific codes. Table 12. Extended Mode Register Bitmap
0 MRS 0 Full 0 Enable
1 EMRS 1 RFU 1 Disable
Table 13. Absolute Maximum Rating Note: All voltages are referenced to V SS. Table 15. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 °C)
Parameter & Test Condition Symbol -5 Unit Note Max. changing once every two clock cycles.
Table 17. Electrical Characteristics and Recommended A.C.Operating Condition Symbol Parameter -5 Unit Note Min. Max.
1) Enables on-chip refresh and address counters. 2) Min(tCL, tCH) refers to the smaller of the actual clock low time and actual clock high time as provided to the device. CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. parameter, but system performance (bus turnaround) will degrade accordingly. 6) For command/address and CK & CK slew rate ≧ 1.0V/ns. 7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. Table 19. SSTL _2 Interface
reference load to a system environment is suggested. Figure 3. SSTL_2 A.C. Test Load be performed in the following sequence. "NOP" state and maintain CKE “LOW”. 2) Start clock and maintain stable condition for minimum 200 µs. 4) Issue a “Precharge All” command. 6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register.
Figure 4. Activating a Specific Row in a Specific Bank
Figure 7. Read Burst Required CAS Latencies (CL=2)
n CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Read Burst Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 19 of 63 Rev.1.0 Dec 2015
Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2)
o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n Consecutive Read Bursts Required CAS Latencies (CL=2.5) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 21 of 63 Rev.1.0 Dec 2015
o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n Consecutive Read Bursts Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 22 of 63 Rev.1.0 Dec 2015
Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO o DO n Non-Consecutive Read Bursts Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 24 of 63 Rev.1.0 Dec 2015
Figure 10. Random Read Accesses Required CAS Latencies (CL=2) DO n, etc. =Data Out from column n, etc. DO n, etc. =Data Out from column n, etc.
p DO DO o DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n ' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n Random Read Accesses Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 26 of 63 Rev.1.0 Dec 2015
Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2)
COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n Terminating a Read Burst Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 28 of 63 Rev.1.0 Dec 2015
Figure 12. Read to Write Required CAS Latencies (CL=2)
COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care min tDQSS DI o DM Bank, Col o DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n Read to Write Required CAS Latencies (CL=2.5) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 30 of 63 Rev.1.0 Dec 2015
COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o min tDQSS DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n Read to Write Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 31 of 63 Rev.1.0 Dec 2015
Figure 13. Read to Precharge Required CAS Latencies (CL=2)
COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n Read to Precharge Required CAS Latencies (CL=2.5) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 33 of 63 Rev.1.0 Dec 2015
COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n Read to Precharge Required CAS Latencies (CL=3) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 34 of 63 Rev.1.0 Dec 2015
Figure 14. Write Command
Figure 15. Write Max DQSS
Figure 16. Write Min DQSS
Figure 17. Write Burst Nom, Min, and Max tDQSS
Figure 18. Write to Write Max tDQSS DI n , etc. = Data In for column n,etc.
DI n, etc. = Data In for column n, etc. Figure 19. Write to Write Max tDQSS, Non Consecutive
Figure 20. Random Write Cycles Max tDQSS DI n, etc. = Data In for column n, etc.
Figure 21. Write to Read Max tDQSS Non Interrupting DI n, etc. = Data In for column n, etc.
Figure 22. Write to Read Max tDQSS Interrupting DI n, etc. = Data In for column n, etc.
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
Figure 25. Write to Precharge Max tDQSS, Interrupting
Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting
Figure 27. Precharge Command
Figure 28. Power-Down Figure 29. Clock Frequency Change in Precharge
200 Clocks
*=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up. Figure 32. Initialize and Mode Register Sets
Figure 33. Power Down Mode then the Power-Down mode shown is active Power Down.
Figure 34. Auto Refresh Mode
Figure 35. Self Refresh Mode required before a READ command can be applied.
Figure 36. Read without Auto Precharge
Figure 37. Read with Auto Precharge
Figure 38. Bank Read Access
Figure 39. Write without Auto Precharge
Figure 40. Write with Auto Precharge
Figure 41. Bank Write Access
Figure 42. Write DM Operation
Figure 43. 144 ball LFBGA Package Outline Drawing Information
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. PART NUMBERING SYSTEM AS4C 2M32D1A 5 B C/I N DRAM 2M32=2Mx32 D1=DDR A = Die Revision 5=200MHz B = FBGA C=Commercial (0° C70° C) Indicates Pb and Halogen Free I =Industrial (-40° C85° C) AS4C2M32D1A-5BCN AS4C2M32D1A-5BIN Confidential 63 of 63 Rev.1.0 Dec 2015