AS4C256K16F0-30JI

AS4C256K16FO ALSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 25

Technical content

Features

• Organization: 262,144 words × 16 bits
• High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time
• Low power consumption - Active: 770 mW max (ASAS4C256K16FO-50) - Standby: 5.5 mW max, CMOS I/O
• Fast page mode
• AS4C256K16FO-50 timings are also valid for AS4C256K16FO-60.
• Refresh - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device only. Contact Alliance for more information.
• Read-modify-write
• TTL-compatible, three-state I/O
• JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II
• Single 5V power supply/built-in Vbb generator
• Latch-up current > 200 mA Pin arrangement GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 SOJ NC LCAS UCAS OE GND VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC VCC VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC VCC VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE VSS TSOP II ASC256K16FO ASC256K16FO Selection guide Symbol –25 –30 –35 –50 Unit Maximum RAS access time tRAC ns Maximum column address access time tCAA ns Maximum CAS access time tCAC ns Maximum output enable (OE) access time tOEA ns Minimum read or write cycle time tRC ns Minimum EDO page mode cycle time tPC ns Maximum operating current ICC1 200 180 160 140 mA Maximum CMOS standby current ICC2 2.0 2.0 2.0 2.0 mA

4/11/01; V.0.9.1 Alliance Semiconductor P. 2 of 25 Functional description The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 262,144 words × 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4C256K16FO features a high-speed page mode operation in which high speed read, write and read-write are performed on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system-level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe (CAS) which acts as an output enable independent of RAS. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0–A8 during an 8 ms period is accomplished by performing any of the following:

• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
• Self-refresh cycles.* The AS4C256K16FO is available in standard 40-pin plastic SOJ and 44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 5V ± 10% tolerance and direct interface with TTL logic families. Logic block diagram Recommended operating conditions * Self-refresh option is available for new generation device only. Contact Alliance for more information. Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V Input voltage VIH 2.4 VCC + 1 V VIL –1.0 0.8 V 512×512×16 array (4,194,304) Sense amp VCC GND Addreess buffers Row decoder Column decoder OE RAS UCAS WE LCAS I/O0 to I/O15 Substrate bias generator Data I/O buffer Refresh controller RAS clock generator CAS clock generator WE clock generator

4/11/01; V.0.9.1 Alliance Semiconductor P. 3 of 25 Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC electrical characteristics (VCC = 5 ± 10%, GND = 0V, Ta = 0° C to +70° C) Parameter Symbol Min Max Unit Input voltage VIN –1.0 +7.0 V Output voltage VOUT –1.0 +7.0 V Power supply voltage VCC –1.0 +7.0 V Operating temperature TOPR +70 Storage temperature (plastic) TSTG –55 +150 Soldering temperature × time TSOLDER 260 × 10 °C × sec Power dissipation PD W Short circuit output current IOUT mA Latch-up current 200 mA Parameter Symbol Test conditions –25 –30 –35 –50 Unit Note Min Max Min Max Min Max Min Max Input leakage current IIL 0V ≤ VIN ≤ + 5.5V pins not under test = 0V –10 –10 –10 –10 µA Output leakage current IOL DOUT disabled, 0V ≤ VOUT ≤ + 5.5V –10 –10 –10 –10 µA Operating power supply current ICC1 RAS, UCAS, LCAS, address cycling; tRC = min 200 180 160 140 mA 1,2 TTL standby power supply current ICC2 RAS = UCAS = LCAS = VIH 2.0 2.0 2.0 2.0 mA Average power supply current, RAS refresh mode ICC3 RAS cycling, UCAS = LCAS = VIH, tRC = min 120 200 190 140 mA Fast page mode average power supply current ICC4 RAS = UCAS = LCAS = VIL, address cycling: tSC = min 130 190 180 mA 1,2 CMOS standby power supply current ICC5 RAS = UCAS = LCAS = VCC – 0.2V 0.60 1.0 1.0 1.0 mA CAS-before-RAS refresh power supply current ICC6 RAS, UCAS, LCAS, cycling; tRC = min 120 200 190 140 mA Output voltage VOH IOUT = – 5.0 mA 2.4 2.4 2.4 2.4 V VOL IOUT = 4.2 mA 0.4 0.4 0.4 0.4 V Self refresh current ICC7 RAS = UCAS = LCAS = VIL, WE = OE = A0 – A8 = VCC –0.2V, DQ0 – DQ15 = VCC – 0.2V, 0.2V are open 2.0 2.0 2.0 2.0 mA

4/11/01; V.0.9.1 Alliance Semiconductor P. 4 of 25 AC parameters common to all waveforms (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Read cycle (VCC = 5V±10%, GND = 0V, Ta = 0° C to + 70° C) Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tRC Random read or write cycle time ns tRP RAS precharge time ns tRAS RAS pulse width 75K 75K 75K 75K ns tCAS CAS pulse width ns tRCD RAS to CAS delay time ns tRAD RAS to column address delay time ns tRSH(R) CAS to RAS hold time (read cycle) ns tCSH RAS to CAS hold time ns tCRP CAS to RAS precharge time ns tASR Row address setup time ns tRAH Row address hold time ns tT Transition time (rise and fall) 1.5 1.5 1.5 ns 4,5 tREF Refresh period ms tCLZ CAS to output in low Z ns Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tRAC Access time from RAS ns tCAC Access time from CAS ns 6,13 tAA Access time from address ns 7,13 tAR(R) Column add hold from RAS ns tRCS Read command setup time ns tRCH Read command hold time to CAS ns tRRH Read command hold time to RAS ns tRAL Column address to RAS Lead time ns tCPN CAS precharge time ns tOFF Output buffer turn-off time ns 8,10

4/11/01; V.0.9.1 Alliance Semiconductor P. 5 of 25 Write cycle (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Read-modify-write cycle (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Fast page mode cycle (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tASC Column address setup time ns tCAH Column address hold time ns tAWR Column address hold time to RAS ns tWCS Write command setup time ns tWCH Write command hold time ns tWCR Write command hold time to RAS ns tWP Write command pulse width ns tRWL Write command to RAS lead time ns tCWL Write command to CAS lead time ns tDS Data-in setup time ns tDH Data-in hold time ns tDHR Data-in hold time to RAS ns Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tRWC Read-write cycle time 100 100 105 120 ns tRWD RAS to WE delay time ns tCWD CAS to WE delay time ns tAWD Column address to WE delay time ns tRSH(W) CAS to RAS hold time (write) ns tCAS(W) CAS pulse width (write) ns Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tPC Read or write cycle time ns tCAP Access time from CAS precharge ns tCP CAS precharge time ns tPCM Fast page mode RMW cycle ns tCRW Page mode CAS pulse width (RMW) ns tRASP RAS pulse width 75K 75K 75K 75K ns

4/11/01; V.0.9.1 Alliance Semiconductor P. 6 of 25 Refresh cycle (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Output enable (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Self refresh cycle (VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C) Notes ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the speci- fied tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the speci- fied tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC ≥ tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled, but not 100% tested. Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tCSR CAS setup time (CAS-before-RAS) ns tCHR CAS hold time (CAS-before-RAS) ns tRPC RAS precharge to CAS hold time ns tCPT CAS precharge time (CAS-before-RAS counter test) ns Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tROH RAS hold time referenced to OE ns tOEA OE access time ns tOED OE to data delay ns tOEZ Output buffer turnoff delay from OE ns tOEH OE command hold time ns Standard Symbol Parameter –25 –30 –35 –50 Unit Notes Min Max Min Max Min Max Min Max tRASS RAS pulse width (CBR self refresh) 100K 100K 100K 100K ns tRPS RAS precharge time (CBR self refresh) ns tCHS CAS hold time (CBR self refresh) ns

4/11/01; V.0.9.1 Alliance Semiconductor P. 7 of 25 Key to switching waveforms Read cycle waveform Undefined/don’t care Falling input Rising input tRAS tRC tRP tRSH tRAD tRCH tROH tCAC tOEA tOFF tOEZ RAS UCAS, LCAS Address WE OE I/O Col Address Row Address tCRP tCSH tRCD tASC tCAH tCAS tAR tRAL tRAH tRCS tAA tCLZ tRRH Data Out tASR tRAC

4/11/01; V.0.9.1 Alliance Semiconductor P. 8 of 25 Upper byte read waveform Lower byte read waveform tRAS tRC tRP tCRP tRCD tRSH tCSH tCRP tCRP tASR tRAH tRAD tRAL tCAH tRCS tRRH tRCH tCLZ tCAC tOEZ tOFF Row Column Data Out RAS UCAS LCAS Address WE OE Upper I/O Lower I/O tROH tASC tRAC tOEA tAA tCAS tROH tOEA tRAS tRC tRP tCRP tRCD tRSH tCRP tCRP tASR tRAH tRAD tRAL tCAH tRRH tRCH tCLZ tCAC tRAC tOEZ tOFF Row Column Data Out RAS LCAS UCAS Address WE OE Upper I/O Lower I/O tCSH tASC tRCS tAA tCAS

4/11/01; V.0.9.1 Alliance Semiconductor P. 9 of 25 Early write waveform tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAH tRAD tASC tAWR tCAH tWCS tCWL tRWL tWCH tWP tDS tDH tDHR Col Address Data In RAS UCAS, LCAS Address WE OE I/O Row Address tWCR tRAL tASR

4/11/01; V.0.9.1 Alliance Semiconductor P. 10 of 25 Upper byte early write waveform tRAS tRC tRP tRAH tRAD tAWR tCRP tASC tCAH tRSH tRCD tCSH tCRP tCRP tRPC tRWL tWCS tWP tDS tDH tDHR Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tASR tRAL tCAS tCWL tWCH tWCR

4/11/01; V.0.9.1 Alliance Semiconductor P. 11 of 25 Lower byte early write waveform Write waveform tRC tRAS tRP tRAD tAWR tCRP tRPC tCRP tASC tCAH tRSH tRCD tCSH tCRP tRWL tWP tWCS tWCR tWCH tDS tDH tDHR Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tCWL tRAH tCAS tRAL tASR Row Address tRAS tRC tRP tCRP tRSH tRCD tCSH tCAS tRAH tRAL tRAD tCAH tCWL tRWL tWCR tOEH tOED tDStDH Data In RAS UCAS, Address WE OE I/O Col Address tWP tASC tAWR tASR LCAS tDHR

4/11/01; V.0.9.1 Alliance Semiconductor P. 12 of 25 Upper byte write waveform tRAS tRC tRP tRAL tRAD tASC tCAH tCSH tCRP tCRP tRPC tRWL tWP tOEH tDS tDH tOED Row Address Column Address Data In RAS Address UCAS LCAS WE OE Upper I/O Lower I/O tCRP tAWR tRAH tRCD tCAS tRSH tCWL tASR

4/11/01; V.0.9.1 Alliance Semiconductor P. 13 of 25 Lower byte write waveform Read-modify-write waveform tRC tRAS tRP tRAH tRAD tACS tCAH tRSH tCSH tCRP tCRP tRPC tRWL tWP tOEH tDS tDH Row Address Column Address Data In RAS Address LCAS UCAS WE OE Upper I/O Lower I/O tCRP tRCD tCAS tCWL tAWR tRAL tASR tRAS tRWC tRP tCRP tRSH tRCD tCSH tCAS tRAD tRAL tAR tCAH tCWL tCWD tRWL tAWD tWP tOEA tCLZ tCAC tAA tDS tDH Row Address Col Address Data In Data Out RAS UCAS, Address WE OE I/O tRAH tRWD tRCS tRAC tOEZ tOED tASC tASR LCAS

4/11/01; V.0.9.1 Alliance Semiconductor P. 14 of 25 Upper byte read-modify-write waveform tRWC tRAS tRP tCRP tRSH tRCD tCSH tCAS tCRP tCRP tRPC tRAL tCAH tRWL tAWD tWP tCWD tOEA tDS tCLZ tAA tRAC tCAC tOEZ tOED Row Column Address Data In Data Out Data Out RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tACS tRWD tCWL tOED tRCS tRAH tASR tRAD

4/11/01; V.0.9.1 Alliance Semiconductor P. 15 of 25 Lower byte read-modify write waveform tRWC tRAS tRP tCRP tRPC tCRP tRSH tRCD tCSH tCAS tCRP tRAL tRAD tACS tCAH tRCS tRWL tWP tOEA tOED tDS tCLZ tOEZ Row Column Address Data In Data Out RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tRAH tAWD tCWL tCWD tCAC tRWD tASR tAA tRAC Data Out

4/11/01; V.0.9.1 Alliance Semiconductor P. 16 of 25 Fast page mode read waveform Fast page mode byte read waveform tASC Row tRASP tRP tCRP tRCD tCAS tCSH tRSH tPC tASR tRAD tRCH tRCS tRRH tRCH tOEA tOEA tAA tRAC tCAC tOEZ tCAP Data Out Data Out Data Out Col Address Col Address Col Address RAS UCAS, Address WE OE I/O tAR tRAH tCAH tRAL tRCS tCLZ tCP tOFF LCAS tRASP tRP tCAS tCSH tRSH tCAS tCAS tCRP tCRP tCAS tCP tRPC tRAH tRAD tASC tCAH tASC tRCS tOEA tOEZ tOFF tCAC tRAC tOFF tOEZ tCLZ tAA tCAC tCAP tOFF tOEZ Row Column 1 Column 2 Column n Data Out 1 Data Out n Data Out 2 RAS UCAS LCAS Address WE OE Upper I/O Lower I/O tCLZ tCAP tAA tCLZ tCAC tOEA tRCS tRCH tOEA tCAH tRAL tPC tPC tCAH tASC tRCD tRCH tRCS tASR tCRP tAA tCP

4/11/01; V.0.9.1 Alliance Semiconductor P. 17 of 25 Fast page mode early write waveform Fast page mode byte early write waveform tRAH tRASP tRWL tASC tWCS tRAL tWCH tCWL tWP tDS tDH tOED tCAS Row address Col address Col Address Col Address Data In Data In Data In RAS UCAS, Address WE OE I/O tPC tCAH tCSH tRCD tOEH tHDR tAR tRAD tASR tCRP LCAS tRSH tCP tRASP tRP tCAS tCSH tRSH tCAS tCRP tCRP tCP tCP tRPC tRAD tASC tRAL tWCS tCWL tWCS tWCH tWCS tCWL tRWL tDS tDH tDS tDH tDS tDH Row Column 1 Column 2 Column n Data In 1 Data In n Data In 2 RAS UCAS LCAS Address WE OE Upper I/O Lower I/O tPC tRAH tASC tWCH tWP tWP tCWL tWP tWCH tCAH tRCD tPC tCAS tCAH tCAH tASC tCRP tASR

4/11/01; V.0.9.1 Alliance Semiconductor P. 18 of 25 Fast page mode read-modify-write waveform CAS-before-RAS refresh waveform (WE = VIH) RAS-only refresh waveform (WE = OE = VIH or VIL) tCAC tDS tCLZ tCAC tRAC tRASP tRP tRCD tCSH tCAS tCP tCRP tASR tCAH tCAH tRAL tCAH tCWD tAWD tCWD tCWL tCWD tAWD tRWL tWP tOEZ tOEA tDS tCLZ tCAC tCAP Row Ad Col Ad Col Address Col Ad Data Out Data In Data In Data Out Data Out Data In RAS UCAS, Address WE OE I/O tRAD tRAH tRWD tRCS tCWL tOEA tAA tDH tCLZ tOED tPCM LCAS tRP tRC tRAS tRPC tCPN tCSR tCHR tOFF RAS UCAS, I/O LCAS tRAS tRP tRC tCRP tRPC tARS tRAH Row Address RAS UCAS, Address LCAS

4/11/01; V.0.9.1 Alliance Semiconductor P. 19 of 25 Fast page mode byte read-modify-write waveform Data Out 1 tRASP tRP tRCD tCAS tCSH tCRP tCP tCP tCAH tASC tCAH tASC tRAL tCWD tCWL tCWL tCWD tWP tRWL tOEA tDH tOEZ tDH tCLZ tCAC tAA tCAP tOEZ Data In n Data Out n Data Out 2 Data In 2 R C 1 C 2 C n RAS UCAS LCAS Address WE OE Upper Input Upper Output Lower Input Lower Output tPCM tCAS tRSH tCAS tAWD tCAH tAWD tASC tWP tCWL tWP tOEA tOEA tOED tDS tCAP tDS tOED tDH tOEZ tCLZ tOED tDS tAA tCAC tCLZ tCWD tAWD tCRP tRAD tRAH tASR tRCS tRWD tRAC Data In 1 tAA tCAC

4/11/01; V.0.9.1 Alliance Semiconductor P. 20 of 25 Hidden refresh waveform (read) Hidden refresh waveform (write) tAA tCHR tRAS tRC tPR tRAS tRC tPR tCRP tRCD tRSH tCRP tASR tRAD tASC tRRH tOEA tCLZ tCAC tOEZ tOFF Col Address Row Data Out RAS CAS Address WE OE I/O tAR tRAH tRCS tRAC tRAS tRC tRP tCRP tRCD tRSH tASR tRAH tRAD tAR tCAH tWCS tWCH tDS tDH Data In Col Address Row Address RAS UCAS, Address WE I/O OE tASC tRWL tWCR tWP tDHR tRAL LCAS

4/11/01; V.0.9.1 Alliance Semiconductor P. 21 of 25 CAS before RAS refresh counter test waveform tRAS tRSH tRP tCSRtCHR tCPT tCAS tCAH tCLZ tCAC tRCH tRRH tROH tOEA tRWL tCWL tWCS tWPtWCH tDS tDH tRCS tOEA tDS tDH Col Address Data Out Data In Data Out Data In RAS UCAS, LCAS Address I/O WE OE WE I/O OE WE OE I/O tOED tAA tCLZ tCAC tOEZ tWP tCWL tRCS tAA tOFF tAWD tCWD tRAL Read Cycle Write Cycle Read-Write Cycle

4/11/01; V.0.9.1 Alliance Semiconductor P. 22 of 25 CAS-before-RAS self refresh cycle Typical AC and DC characteristics tRP tRASS tRPC tCP tCHS tCEZ RAS UCAS, DQ LCAS tRPS tCSR tRPC Supply voltage (V) 4.0 5.5 6.0 5.0 4.5 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 Normalized access time Normalized access time tRAC Ambient temperature (°C) –55 125 –10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 Normalized access time Normalized access time tRAC Load capacitance (pF) 200 250 150 100 100 Typical access time Typical access time tRAC vs. ambient temperature Ta vs. load capacitance CL vs. supply voltage VCC Ta = 25°C –70 –60 –50 Supply voltage (V) 4.0 5.5 6.0 5.0 4.5 0.0 Supply current (mA) Typical supply current ICC Ambient temperature (°C) –55 125 –10 0.0 Supply current (mA) Typical supply current ICC Cycle rate (MHz) 0.0 Power-on current (mA) Typical power-on current IPO vs. ambient temperature Ta vs. cycle rate 1/tRC vs. supply voltage VCC

4/11/01; V.0.9.1 Alliance Semiconductor P. 23 of 25 Supply voltage (V) 4.0 5.5 6.0 5.0 4.5 Refresh current (mA) Typical refresh current ICC3 Ambient temperature (°C) 0.0 Refresh current (mA) Typical refresh current ICC3 Supply voltage (V) 4.0 5.5 6.0 5.0 4.5 0.5 1.5 2.0 1.0 2.5 3.0 3.5 Stand-by current (mA) Typical TTL stand-by current ICC2 vs. Ambient temperature Ta vs. supply voltage VCC vs. supply voltage VCC Ambient temperature (°C) 0.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 Stand-by current (mA) Typical TTL stand-by current ICC2 Output voltage (V) 0.0 1.5 2.0 1.0 0.5 0.0 Output sink current (mA) Typical output sink current IOL Output voltage (V) 0.0 3.0 4.0 2.0 1.0 0.0 Output source current (mA) Typical output source current IOH vs. output voltage VOL vs. output voltage VOH vs. ambient temperature Ta Fast page mode current (mA) Ambient temperature (°C) 0.0 Fast page mode current (mA) Typical fast page mode current ICC4 Supply voltage (V) 4.0 5.5 6.0 5.0 4.5 0.0 Typical fast page mode current ICC4 vs. supply voltage VCC vs. ambient temperature Ta

4/11/01; V.0.9.1 Alliance Semiconductor P. 24 of 25 Package dimensions Capacitance (f = 1 MHz, Ta = Room Temperature, VCC = 5V ±10%) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN1 A0 to A8 VIN = 0V pF CIN2 RAS, UCAS, LCAS, WE, OE VIN = 0V pF I/O capacitance CI/O I/O0 to I/O15 VIN = VOUT = 0V pF 44-pin TSOP II Min (mm) Max (mm) A 1.2 0.05 0.95 1.05 b 0.30 0.45 c 0.127 (typical) D 18.28 18.54 E 10.03 10.29 He 11.56 11.96 e 0.80 (typical) l 0.40 0.60 D He 1 2 3 4 5 6 7 8 91011121314 4443424140393837363534333231 1516 3029 17181920 28272625 c l e 40/44-pin TSOP II 0–5° E A b 40-pin SOJ 400 mil Min Max A 0.128 0.148 0.026 1.105 1.115 B 0.026 0.032 b 0.020 c 0.007 0.013 D 1.020 1.035 E 0.370 (typical) 0.395 0.405 0.435 0.445 e 0.050 (typical) e D Pin 1 b B c Seating Plane A 40-pin SOJ

4/11/01; V.0.9.1 Alliance Semiconductor P. 25 of 25 Ordering codes Part numbering system –25 ns –30 ns –35 ns –50 ns AS4C256K16F0-25JC AS4C256K16F0-30JC AS4C256K16F0-35JC AS4C256K16FO-50JC AS4C256K16F0-25JI AS4C256K16F0-30JI AS4C256K16F0-35JI AS4C256K16FO-50JI AS4C256K16F0-25TC AS4C256K16F0-30TC AS4C256K16F0-35TC AS4C256K16FO-50TC AS4C256K16F0-25TI AS4C256K16F0-30TI AS4C256K16F0-35TI AS4C256K16FO-50TI AS4C 256K16F0 –XX X C/I DRAM prefix Device number RAS access time Package: J = Plastic SOJ, 400 mil, 40-pin T = TSOP II, 400 mil, 40/44-pin Temperature Range: C= Commercial (0 °C to 70 °C) I= Industrial (-40°C to 85°C)