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Technical content
Features
- Fast access time: 5.4ns
- Fast clock rate: 143 MHz
- Self refresh mode: standard
- Internal pipelined architecture
- 512K word x 16-bit x 2-bank
- Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function
- Individual byte controlled by LDQM and UDQM
- Auto Refresh and Self Refresh
- 4096 refresh cycles/64ms
- CKE power down mode
- JEDEC standard +3.3V±0.3V power supply
- Interface: LVTTL
- 50-pin 400 mil plastic TSOP II package -Pb and Halogen Free Overview The AS4C1M16S SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C1M16S provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications
Table 1. Key Specifications Table 2. Ordering Information
Figure 1 Pin Assignment (Top View)
Figure 2. Block Diagram
Table 3. Pin Details of AS4C1M16S controls the output registers. Power Down and Self Refresh modes, providing low standby power. BankPrecharge command is being applied. the op-code during a Mode Register Set command. considered part of the command code. designated by BA is switched to the idle state after the precharge operation.
DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are byte-maskable during Reads and Writes. NC - No Connect: These pins should be left unconnected. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VDD Supply Power Supply: 3.3V ± 0.3V VSS Supply Ground
4 shows the truth table for the operation commands. Table 4. Truth Table (Note (1), (2))
- CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
- These are states of bank designated by A11 signal.
- Device state is 1, 2, 4, 8, and full page burst operation.
- Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
1 BankActivate
used, the Write command and the Block Write command perform the no mask write operation. Figure 3. BankActivate Command Cycle (Burst Length = n)
2 BankPrecharge command
and is ready to be activated again.
3 PrechargeAll command
banks are not in the active state. Both banks are then switched to the idle state.
4 Read command
5 Read and AutoPrecharge command
command and the auto precharge function is ignored.
6 Write command
the page it will wrap to column 0 and continue). Figure 10. Burst Write Operation (Burst Length = 4) BankPrecharge/PrechargeAll, or Read command before the end of the burst length. (refer to the following figure). Figure 11. Write Interrupted by a Write (Burst Length = 4) registered, the data inputs will be ignored and writes will not be executed.
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) command is entered (refer to the following figure). Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2. Figure 13. Write to Precharge
7 Write and AutoPrecharge command (refer to the following figure)
in this command and the auto precharge function is ignored. Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
0 Sequential
1 Interleave
8 Mode Register Set command
the clock cycle requirements during operation as long as both banks are in the idle state. Table 5. Mode Register Bitmap
0 RFU* WBL Test Mode CAS# Latency BT Burst Length
0 Burst
1 Single Bit
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle. Figure 15. Mode Register Set Cycle
- Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 1, 2, 4, 8, or full page.
Table 6. Burst length
- Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8.
Table 7. Addressing Mode Select Field
- Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 8. Burst Definition
2 X X 0 0, 1 0, 1
- CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC (min) ≤ CAS# Latency X tCK
Table 9. CAS Latency
1 X X Reserved
- Test Mode field (A8~A7) These two bits are used to enter t he test mode and must be programmed to "00" in normal operation.
Table 10. Test Mode field
1 X Vendor Use Only
- Write Burst Length (A9) This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected.
Table 11. Write Burst Length
0 Burst-Read-Burst-Write
1 Burst-Read-Single-Write
Note: A11 should stay “L” during mode set cycle.
9 No-Operation command
Low). This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
burst is shown in the following figure.
Figure 16. Termination of a Burst Read Operation (Burst Length ＞ 4, CAS# Latency = 2, 3) Figure 17. Termination of a Burst Write Operation (Burst Length = X)
11 Device Deselect command
12 AutoRefresh command
13 SelfRefresh Entry command
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for t XSR (min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when both banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operati on of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. t PDE (min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Table 12. Absolute Maximum Rating Table 13. Recommended D.C. Operating Conditions (TA = 0~70°C) Table 14. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C) Note: These parameters are periodically sampled and are not 100% tested.
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
- Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
- These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
- These parameters depend on the output loading. Specified values are obtained with the output open.
- Power-up sequence is described in Note 12.
Table 17. LVTTL Interface
- Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
- tHZ defines the time in which the outputs achieve the open circuit conditi on and are not at reference levels.
- These parameters account for the number of clock cycle and depend on the operating frequency of the
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
- Assumed input rise and fall time tT (tR & tF) = 1 ns
ns should be added to the parameter. Power up must be performed in the following sequence. signals are held "NOP" state. recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register.
- The Auto Refresh command can be issue before or after Mode Register Set command.
Figure 19. AC Parameters for Write Timing (Burst Length=4)
Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2)
Figure 22. Power on Sequene and Auto Refresh
Figure 23. Self Refresh Entry & Exit Cycle
- CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
- After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
- The device remains in SelfRefresh mode as long as CKE stays "low".
- Once the device enters SelfRefresh mode, minimum t RAS is required before exit from SelfRefresh.
- System clock restart and be stable before returning CKE high.
- Enable CKE and CKE should be set high for valid setup time and hold time.
- Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
- 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 A0-A9 DQM RAx RAx CAx Hi-Z DQ Ax0 Ax1 Ax2 Ax3 tHZ Activate Command Bank A Read Command Bank A Clock Suspend
1 Cycle
2 Cycl es
3 Cycl es
Don’t Care
Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 A0-A9 DQM RAx RAx CAx Hi-Z DQ Ax0 A x1 Ax2 Ax3 tHZ Activate Command Bank A Read Command Bank A Clock Suspend
1 C ycle
2 C ycles
Don’t Care
Figure 25. Clock Suspension During Burst Write (Using CKE)
Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2)
Figure 27.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAw RAz A0-A9 DQM RAw CAw CAx CAy RAz CAz Hi-Z DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 A y1 Ay2 Ay3 Az0 Activate Read Read Read Precharge Activate Read Command Command Command Command Command Command Command Bank A Bank A Bank A Bank A Bank A Bank A Bank A Don’t Care
Figure 27.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAw RAz A0-A9 DQM RAw CAw CAx CAy RAz CAz Hi-Z DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 A y1 Ay2 Ay3 Activate Read Read Read Precharge Activate Read Command Command Command Command Command Command Command Bank A Bank A Bank A Bank A Bank A Bank A Bank A Don’t Care
Figure 28. Random Column Write (Page within same Bank)
Figure 29.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS# RAS# CAS# WE# A11 A10 RBx RAx RBy A0-A9 RBx CBx RAx CAx RBy CBy DQM tRCD tAC tRP Hi-Z DQ Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 B x7 Ax0 Ax1 Ax2 Ax3 Ax4 A x5 Ax6 Ax7 Activate Read Activate Read Activate Read Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Precharge Command Bank B Don’t Care
Figure 29.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS# RAS# CAS# WE# A11 A10 RBx RAx RBy A0-A9 DQM RBx tRCD CBx tAC RAx CAx RBy CBy tRP Hi-Z DQ Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 A x5 Ax6 Ax7 By0 Activate Read Activate Read Precharge Activate Read Precharge Command Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank B Bank A Don’t Care
Figure 30. Random Row Write (Interleaving Banks)
Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 DQM RAx CAx CAy CAz Hi-Z DQ Ax0 Ax1 Ax2 A x3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Read Write The Write Data Read The Read Data Command Command Command is Masked with a Command is Masked with a Bank A Bank A Bank A Zero Clock Bank A Two Clock Latency Latency Don’t Care
Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAx A0-A9 DQM RAx CAx CAy CAz Hi-Z DQ Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Read Command Write Command The Write Data is Masked with a The Read Da ta is Masked with a Bank A Bank A Bank A Zero Clock Latency Read Command Bank A Two Clock Latency Don’t Care
Figure 32.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 DQM RAx tRCD CAy RBx CBw CBx CBy CAy CBz Hi-Z DQ tAC Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Read Activate Read Read Read Read Read Precharge Precharge Command Command Command Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank A Bank B Bank A Bank B Don’t Care
Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# RAS# CAS# WE# A11 A10 RAx RBx A0-A9 DQM RAx tRCD CAx RBx CBx CBy CBz CAy Hi-Z DQ tAC Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 B y1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3 Activate Read Read Read Read Read Precharge Precharge Command Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank A Bank B Bank A Activate Command Bank B Don’t Care
Figure 33. Interleaved Column Write Cycle (Burst Length=4)
Figure 34.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# High Begin Auto Precharge Bank B Begin Auto Precharge Bank A RAS# CAS# WE# A11 A10 RAx RBx RBy RAz A0-A9 DQM RAx CAx RBx CBx CAy RBy CBy tRP RAz Hi-Z DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 A y1 Ay2 Ay3 By0 By1 By2 Activate Read Activate Read with Read with Activate Read with Activate Command Command Command Auto Precharge Auto precharge Command Auto Precharge Command Bank A Bank A Bank B Command Command Bank B Command Bank A Bank B Bank A Bank B Don’t Care
Read with Command Command Auto Precharge Auto Precharge Command Auto Precharge Bank A Bank A Command Command Bank B Command Activate Command Bank B Bank B Bank A Bank B AS4C1M16S Figure 34.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS# High Begin Auto Precharge Bank B Begin Auto Precharge Bank A RAS# CAS# WE# A11 A10 RAx RBx RBy A0-A9 DQM RAx CAx RBx CBx CAy tRP RBy CBy Hi-Z DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 Don’t Care
Figure 35. Auto Precharge after Write Burst (Burst Length=4)
Figure 36.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS# RAS# CAS# WE# A11 A10 RAx RBx RBy A0-A9 DQM RAx CAx RBx CBx tRP RBy Hi-Z DQ Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Activate Read Activate The burst counter wraps Read Precharge Activate Command Command Command from the highest order Command Command Command Bank A Bank A Bank B page address back to zero Bank B during this time interval Full Page burst operation does not terminate when the burst leng th is satisfied; the burst counter increments and continues bursting beginning with the starting address Bank B Burst Stop Command Bank B Don’t Care
Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS# RAS# CAS# WE# A11 A10 RAx RBx RBy A0-A9 DQM RAx CAx RBx CBx tRP RBy Hi-Z DQ Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Activate Command Bank A Read Command Bank A Activate Command Bank B The burst counter wraps from the highest order Read Command Bank B Precharge Command Bank B Burst Stop Activate Command Bank B Don’t Care page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is sati sfied; the burst counter increments and c ontinues bursting beginning with the starting address Command
Figure 37. Full Page Write Cycle (Burst Length=Full Page)
Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=2)
Figure 39. Random Row Read (Interleaving Banks)
Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
Figure 41. Full Page Random Column Write (Burst Length=Full Page)
Figure 42. Precharge Termination of a Burst
Figure 43. 50 Pin TSOP II Package Outline Drawing Information
- Dimension D&E do not include interlead flash.
- Dimension B does not include dambar protrusion/intrusion.
- Dimension S includes end flash.
- Controlling dimension: mm
ORDERING INFORMATION
AS4C1M16S-7TCN 1M x 16 3.3V+/-0.3V 50 pin TSOP III Commercial 143 PART NUMBERING SYSTEM AS4C 1M16S 7 T = TSOP Package C N SDRAM prefix S = SDRAM 16Mb (1M x 16) Speed 50 pin TSOP II Temperature Range: C = Commercial (0°C to +70°C) N = Lead Free ROHS Compliant Part