AS4C16M32SC-7TIN

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512M SDRAM 54/86pin TSOP II Package Revision Details Date Rev 1.0 Preliminary datasheet Sep. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 1 of 24 - Rev.1.0 Sep. 2018

1 Overview

1.1 Features

Table 1. Key Specifications Table 2. Ordering Information

• Fast clock rate: 133 MHz
• Programmable Mode registers - CAS Latency: 1 or 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleave d
• Auto Refresh and Self Refresh
• 8192 refresh cycles/64ms(7.8 µs) T≦85°C
• Power down mode
• Single +3.3V±0.3V power supply
• Operating Temperature Range: - Industrial: TA = -40~85°C
• Interface: LVTTL - Pb free and Halogen free Fully Synchronous to Positive Clock Edge Four Banks controlled by BA0 & BA1 Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read / Write control (x8, x16, x32) Data Mask for Byte Control (x16,x32) Random Column Address every CLK (1-N Rule) Available in 86/54 Pin 400 mil plastic TSOP II package,TSOPII–54 (x8, x16) TSOPII–86 (x32)

1.2 Description

The AS4C16M32SC-7TIN, AS4C32M16SC-7TIN and AS4C64M8SC-7TIN are four bank Synchronous DRAMs organized as 4 banks x 4MBit x32, 4 banks x 8Mbit x 16 and 4 banks x 16MBit x 8 MBit x 8 respectively. Thes e synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 3 of 24 - Rev.1.0 Sep. 2018 Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. All 512-Mbit components are available in TSOPII–[86/54] packages. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically.All of the control, address, data input and output circuits are synchronized with the positive edge externally supplied clock.

2 Configuration

This chapter contains the pin configuration table, the TSOP package drawing,

2.1 Pin Description

Listed below are the pin configurations sections for the various signals of the SDRAM Table 3. Configuration TSOP-54/86 Name Pin Type Buffer Type Function Clock Signals CLK I LVTTL Clock Signal CK CKE I LVTTL Clock Enable Note: Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode. Control Signals RAS I LVTTL Row Address Strobe CAS I LVTTL Column Address Strobe WE I LVTTL Write Enable CS I LVTTL Chip Select Address Signals BA0~BA1 I LVTTL Bank Address Signals 1:0 Note: Bank Select Inputs. Bank address inputs selects which of the four banks a command applies to. A0~A12 I LVTTL Address Signal 9:0, Address Signal 10/Auto precharge Note: During a Bank Activate command cycle, A0-A12 define the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0-CAn) when sampled at the rising clock edge. CAn depends upon the SDRAM organization: 64M x8SDRAM CAn = CA9,CA11 (Page Length = 2048 bits) 32M x16SDRAM CAn = CA9 (Page Length = 1024 bits) 16M x32SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10 (= AP) is used to invoke the auto pre charge operation at the end of the burst read or write cycle. If A10 is high, auto pre charge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, auto pre charge is disabled. During a Precharge c ommand cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 4 of 24 - Rev.1.0 Sep. 2018

DQ0~DQ31 I/O LVTTL Data Signal 31:0 DQM(x8)/ LDQM(x16)/ DQM0(x32) I LVTTL Data Mask for DQ0~DQ7 UDQM(x16)/ DQM1(x32) I LVTTL Data Mask for DQ8~DQ15 DQM2(x32) I LVTTL Data Mask for DQ16~DQ23 DQM3(x32) I LVTTL Data Mask for DQ24~DQ31 Power Supplies VDDQ Suply – Power Supply for DQs VDD Suply – Power Supply VSSQ Suply – Power Supply Ground for DQs VSS Suply – Power Supply Ground Not Connected NC NC — Not Connected AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 5 of 24 - Rev.1.0 Sep. 2018

Configuration for x32 Organization, TSOP86, Top View AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 6 of 24 - Rev.1.0 Sep. 2018

Configuration for x16 Organization, TSOP-54, Top View AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 7 of 24 - Rev.1.0 Sep. 2018

Configuration for x8 Organization, TSOP-54, Top View AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 8 of 24 - Rev.1.0 Sep. 2018

3 Functional Description

3.1 Operation Definition

1) V = Valid, x = Don’t Care, L = Low Level, H = High Level 2) CKEn signal is input level when commands are provided, CKEn -1 signal is input level one clock before the commands are Provided 3) This is the state of the banks designated by BA0, BA1 signals. 4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock su spend mode. All of SDRAM operations are defined by states of control signals , , , , and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. CS RAS CAS WE AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 9 of 24 - Rev.1.0 Sep. 2018

3.2 Initialization

The default power on state of the mode register is supplier specific and may be undef ined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VD D and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the in itial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.

3.3 Mode Register Definition

The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields. First, a Burst Length field whi ch sets the length of the burst. Second, an Addressing Selection bit which programs the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency field to set the access time at clock cycle. Fourth, an Operation mode field t o differentiate between normal operation (Burst read and burst Write) and special Burst Read and Single Write mode. After the initial power up, the mode set operation must be done before any activate command. Any content of the mode register can be altered by re- executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at th e positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 reserved weak OCD wrbst reserved CL BT BL AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 10 of 24 - Rev.1.0 Sep. 2018

Field Bits Type1) Description BL [2:0] W Burst Length 000B1, 001B 2, 010B 4, 011B 8, 111B Full Page (Sequential burst type only), BT [3] Burst Type

0 Sequential

1 Interleaved

[6:4] CAS Latency CL Note: All other bit combinations are RESERVED. 010B 2 011B 3 MODE [8:7] RESERVED wrbst [9] Write Burst Mode 0BProgrammed Burst Length, 1BSingle Location Access, Weak [10] Weak OCD Mode OCD 0Bnormal OCD, 1Bweak OCD, MODE [12:11] RESERVED 1) W = write only register bit AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 11 of 24 - Rev.1.0 Sep. 2018

3.4 Burst Type

Accesses within a given burst may be programmed to be sequential or interleaved; as shown in table 6. Table 6 Burst Definition Burst Length Starting Column Address Order of Accesses Within a Burst A2 A1 A0 Type = Sequential Type = Interleaved 2 0 0-1 0-1 1 1-0 1-0 Full page n Cn, Cn+1, Cn+2 not supported Notes 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wr aps within the block. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 12 of 24 - Rev.1.0 Sep. 2018

3.5 Commands

SDRAM has two re fresh modes, Au to R efresh and Se lf Refresh. Au to R efresh is s imilar to t he CAS -before-RAS re fresh of conventional D RAMs. A ll b anks must b e p recharged before applying a ny re fresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is r equir ed for bot h refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and C KE and WE are held high at a clock timing. The mode restores w or d line after the refresh and no external precharge command is nec essary. A mi nimum tRC time is r equired between t wo a utomatic refreshes in a burst r efresh mode. The s ame rule applies to any ac cess command after the aut omatic r efresh operation. Th e chip h a s an o n -chip timer and the S elf R efresh mode is a vailable. The mode restores t he word l ines a fter, RAS CAS and CKE are l ow and WE is h igh at a clock timing. All o f external control signals including t he clock are disabled. R eturni ng CKE to high enables the clock and i nitiates the refresh exit oper ation. After the exit command, a t l east one tRC delay is required prior to any access command. Au to P recharge Tw o methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (“write recovery time”) after the last data in. A burst operation with Auto-Precharge may only be interrupted by a burst start to another bank. It must not be i nterrupted by a precharge or a burst stop command. Precharge Command Th ere is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR (“write recovery time”) of 2 clocks minimum from the last data out to apply the precharge command. Table 7 Bank Selection by Address Bits A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3

1 X X All Banks

Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 13 of 24 - Rev.1.0 Sep. 2018

3.6 Operations

When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by RAS setting high and CAS low at a clock timing after a necessary delay, tRCD from the RAS timing. WE is used to define either a read(WE=H) or a write(WE=L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation does not self terminate once the burst length has been reached. In other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to “high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE “high“. One clock delay is required for Power Down mode entry and exit. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 14 of 24 - Rev.1.0 Sep. 2018

4 Electrical Characteristics

4.1 Table 8 Absolute Maximum Ratings Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods m ay affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 9 Operating Temperature Symbol Parameter Rating Unit Note/ Test Condition Min Max Toper Operating temperature °C – 40 85 Industrial temperature range 1) Operating Temperature is the operating ambient temperature surrounding the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 15 of 24 - Rev.1.0 Sep. 2018 Symbol Item Values Unit Note -1.0 ~ 4.6 V VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V TA Ambient Temperature °C Industrial -40 ~ 85 °C TSTG Storage Temperature -55 ~ 105 °C TSOLDER So ldering Temperature (10 seconds) 260 PD Power Dissipation 1 W IOS Short Circuit Output Current 50 mA

Parameter Symbol Values Unit Note/ Test Condition Min. Max. Supply Voltage VDD 3.0 3.6 V 2) I/O Supply Voltage VDDQ 3.0 3.6 V 2) Input high voltage VIH 2.0 VDDQ+0.3 V 2)3) Input low voltage VIL – 0.3 +0.8 V 2)3) Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V 2) Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V 2) Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL – 10 +10 µA – Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ) IOL – 10 +10 µA – 1) All voltages are referenced to VSS Pulse width measured at 50% points with amplitude meas ured peak to DC reference. Table 11 Input and Output Capacitances Input Capacitances: CK, CK CI1 Input Capacitance (A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) CI2 Input/Output Capacitance (DQ) CI0 1) VDD, VDDQ = 3.3 V ± 0.3 V, f = 1 MHz AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 16 of 24 - Rev.1.0 Sep. 2018 Symbol Parameter Min. Max. Unit 2.5 3.5 pF 2.5 3.8 pF 4.0 6.0 pF

D.C. Characteristics (VDD = 3.3V ± 0.3V) Notes: 1. These parameters depend on the cycle rate and these values a re measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. 3. The temperature from -40°C~85°C AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 17 of 24 - Rev.1.0 Sep. 2018 X32 X16 X8 Operating Current tRC = tRC(min),tRC = tck(min),Burst length=1,One bank active IDD1 70 60 60 mA 1,3 Precharge Standby Current in non-power down mode tCK =min, CS# = VIH,CKE≥ VIL(max) IDD2N 15 15 15 mA 3 Precharge Standby Current in Power Down Mode tCK = min. CS =VIH,CKE≤ VIL(max), IDD2P 4 4 4 mA 1,3 No Operating Current Active state (max. 4 banks) CS = VIH(min), CKE ≥VIH(min.),tCK = min, IDD3N 20 20 20 mA 3 No Operating Current Active state (max. 4 banks) CS = VIH(min), CKE ≤ VIL(max.) tCK = min, IDD3P 6 6 6 mA 3 Burst Operating Current Read/Write command cycling tCK = min IDD4 90 80 70 mA 1,2,3 Auto Refresh Current Auto Refresh command cycling tRC= tRC(min),tCK = min IDD5 170 170 170 mA 1,3 Self Refresh Current Self Refresh Mode, CKE≤ 0.2V, tCK=infinity IDD6 5 5 5 mA 3 IDDmaxDescription/Test condition Symbol Unit Notes

AC Characteristics 4.2 Table 13 1. VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns 2. For proper power-up see the operation section of this data sheet. AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 18 of 24 - Rev.1.0 Sep. 2018 Symbol A.C. Parameter tRC Row cycle time (same bank) 66 - ns tRFC Row Cycle Time during Auto Refresh 66 - tRCD Row to Column Delay Time 15 - tRP Row Precharge Time 15 - tRRD Row activate to row activate delay (different banks) 15 - tMRD Mode register set cycle time 2 - tRAS Row activate to precharge time (same bank) 44 120K tWR Write recovery time 15 - tCK Clock cycle time CL* = 1 20 - CL* = 2 10 - 7.5 - tAC Access time from CLK (positive edge) CL* = 2 - 6 3,4, CL* = 3 - 5.4 tOH Data output hold time 2.7 - 3,5 tLZ Data output low impedance 1 - tHZ Data output high impedance 5.4 tDDE Power Down Exit set -up time 7.5 0 tREF Refresh Period (8192 cycles) - 64 ms tXSR Exit Self-Refresh to any Command 75 - ns Min. Max. Unit Note tck CL* = 3 ns CL* = 1 17 tCH Clock High Pulse Width tCL Clock Low Pulse Width tIS Data/Address/Control Input set -up time 1.5 - 6 tIH Data/Address/Control Input hold time 0.8 - 6 2.5 - 2.5 tCCD CAS# to CAS# Delay time - tck CL* = 2 CL* = 3 CL* = 1 ns tDQZ DQM Data Out Disable Latency tDAL(min.) Last Data Input to Activate (Write with Auto Precharge) tT Transition time 0.3 1.2 tDQW DQM Write Mask Latency - tck - tck ns

measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V /ns edge rate betw een 0.8 V and 2.0 V. 4. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 6. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7. These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fract ions as a whole number) 8. It is recommended to use two clock cycles between the last data -in and the precharge command in case of a write command without Auto-Precharge. One clock cycle between the last data -in and the precharge command is also supported, bu t restricted to cycle times tCK greater or equal the specified tWR value, where tck is equal to the actual system clock time. 9. When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Comm and can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time. Figure 4 AC Output Load Circuit Diagram / Timing Reference Load AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential - 19 of 24 - Rev.1.0 Sep. 2018

5 Package Outlines

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Alliance Memory, Inc.

511 Taylor Way,

San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS4C 16M32SC 32M16SC 64M8SC -7 T I N XX DRAM 16M32=16M x 32 32M16=32M x 16 64M8=64M x 8 S=SDRAM C=C die 7=133 MHz T=TSOP I=Industrial temp -40°C~ 85°C Indicates Pb and Halogen Free Packing Type None:Tray TR:Reel AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Confidential Rev.1.0 Sep. 2018 - 24 of 24 -