AS4C16M16SA-6BIN ALSC | Alldatasheet
Document overview
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Technical content
AS4C16M16SA-C&I Confidential 0 Rev. 3.0 Mar./2015
Revision History
Rev 1.0 Preliminary datasheet February 2014 Rev 2.0 Correct some typing mistakes. March 2014 Rev 3.0 1. Add AS4C16M16SA-6TCN part. 2. Modify ordering information. 3. Add part number system on the last page. March 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice.
AS4C16M16SA-C&I Confidential 1 Rev. 3.0 Mar. /2015 256M – (16Mx16bit) Synchronous DRAM (SDRAM) Confidential Advanced(Rev. 3.0, Mar. /2015)
Features
Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function Operating temperature range - Commercial (0 ~ 70° C) - Industrial (-40 ~ 85° C) Auto Refresh and Self Refresh 8192 refresh cycles/64ms CKE power down mode Single +3.3V ±0.3V power supply Interface: LVTTL 54-pin 400 mil plastic TSOP II package 54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package - All parts ROHS are compliant Overview The 256Mb SDRAM is a hig h-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM ar e burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self -timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth an d particularly well suited to high performance PC applications. Table 1. Key Specifications Table 2. Ordering Information
Figure 2. Block Diagram
Table 3. Pin Details deactivating the clock controls the entry to the Power Down and Se lf Refresh modes. providing low standby power. BA0,BA1 Input Bank Activate: BA0, BA1 input select the bank for operation. the BankActivate command or the Precharge command is selected by the WE# signal. to the idle state after the precharge operation. used to select the BankActivate or Precharge command and Read or Write command.
AS4C16M16SA-C&I Confidential 5 Rev. 3.0 Mar. /2015 DQ0-DQ15 Input / Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskabled during Reads and Writes. NC - No Connect: These pins should be left unconnected. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. ( 0 V ) VDD Supply Power Supply: +3.3V 0.3V VSS Supply Ground
shows the truth table for the operation commands. Table 4. Truth Table (Note (1), (2))
- CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
- These are states of bank designated by BA signal.
- Device state is 1, 2, 4, 8, and full page burst operation.
- Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
1 BankActivate
write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. Figure 3. BankActivate Command Cycle (Burst Length = n)
2 BankPrecharge command
3 PrechargeAll command
are not in the active state. All banks are then switched to the idle state.
4 Read command
of the page it will wrap to column 0 and continue).
5 Read and AutoPrecharge command
auto precharge function is ignored.
6 Write command
write bursts, the first valid data -in element will be registered coincident with the Write command. figure). The DQs remain with high -impedance at the end of the burst unless another command is initiated. full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). Figure 10. Burst Write Operation (Burst Length = 4) Figure 11. Write Interrupted by a Write (Burst Length = 4) and writes will not be executed.
Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Figure 13. Write to Precharge
7 Write and AutoPrecharge command
and the auto precharge function is ignored.
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data)
Register after power-up are undefined; therefore this command must be issued at the power -up sequence. long as all banks are in the idle state. Table 5. Mode Register Bitmap
0 Burst 0 0 Normal 0 Sequential
1 Single Bit 1 0 Vendor Use Only 1 Interleave
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
Figure 15. Mode Register Set Cycle to be 2, 4, 8, or full page. Table 6. Burst Length Field supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8. Table 7. Addressing Mode Select Field
0 Sequential
1 Interleave
Table 8. Burst Definition
2 X X 0 0, 1 0, 1
This field specifies the number of clock cycles from the assertion of the Read command to the first read data. satisfying the following formula must be programmed into this field. Table 9. CAS Latency
1 X X Reserved
These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 10. Test Mode
1 X Vendor Use Only
selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected. Table 11. Write Burst Length
0 Burst-Read-Burst-Write
1 Burst-Read-Single-Write
Note: A10 and BA0, 1 should stay “L” during mode set cycle.
9 No-Operation command
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
AS4C16M16SA-C&I Confidential 16 Rev. 3.0 Mar. /2015
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A12 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non -persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 8192 times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A12 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Onc e the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRe fresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
This command is used to exit from the SelfRefresh mode. Once thi s command is registered, NOP or Device Deselect commands must be issued for tXSR(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a b urst of 8192 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CL K is suspended (masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the Power Down mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH" , the comma nd should be NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. t PDE (min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system.
Table 12. Absolute Maximum Rating Table 13. Recommended D.C. Operating Conditions (TA = -40~85°C) Table 14. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C) Note: These parameters are periodically sampled and are not 100% tested.
Description/Test condition Symbol - 6 -7 Unit Note Max.
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions
- Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
- All voltages are referenced to V SS. Overshoot VIH (Max) = 4.6V for pulse width ≤ 3ns. Undershoot VIL (Min) =
-1.0V for pulse width ≤ 3ns.
- These parameters depend on th e cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
- These parameters depend on the output loading. Specified values are obtained with the output open .
- Power-up sequence is described in Note 11.
Table 17. LVTTL Interface
- Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed slope
- tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
- If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
- Assumed input rise and fall time tT (tR & tF) = 1 ns
Power up must be performed in the following sequence. signals are held "NOP" state. recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
Figure 19. AC Parameters for Write Timing (Burst Length=4)
Figure 20. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2)
Figure 22. Power on Sequence and Auto Refresh
Figure 23. Self Refresh Entry & Exit Cycle
- CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
- After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
- The device remains in SelfRefresh mode as long as CKE stays "low".
- Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
- System clock restart and be stable before returning CKE high.
- Enable CKE and CKE should be set high for valid setup time and hold time.
- Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
- 8192 cycles o f burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
AS4C16M16SA-C&I Confidential 26 Rev. 3.0 Mar. /2015 Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx Activate Command Bank A Read Command Bank A Ax0 Ax1 Ax2 Ax3 tHZ Clock Suspend
1 Cycle
2 Cycles
3 Cycles
CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
AS4C16M16SA-C&I Confidential 27 Rev. 3.0 Mar. /2015 Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx Activate Command Bank A Read Command Bank A Ax0 Ax1 Ax2 Ax3 tHZ Clock Suspend CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
Figure 25. Clock Suspension During Burst Write (Using CKE)
Figure 26. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=2)
AS4C16M16SA-C&I Confidential 30 Rev. 3.0 Mar. /2015 Figure 27.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAw RAw CAx Aw0 Aw1 Ay2 Precharge Command Bank A RAz CAw CAy RAz CAz Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay3 Az0 Read Command Bank A Read Command Bank A Activate Command Bank A Read Command Bank A CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
AS4C16M16SA-C&I Confidential 31 Rev. 3.0 Mar. /2015 Figure 27.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAw RAw CAx Aw0 Aw1 Ay2 Precharge Command Bank A RAz CAw CAy RAz CAz Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay3 Read Command Bank A Read Command Bank A Activate Command Bank A Read Command Bank A CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
Figure 28. Random Column Write (Page within same Bank)
AS4C16M16SA-C&I Confidential 33 Rev. 3.0 Mar. /2015 Figure 29.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank B T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank B RBx RBx RAx Bx0 Bx1 Ax0 Precharge Command Bank B CLK RBy CBx CAx RBy CBy Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax1 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B CS# CKE WE# A10 Ax6 Ax7 High RAx Ax2 Ax3 Ax4 Ax5 tRCD tAC tRP A0-A9, A11-A12 DQM DQ BA0,1 RAS# CAS#
AS4C16M16SA-C&I Confidential 34 Rev. 3.0 Mar. /2015 Figure 29.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank B T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank B RBx RBx RAx Bx0 Bx1 Ax0 Precharge Command Bank B RBy CBx CAx RBy CBy Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax1 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Ax6 Ax7 High RAx Ax2 Ax3 Ax4 Ax5 tRCD tAC tRP Precharge Command Bank A By0 CLK CS# CKE WE# A10 A0-A9, A11-A12 DQM DQ BA0,1 RAS# CAS#
Figure 30. Random Row Write (Interleaving Banks)
AS4C16M16SA-C&I Confidential 36 Rev. 3.0 Mar. /2015 Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx DAy1 CAx CAz Ax0 Ax1 Ax2 Ax3 DAy0 Write Command Bank A The Write Data is Masked with a Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency Az1 Az3 CAy DAy3 Az0 CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
AS4C16M16SA-C&I Confidential 37 Rev. 3.0 Mar. /2015 Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx DAy1 CLK CAx CAz Ax0 Ax1 Ax2 Ax3 DAy0 Write Command Bank A The Write Data is Masked with a Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ Az1 Az3 CAy DAy3 Az0
AS4C16M16SA-C&I Confidential 38 Rev. 3.0 Mar. /2015 Figure 32.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx RBx Ax0 Ax1 By0 Read Command Bank A RBx CAy CBw Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By1 Activate Command Bank B Read Command Bank B Read Command Bank B Precharge Command Bank B Bz2 Bz3 CBx CBy CAy CBz tRCD tAC Read Command Bank B Read Command Bank B Bz0Ay0 Ay1 Bz1 Precharge Command Bank A CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
AS4C16M16SA-C&I Confidential 39 Rev. 3.0 Mar. /2015 Figure 32.2. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx RBx Ax0 Ax1 Bz0 Precharge Command Bank B RBx CAx CBx Ax2 Ax3 Bx0 Bx1 By0 By1 Bz1 Activate Command Bank B Read Command Bank B Precharge Command Bank A CBy CBz CAy tRCD tAC Read Command Bank B Read Command Bank A Ay2Ay0 Ay1 Ay3 Read Command Bank B CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
Figure 33. Interleaved Column Write Cycle (Burst Length=4)
AS4C16M16SA-C&I Confidential 41 Rev. 3.0 Mar. /2015 Figure 34.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx CBx Ax0 Ax1 Bx0 Read with Auto precharge Command Bank A RAz CAx CAy RBy CBy Ax2 Ax3 Bx1 Activate Command Bank B Read with Auto Precharge Command Bank B Activate Command Bank B Activate Command Bank A Ay2 Ay3 High RBx Bx2 Bx3 Ay0 Ay1 tRP RBy RBx RAz By2By0 By1 Read with Auto Precharge Command Bank B Begin Auto Precharge Bank B Begin Auto Precharge Bank A CLK CS# CKE WE# A10 A0-A9, A11-A12 DQM DQ BA0,1 RAS# CAS#
AS4C16M16SA-C&I Confidential 42 Rev. 3.0 Mar. /2015 Figure 34.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx RBx Bx2 RBx CAx CBx Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx3 Activate Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B CAy Activate Command Bank B Ay2Ay0 Ay1 Ay3 Read with Auto Precharge Command Bank B RBy tRP Begin Auto Precharge Bank B Begin Auto Precharge Bank A RBy CBy By2By0 By1 High CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ
Figure 35. Auto Precharge after Write Burst (Burst Length=4)
AS4C16M16SA-C&I Confidential 44 Rev. 3.0 Mar. /2015 Figure 36.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx Ax+1 RBx CAx RBx Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Bx Activate Command Bank B Read Command Bank B Precharge Command Bank B CBx Burst Stop Command Bx+3Bx+1 Bx+2 Bx+4 The burst counter wraps from the highest order page address back to zero during this time interval tRP RBy RBy Bx+5 Bx+6 High Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Bursting beginning with the starting address Activate Command Bank B CLK CS# CKE WE# A10 DQ RAS# CAS# BA0,1 A0-A9, A11-A12 DQM
AS4C16M16SA-C&I Confidential 45 Rev. 3.0 Mar. /2015 Figure 36.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care Activate Command Bank A T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Read Command Bank A RAx RAx Ax+1 RBx CAx RBx Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Bx Activate Command Bank B Read Command Bank B Precharge Command Bank B CBx Burst Stop Command Bx+3Bx+1 Bx+2 Bx+4 The burst counter wraps from the highest order page address back to zero during this time interval tRP RBy RBy Bx+5 High Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Bursting beginning with the starting address Activate Command Bank B CLK CS# CKE WE# A10 DQ RAS# CAS# BA0,1 A0-A9, A11-A12 DQM
Figure 37. Full Page Write Cycle (Burst Length=Full Page)
Figure 38. Byte Read and Write Operation (Burst Length=4, CAS# Latency=2)
Figure 39. Random Row Read (Interleaving Banks)
Figure 40. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
Figure 41. Full Page Random Column Write (Burst Length=Full Page)
Figure 42. Precharge Termination of a Burst
Figure 43. 54 Pin TSOP II Package Outline Drawing Information
Figure 44. 54 Ball TFBGA Package Outline Drawing Information
AS4C16M16SA-C&I Confidential 54 Rev. 3.0 Mar. /2015 PART NUMBERING SYSTEM AS4C 16M16SA 6/7 T/B C/I N DRAM 16M16=16Mx16 SA=SDRAM（A version） 6=166MHz 7=143MHZ T = TSOP II B = FBGA C=Commercial (0° C ～ 70° C) I=Industrial (-40° C ～ 85° C) Indicates Pb and Halogen Free Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 200 7 Alliance Memo ry, Inc. All rights reserved. Our three -point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make cha nges to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchas e of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical c omponents in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.