AS4C16M16D1 ALSC | Alldatasheet
Document overview
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Technical content
Features
Fast clock rate: 200MHz Differential Clock CK & CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 4M x 16-bit for each bank Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved Individual byte-write mask control DM Write Latency = 0 Auto Refresh and Self Refresh 8192 refresh cycles / 64ms Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C) Precharge & active power down Power supplies: VDD & VDDQ = 2.5V 0.2V Interface: SSTL_2 I/O Interface Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free Package: 60-Ball, 8x13x1.2 mm (max) TFBGA - Pb free and Halogen Free Table 1.Ordering Information T: indicates TSOP II package B: indicates TFBGA package C: indicates Commercial temp. I: indicates Industrial temp. N: indicates lead free ROHS Overview The AS4C16M16D1 SDRAM is a high -speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 4M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK .d Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C16M16D1 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self -timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, AS4C16M16D1 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory band -width, result in a device particularl y well suited to high performance main memory and graphics applications. Part Number Clock Data Rate Package Temperature Temp Range AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial 0 ~ 70°C AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII Industrial -40 ~ 85°C AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial 0 ~ 70°C AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA Industrial -40 ~ 85°C
Figure 2. Block Diagram
Table 2. Pin Details counter and controls the output registers. the Power Down and Self Refresh modes. BankPrecharge command is being applied. WE signals and is latched at the positive edges of CK. switched to the idle state after the precharge operation. WE signals and is latched at the positive edges of CK. and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. CK The I/Os are byte-maskable during Writes.
Alliance Memory, lnc. Confidential 5 Rev. 1.1 Sep. /2011 VDD Supply Power Supply: 2.5V ± 0.2V . VSS Supply Ground VDDQ Supply DQ Power: 2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - No Connect: These pins should be left unconnected.
shows the truth table for the operation commands. Table 3. Truth Table (Note (1), (2))
- CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
- These are states of bank designated by BA signal.
- Device state is 2, 4, and 8 burst operation.
- LDM and UDM can be enabled respectively.
default value of the Mode Register is not defined; therefo re the Mode Register must be written by the user. Table 4. Mode Register Bitmap
0 MRS 1 0 1 Reserved 1 0 1 Reserved
Table 5. Burst Length
Mode and Interleave Mode support burst length of 2, 4 and 8. Table 6. Addressing Mode
0 Sequential
1 Interleave
Table 7. Burst Address ordering
2 X X 0 0, 1 0, 1
This field specifies the number of clock cycles from the assertion of the Read command to the first read data. Table 8. CAS Latency
These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 9. Test Mode Table 10. MRS/EMRS
Table 11. Extended Mode Register Bitmap
0 MRS 0 0 Full 0 Enable
1 EMRS 0 1 Weak 1 Disable
Table 12. Absolute Maximum Rating Table 13. Recommended D.C. Operating Conditions (TA = -40 ~ 85 C) Note: All voltages are referenced to VSS. Table 14. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 C)
Parameter & Test Condition Symbol -5 Unit Note Max. changing once every two clock cycles.
Table 16. Electrical Characteristics and Recommended A.C.Operating Condition Symbol Parameter -5 Unit Note Min. Max.
1) Enables on-chip refresh and address counters. LOW at this time, depending on tDQSS. this parameter, but system performance (bus turnaround) will degrade accordingly. 7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. Table 18. SSTL _2 Interface
Figure 3. SSTL_2 A.C. Test Load Power up must be performed in the following sequence. "NOP" state and maintain CKE “LOW”. 2) Start clock and maintain stable condition for minimum 200s. 4) Issue a “Precharge All” command. 6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register.
Figure 4. Activating a Specific Row in a Specific Bank
Figure 7. Read Burst Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 19 Rev. 1.1 Sep. /2011 Read Burst Required CAS Latencies (CL=3) DO n CK CK COMMAND READ NOP NOP NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 21 Rev. 1.1 Sep. /2011 Consecutive Read Bursts Required CAS Latencies (CL=2.5) DO o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n
Alliance Memory, lnc. Confidential 22 Rev. 1.1 Sep. /2011 Consecutive Read Bursts Required CAS Latencies (CL=3) DO o CK CK COMMAND READ NOP READ NOP NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device DO n
Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 24 Rev. 1.1 Sep. /2011 Non-Consecutive Read Bursts Required CAS Latencies (CL=2.5) CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO n DO o
Alliance Memory, lnc. Confidential 25 Rev. 1.1 Sep. /2011 Non-Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND READ NOP NOP READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o NOP DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) DO o DO n
Figure 10. Random Read Accesses Required CAS Latencies (CL=2) DO n, etc. =Data Out from column n, etc.
Alliance Memory, lnc. Confidential 27 Rev. 1.1 Sep. /2011 Random Read Accesses Required CAS Latencies (CL=2.5) DO p DO DO o DO DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n' , etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n
Alliance Memory, lnc. Confidential 28 Rev. 1.1 Sep. /2011 Random Read Accesses Required CAS Latencies (CL=3) DO p DO DO o DO CK CK COMMAND READ READ READ READ NOP NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o Bank, Col p Bank, Col q DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks DO n
Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 30 Rev. 1.1 Sep. /2011 Terminating a Read Burst Required CAS Latencies (CL=2.5) CK CK COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=2.5 Don’t Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n
Alliance Memory, lnc. Confidential 31 Rev. 1.1 Sep. /2011 Terminating a Read Burst Required CAS Latencies (CL=3) CK CK COMMAND READ NOP BST NOP NOP NOP Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DO n
Figure 12. Read to Write Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 33 Rev. 1.1 Sep. /2011 Read to Write Required CAS Latencies (CL=2.5) CK CK COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=2.5 Don’t Care min tDQSS DI o DM Bank, Col o DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n
Alliance Memory, lnc. Confidential 34 Rev. 1.1 Sep. /2011 Read to Write Required CAS Latencies (CL=3) CK CK COMMAND READ BST NOP NOP WRITE NOP Bank, Col nADDRESS DQS DQ CL=3 Don’t Care Bank, Col o min tDQSS DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order DO n
Figure 13. Read to Precharge Required CAS Latencies (CL=2)
Alliance Memory, lnc. Confidential 36 Rev. 1.1 Sep. /2011 Read to Precharge Required CAS Latencies (CL=2.5) CK CK COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=2.5 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n
Alliance Memory, lnc. Confidential 37 Rev. 1.1 Sep. /2011 Read to Precharge Required CAS Latencies (CL=3) CK CK COMMAND READ NOP PRE NOP NOP ACT Bank A, Col nADDRESS DQS DQ CL=3 Don’t Care Bank (a or all) Bank A, Row tRP DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met DO n
Figure 14. Write Command
Figure 15. Write Max DQSS
Figure 16. Write Min DQSS
Figure 17. Write Burst Nom, Min, and Max tDQSS
Figure 18. Write to Write Max tDQSS DI n , etc. = Data In for column n,etc.
Figure 19. Write to Write Max tDQSS, Non Consecutive DI n, etc. = Data In for column n, etc.
Figure 20. Random Write Cycles Max tDQSS DI n, etc. = Data In for column n, etc.
Figure 21. Write to Read Max tDQSS Non Interrupting DI n, etc. = Data In for column n, etc.
Figure 22. Write to Read Max tDQSS Interrupting DI n, etc. = Data In for column n, etc.
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
Figure 25. Write to Precharge Max tDQSS, Interrupting
Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting
Figure 27. Precharge Command
Figure 28. Power-Down Figure 29. Clock Frequency Change in Precharge
200 Clocks
Figure 32. Initialize and Mode Register Sets *=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
Figure 33. Power Down Mode then the Power-Down mode shown is active Power Down.
Figure 34. Auto Refresh Mode
Figure 35. Self Refresh Mode required before a READ command can be applied.
Figure 36. Read without Auto Precharge
Figure 37. Read with Auto Precharge
Figure 38. Bank Read Access
Figure 39. Write without Auto Precharge
Figure 40. Write with Auto Precharge
Figure 41. Bank Write Access
Figure 42. Write DM Operation
Figure 43. 66 Pin TSOP II Package Outline Drawing Information
Figure 44. BGA 60ball package Outline Drawing Information
Alliance Memory, lnc. Confidential 67 Rev. 1.1 Sep. /2011