AS4C128M16D3L-12BIN

2GB-DDR3L-AS4C128M16D3L ALSC | Alldatasheet

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Technical content

2Gb DDR3L – AS4C128M16D3L Confidential 1 Rev. 2.0 Aug. /2014

Revision History

AS4C128M16D3L - 96-ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet April 2014 Rev 2.0 Added "Backward compatible to VDD & VDDQ = 1.5V +/- 0.075V" - page 2 August 2014 Updated Table 12. Recommended DC Operating Conditions – page 21 Added CL=5 & CL=6 to Table 18 – page 26

2Gb DDR3L – AS4C128M16D3L Confidential 2 Rev. 2.0 Aug. /2014 128M x 16 bit DDR3L Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, Aug. /2014)

Features

 JEDEC Standard Compliant  Power supplies: VDD & VDDQ = 1.35V  Backward compatible to VDD & VDDQ = 1.5V ±0.075V  Operating temperature: - Commercial (0 ~ 95°C) - Industrial (-40 ~ 95°C)  Supports JEDEC clock jitter specification  Fully synchronous operation  Fast clock rate: 800MHz  Differential Clock, CK & CK#  Bidirectional differential data strobe - DQS & DQS#  8 internal banks for concurrent operation  8n-bit prefetch architecture  Internal pipeline architecture  Precharge & active power down  Programmable Mode & Extended Mode registers  Additive Latency (AL): 0, CL-1, CL-2  Programmable Burst lengths: 4, 8  Burst type: Sequential / Interleave  Output Driver Impedance Control  8192 refresh cycles / 64ms - Average refresh period  Write Leveling  OCD Calibration  Dynamic ODT (Rtt_Nom & Rtt_WR)  RoHS compliant  Auto Refresh and Self Refresh  96-ball 9 x 13 x 1.2mm FBGA package - Pb and Halogen Free Overview The 2Gb Double -Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve hig h-speed operation. It is internally configured as an eight bank DRAM. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double -data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK ri sing and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1. 35V -0.067V /+0.1V power supply and are available in BGA packages. Table 1. Speed Grade Information Table 2. Ordering Information

Figure 1. Ball Assignment (FBGA Top View)

Figure 2. Block Diagram

Figure 3. State Diagram

Table 3. Ball Descriptions (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). and the state of output and burst address is froze n as long as the CKE remains LOW. Down and Self Refresh modes. BankPrecharge command is being applied. Autoprecharge should be performed to the accessed bank after the Read/Write operation. burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). the idle state after the precharge operation. command is selected by asserting WE# “HIGH " or “LOW". command and Read or Write command. is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.

2Gb DDR3L – AS4C128M16D3L Confidential 7 Rev. 2.0 Aug. /2014 LDM, UDM Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. DQ0 - DQ15 Input / Output Data I/O: The data bus input and output data are synchronized with positive and negative edges of DQS/DQS#. The I/Os are byte-maskable during Writes. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#. The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. RESET# Input Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD VDD Supply Power Supply: +1.35V -0.067V/+0.1V VSS Supply Ground VDDQ Supply DQ Power: +1.35V -0.067V/+0.1V VSSQ Supply DQ Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. NC - No Connect: These pins should be left unconnected.

Table 4. Truth Table (Note (1), (2)) NOTE 2: CKEn signal is input level when commands are provided. NOTE 3: CKEn-1 signal is input level one clock cycle before the commands are provided. NOTE 4: These are states of bank designated by BA signal. NOTE 5: Device state is 4, and 8 burst operation. NOTE 6: LDM and UDM can be enabled respectively.

internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. descriptions and device operation. Figure 4. Reset and Initialization Sequence at Power-on Ramping NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands.

2Gb DDR3L – AS4C128M16D3L Confidential 10 Rev. 2.0 Aug. /2014  Power-up and Initialization The Following sequence is required for POWER UP and Initialization 1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). RESET# needs t o be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before RESET# being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts. - VDD and VDDQ are driven from a single power converter output, AND - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND - Vref tracks VDDQ/2. OR - Apply VDD without any slope reversal before or at the same time as VDDQ. - Apply VDDQ without any slope reversal before or at the same time as VTT & Vref. - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After RESET# is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clock (CK, CK#) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3L DRAM will keep its on-die termination in high impedance state as long as RESET# is asserted. Further, the DRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load mode register.(tXPR=max (tXS, 5tCK)) 6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to BA0 and BA2, “High” to BA1) 7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to BA2, “High” to BA0 and BA1) 8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2) 9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command provide “High” to A8 and “Low” to BA0-BA2) 10. Issue ZQCL command to starting ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3L SDRAM is now ready for normal operation.

The following sequence is required for RESET at no power interruption initialization.

1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3L SDRAM is ready for normal operation.

Figure 5. Reset Procedure at Power Stable Condition NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands.

up without affecting the array contents. register and is the minimum time required between two MRS commands shown in Figure of tMRD timing. Figure 6. tMRD timing and DES shown in Figure of tMOD timing.

Figure 7. tMOD timing various fields depending on the functionality and/or modes.

address pins according to the following figure. Table 5. Mode Register Bitmap

0 Slow exit (DLL off)

1 Yes

Note 1: Reserved for future use and must be set to 0 when programming the MR.

Table 6. Burst Type and Burst Order

8 Read

Note 2: 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst. Note 3: T: Output driver for data and strobes are in high impedance. Note 4: V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. delay, in clock cycles, between the internal Read command and the availability of the first bit of output data. Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. used by the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

must be programmed to be equal or larger than tWR (min). according to the following figure. Table 7. Extended Mode Register EMR (1) Bitmap

1 Output buffer disabled 0 0 0 Rtt_Nom disabled

0 Disabled 0 1 1 RZQ/6

1 Enabled 1 0 0 RZQ/12 *4

Note 1: Reserved for future use and must be set to 0 when programming the MR. Note 2: Outputs disabled - DQs, DQSs, DQS#s. Note 4: If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.

2Gb DDR3L – AS4C128M16D3L Confidential 17 Rev. 2.0 Aug. /2014 - DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. During normal operation (DLL -on) with MR1 (A0=0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically re -enable upon exit of Self -Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 L SDRAM does not require DLL for any Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation are described in DLL-off Mode. The direct ODT feature is not supported during DLL-off mode. The on -die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at DLL -off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0, 0}, to disable Dynamic ODT externally - Output Driver Impedance Control The output driver impedance of the DDR3 L SDRAM device is selected by MR1 (bit A1 and A5 ) as shown in MR1 definition figure. - ODT Rtt Values DDR3L SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. - Additive Latency (AL) Additive Latency (AL) operation is supported to make command and data bus efficient f or sustainable bandwidth in DDR3L SDRAM. In this operation, the DDR3 L SDRAM allows a read or write command (either with or without auto-precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency ( AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of th e AL register options are shown in MR. - Write leveling For better signal integrity, DDR3 L memory module adopted fly -by topology for the commands, addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’ in DDR3L SDRAM to compensate for skew. - Output Disable The DDR3L SDRAM outputs maybe enable/disabled by MR1 (bit 12) as shown in MR1 definition. When this feature is enabled (A12=1) all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device removi ng any loading of the output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should be set to ‘0’.

on BA0 and BA2, while controlling the states of address pins according to the table below. Table 8. Extended Mode Register EMR (2) Bitmap Note 1: BA2 and A8, A11~ A13 are RFU and must be programmed to 0 during MRS. Note 2: The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.

2Gb DDR3L – AS4C128M16D3L Confidential 19 Rev. 2.0 Aug. /2014 - Partial Array Self-Refresh (PASR) Optional in DDR3 L SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3L SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. - CAS Write Latency (CWL) The CAS Write Latency is defined by MR2 (bits A3 -A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 L DRAM does not support any half clock latencie s. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL. For more information on the supported CWL and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. For detailed Write operation refer to “WRITE Operation”. - Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) DDR3L SDRAM must support Self -Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Ra nge must use the ASR function or program the SRT bit appropriately. Optional in DDR3 L SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3L SDRAM devices support the following options or requirements referred to in this material. For more details refer to “Extended Temperature Usage”. DDR3 L SDRAMs must support Self -Refresh operation at all supported temperatures. Applications requiring Self -Refresh operation in the Extended Temperature Range must use the optional ASR function or program the SRT bit appropriately. - Dynamic ODT (Rtt_WR) DDR3L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination str ength of the DDR3 L SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. DDR3L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 L SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available . For details on Dynamic ODT operation, refer to “Dynamic ODT”.

Table 9. Extended Mode Register EMR (3) Bitmap Note 1: BA2, A3 - A13 are RFU and must be programmed to 0 during MRS. Note 2: The predefined pattern will be used for read synchronization. Note 3: When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.

Table 10. Absolute Maximum DC Ratings rating conditions for extended periods may affect reliability. NOTE2: Storage Temperature is the case surface temperature on the center/top side of the DRAM. when VDD and VDDQ are less than 500mV; Vref may be equal to or less than 300mV. Table 11. Temperature Range NOTE1: Operating temperature is the case surface temperat ure on center/top of the DRAM. NOTE2: The operating temperature range is the temperature where all DRAM specification will be supported. case temperature. Full specifications are guaranteed in this range, but the following additional apply. also possible to specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range. the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0). -40°C~95°C under all operating Conditions. Table 12. Recommended DC Operating Conditions

1. Under all conditions VDDQ must be less than or equal to VDD
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD & VDDQ rating are determined by operation voltage.

Table 13. Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter -12 Unit Note Min. Max. NOTE 1: For input only pins except RESET#. Vref = VrefCA(DC). NOTE 2: See “Overshoot and Undershoot Specifications”. NOTE 3: The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/ -1% VDD. NOTE 4: For reference: approx. VDD/2 +/- 13.5 mV. when Vref + 0.160V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced. when Vref - 0.160V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced. Table 14. Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter -12 Unit Note Min. Max. NOTE 2: See “Overshoot and Undershoot Specifications”. NOTE 3: The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD. NOTE 4: For reference: approx. VDD/2 +/- 13.5 mV.

Table 15. Differential AC and DC Input Levels Symbol Parameter -12 Unit Note Min. Max. NOTE 1: Used to define a differential signal slew-rate. Table 16. Capacitance (VDD = 1.35V, f = 1MHz, TOPER = 25 C) Symbol Parameter -12 Unit Note Min. Max. NOTE 1: Although the DM pins have different functions, the loading matches DQ and DQS . VBIAS=VDD/2 and on die termination off. NOTE 3: This parameter applies to monolithic devices only; stacked/dual -die devices are not covered here. NOTE 4: Absolute value of CCK-CCK#. NOTE 5: Absolute value of CIO(DQS)-CIO(DQS#). NOTE 6: CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#, CAS#, WE#. NOTE 7: CDI_CTRL applies to ODT, CS# and CKE. NOTE 8: CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#)). NOTE 9: CDI_ADD_CMD applies to A0-A12, BA0-BA2, RAS#, CAS# and WE#. NOTE 10: CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#)). NOTE 11: CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)). NOTE 12: Maximum external load capacitance on ZQ pin: 5 pF.

Table 17. IDD specification parameters and test conditions (VDD = 1.35V) Parameter & Test Condition Symbol -12 Unit Max. Enabled in Mode Registers*2; ODT Signal: stable at 0. Mode Registers*2; ODT Signal: stable at 0. Enabled in Mode Registers*2; ODT Signal: stable at 0. Registers*2; ODT Signal: stable at HIGH.

2Gb DDR3L – AS4C128M16D3L Confidential 25 Rev. 2.0 Aug. /2014 Burst Refresh Current CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between tREF; Command, Address, Bank Address Inputs: partially toggling; Data IO: MID- LEVEL;DM:stable at 0; Bank Activity: REF command every tRFC; Output Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: stable at 0. IDD5B 135 mA Self Refresh Current: Auto Self-Refresh (ASR): Disabled*4; Self-Refresh Temperature Range (SRT): Normal*5; CKE: Low; External clock: Off; CK and CK#: LOW; BL: 8*1; AL: 0; CS#, Command, Address, Bank Address, Data IO: MID- LEVEL;DM:stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: MID-LEVEL TCASE: 0 - 85°C IDD6 11 mA TCASE: -40 - 95°C IDD6ET 14 mA Operating Bank Interleave Read Current: CKE: High; External clock: On; BL: 8*1, 7; AL: CL-1; CS#: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; DM:stable at 0; Output Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: stable at 0. IDD7 210 mA RESET Low Current: RESET: Low; External clock: Off; CK and CK# : Low ; CKE : Floating ; CS, Command, Address, Bank Address, Data IO : Floating ; ODT Signal : Floating IDD8 13 mA NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B NOTE 3. Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3L SDRAM device NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions Symbol Parameter -12 Unit Min. Max.

2Gb DDR3L – AS4C128M16D3L Confidential 27 Rev. 2.0 Aug. /2014 tWTR Delay from start of internal write transaction to internal read command max (4nCK, 7.5ns) tWR WRITE recovery time 15 - ns tMRD Mode Register Set command cycle time 4 - tCK tMOD Mode Register Set command update delay max (12nCK, 15ns) tCCD CAS# to CAS# command delay 4 - tCK tDAL(min) Auto precharge write recovery + prechargetime WR + tRP tCK tMPRR Multi-Purpose Register Recovery Time 1 - tCK tRRD ACTIVE to ACTIVE command period max (4nCK, 7.5ns) tFAW Four activate window 40 - ns tIS(base) Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels AC160 60 - ps AC135 185 - ps tIH(base) Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels DC90 130 - ps tIPW Control and Address Input pulse width for each input 560 - - tZQinit Power-up and RESET calibration time 512 - tCK tZQoper Normal operation Full calibration time 256 - tCK tZQCS Normal operation Short calibration time 64 - tCK tXPR Exit Reset from CKE HIGH to a valid command max(5nCK, tRFC+10ns) tXS Exit Self Refresh to commands not requiring a locked DLL max(5nCK, tRFC+10ns) tXSDLL Exit Self Refresh to commands requiring a locked DLL tDLLK(min) - tCK tCKESR Minimum CKE low width for Self Refresh entry to exit timing tCKE(min) +1nCK tCKSRE Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) max (5nCK, 10 ns) tCKSRX Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit max (5nCK, 10 ns) tXP Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL max (3nCK, 6 ns) tXPDLL Exit Precharge Power Down with DLL frozen to commands requiring a lockedDLL max (10nCK, 24 ns) tCKE CKE minimum pulse width max (3nCK, 5ns) tCPDED Command pass disable delay 1 - tCK tPD Power Down Entry to Exit Timing tCKE(min) 9 * tREFI tACTPDEN Timing of ACT command to Power Down entry 1 - tCK tPRPDEN Timing of PRE or PREA command to Power Down entry 1 - tCK tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 - tCK tWRPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 +(tWR / tCK) - tCK

2Gb DDR3L – AS4C128M16D3L Confidential 28 Rev. 2.0 Aug. /2014 tWRAPDEN Timing of WRA command to Power Down entry (BL8OTF, BL8MRS,BC4OTF) WL + 4 +WR + 1 - tCK tWRPDEN Timing of WR command to Power Down entry (BC4MRS) WL + 2 +(tWR / tCK) - tCK tWRAPDEN Timing of WRA command to Power Down entry (BC4MRS) WL + 2 +WR + 1 - tCK tREFPDEN Timing of REF command to Power Down entry 1 - tCK tMRSPDEN Timing of MRS command to Power Down entry tMOD(min) - ODTLon ODT turn on Latency WL - 2 = CWL + AL - 2 tCK ODTLoff ODT turn off Latency WL - 2 = CWL + AL - 2 ODTH4 ODT high time without write command or with write command and BC4 4 - tCK ODTH8 ODT high time with Write command and BL8 6 - tCK tAONPD Asynchronous RTT turn-on delay (Power- Down with DLL frozen) 2 8.5 ns tAOFPD Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 2 8.5 ns tAON RTT turn-on -225 225 ps tAOF RTT_Nom and RTT_WR turn-off time from ODTLoff reference 0.3 0.7 tCK tADC RTT dynamic change skew 0.3 0.7 tCK tWLMRD First DQS/DQS# rising edge after write leveling mode is programmed 40 - tCK tWLDQSEN DQS/DQS# delay after write leveling mode is programmed 25 - tCK tWLS Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing 165 - ps tWLH Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing 165 - ps tWLO Write leveling output delay 0 7.5 ns tWLOE Write leveling output error 0 2 ns tRFC REF command to ACT or REF command time 160 - ns tREFI Average periodic refresh interval -40°C to 85°C - 7.8 μs 85°C to 95°C - 3.9 μs

Figure 8. MPR Block Diagram To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1 . Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). RDA has the same functionality as a READ command which means the auto precharge part of RDA is ignored. mode. The RESET function is supported during MPR enable mode. Table 19. MPR MR3 Register Definition Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Write will go to DRAM array.

• One bit wide logical interface via all DQ pins during READ operation.
• Register Read on x16:
• DQL[0] and DQU[0] drive information from MPR.
• DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
• Addressing during for Multi Purpose Register reads for all MPR agents:
• BA [2:0]: don’t care
• A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
• A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *)
• A[9:3]: don’t care
• A10/AP: don’t care
• A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
• A11, A13, ... (if available): don’t care
• Regular interface functionality during register reads:
• Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
• Support of read burst chop (MRS and on-the-fly via A12/BC)
• All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3L SDRAM.
• Regular read latencies and AC timings apply.
• DLL must be locked prior to MPR Reads. NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

Table 20. MPR MR3 Register Definition states. Operations already in progress are not affected. DDR3L SDRAM is effectively deselected. Operations already in progress are not affected.

until A0 bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later. need to satisfy the refresh interval, tREFI. Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode. Figure 9. DLL-off mode READ Timing Operation both timings in the same way and the skew between all DQ and DQS, DQS# signals will still be tDQSQ.

until A0 bit set back to “0”.

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors,

RTT, must be in high impedance state before MRS to MR1 to disable the DLL).

1. Set MR1 Bit A0 to “1” to disable the DLL.
2. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
3. Change frequency, in guidance with “Input Clock Frequency Change” section.
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD

when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH.

1. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR

may be necessary. A ZQCL command may also be issued after tXS).

1. Wait for tMOD, and then DRAM is ready for next command.

Figure 10. DLL Switch Sequence from DLL-on to DLL-off

1. Starting with Idle State, RTT in Hi-Z state
2. Disable DLL by setting MR1 Bit A0 to 1
3. Clock must be stable tCKSRX
4. Update Mode registers with DLL off parameters setting

1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors

(RTT) must be in high impedance state before Self-Refresh mode is entered).

1. Enter Self Refresh Mode, wait until tCKSRE satisfied.
2. Change frequency, in guidance with “Input clock frequency change” section.
3. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
4. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing

mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH.

1. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
2. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
3. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may

issued during or after tDLLK).

1. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before

Figure 11. DLL Switch Sequence from DLL-off to DLL on

1. Clock must be stable tCKSRX
2. Start DLL Reset by MR0 A8=1

registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min. parameters should be met whether clock jitter is present or not. these parameters should be met whether clock jitter is present or not. edge to its respective data strobe signal (DQS(L/U), DQS(L/U)#) crossing. tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. Table 21. Input clock jitter spec parameter

spectrum clocking) specification. illegal to change the clock frequency. minimum and maximum operating frequency specified for the particular speed grade. may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. DRAM is ready to operate with new clock frequency. Figure 12. Change Frequency during Precharge Power-down

2Gb DDR3L – AS4C128M16D3L Confidential 36 Rev. 2.0 Aug. /2014 CK# T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0T0 ADDRESS CK Te1 COMMAND ODT NOPNOP NOP NOP NOP MRS NOP VALID DLL RESET High-Z High-z DQS# DQS DQ DM NOTES 1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down. 2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1;refer to ODT timing section for exact requirements 3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 13. If the RTT_NOM feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. tCH tCL tCK tCKSRE tCHb tCLb tCKb tCHb tCLb tCKb tCHb tCLb tCKb tCKSRX tCKE CKE tIH tIS VALID tXP Enter PRECHARGE Power-Down Mode tCPDED PREVIOUS CLOCK FREQUENCY NEW CLOCK FREQUENCY tAOFPD / tAOF Frequency Change Exit PRECHARGE Power-Down Mode tDLLK Don't Care Indicates a break in time scale tIH tIS tIH tIS

leveling” in DDR3L SDRAM to compensate the skew. delay setting on DQS – DQS# to align the rising edge of DQS – DQS# with that of the clock at the DRAM pin. delay established though this exercise would ensure tDQSS specification. the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS - DQS# signals. populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X16. Figure 13. Write Leveling Concept

activated and deactivated via ODT pin not like normal operation. Table 22. DRAM termination function in the leveling mode settings of RZQ/2, RZQ/4, and RZQ/6 are allowed. tMOD, time at which DRAM is ready to accept the ODT signal. is used by the DRAM to sample CK – CK# driven from controller. tWLMRD(max) timing is controller dependent. delay setting and write leveling is achieved for the device. Figure 14. Timing details of Write Leveling sequence

1. MRS: Load MR1 to enter write leveling mode.
2. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,

and maintained at this state through out the leveling procedure.

1. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
2. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.

1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after

Figure 15. Timing details of Write Leveling exit

1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
2. Auto Self-refresh supported
3. Extended Temperature Range supported
4. Double refresh required for operation in the Extended Temperature Range (applies only for devices

please refer to IDD table for details. Table 23. Self-Refresh mode summary refer to the IDD table for details. Range).Self-Refresh power consumption is temperature dependent. command must be issued before opening a different row in the same bank. The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. the precharge period will be determined by the last PRECHARGE command issued to the bank.

Read timing is shown in the following figure and is applied when the DLL is enabled and locked. invalid transition of the associated DQ pins. associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined. Figure 18. READ timing Definition

tQSL describes the data strobe low pulse width. Figure 19. Clock to Data Strobe relationship

1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe

edge can vary between tDQSCK(min) and tDQSCK(max).

1. Notwithstanding note 1, a rising strobe edge with tDQSCK(max) at T(n) can not be immediately followed by a rising strobe edge
2. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by tQSL.
3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are

not tied to tDQSCKmax (late strobe case).

1. The minimum pulse width of read preamble is defined by tRPRE(min).
2. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
3. The minimum pulse width of read postamble is defined by tRPST(min).
4. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.

• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.

Figure 20. Data Strobe to Data Relationship

1. DOUT n = data-out from column n.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
4. Output timings are referenced to VDDQ/2, and DLL on for locking.
5. tDQSQ defines the skew between DQS,DQS# to Data and does not define DQS,DQS# to Clock.
6. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst.

2Gb DDR3L – AS4C128M16D3L Confidential 45 Rev. 2.0 Aug. /2014 Write Operation  DDR3L Burst Operation During a READ or WRITE command, DDR3L will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (Auto Precharge can be enabled or disabled). A12=0, BC4 (BC4 = Burst Chop, tCCD=4) A12=1, BL8 A12 is used only for burst length control, not as a column address.  WRITE Timing Violations Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up” and errors be limited to that particular operation. For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned below.  Data Setup and Hold Violations Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly otherwise.  Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise.  Write Timing Parameters This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge ).  Refresh Command The Refre sh command (REF) is used during normal operation of the DDR3 L SDRAMs. This command is not persistent, so it must be issued each time a refresh is required. The DDR3 L SDRAM requires Refresh cycles at an average periodic interval of tREFI. When CS#, RAS#, and CAS# are held Low and WE# High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command can be applied. The refresh addres sing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the refresh cycle. No control of the external address bus is required once thi s cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min). In general, a Refresh command needs to be issued to the DDR3 L SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is pr ovided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3 L SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be executed.

2Gb DDR3L – AS4C128M16D3L Confidential 46 Rev. 2.0 Aug. /2014  Self-Refresh Operation The Self-Refresh command can be u sed to retain data in the DDR3 L SDRAM, even if the reset of the system is powered down. When in t he Self-Refresh mode, the DDR3L SDRAM retains data without external clocking. The DDR3L SDRAM device has a built -in timer to accommodate Self -Refresh operation. The Self -Refresh Entry (SRE) Command is defined by having CS#, RAS#, CAS#, and CKE held low with WE# high at the rising edge of the clock. Before issuing the Self -Refreshing-Entry command, the DDR3 L SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self -Refresh-Entry command, by either registerin g ODT pin low “ODTL + 0.5tCK” prior to the Self -Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal operation (DLL on), MR1 (A0=0) , the DLL is automatically disabled upon entering Self-Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh. When the DDR3 L SDRAM has entered Self -Refresh mode, all of the external control signals, except CKE and RESET#, are “don’t care”. For proper Self -Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters Self-Refresh mode. The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3L SDRAM must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-Refresh mode. The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements [TBD] must be satisfied. Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration commands, applicable timing requirements must be satisfied. CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self- Refresh re-entry. Upon exit from Self-Refresh, the DDR3L SDRAM can be put back into Self-Refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3L SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh mode.

Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, CKE, and RESET# . in deactivation of command and address receivers after tCPDED has expired. Table 24. Power-Down Entry Definitions (A Bank or more open) Don't Care On Fast tXP to any valid command. operate, such as RD, RDA or ODT control line. (All Banks Precharged) 1 On Fast tXP to any valid command. PD mode and into reset state). at AC spec table of this datasheet.

The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown as below. Figure 21. Functional representation of ODT the Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode. RTT is determined by the settings of those bits. Application: Controller sends WR command together with ODT asserted. One possible application: The rank that is being written to provides termination. DRAM does not use any write or read command decode information. Table 25. Termination Truth Table

0 OFF

1 On, (Off, if disabled by MR1 (A2, A6, A9) and MR2 (A9, A10) in general)

via a mode register set command during DLL-off mode. latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL-2. refer to DDR3L SDRAM latency definitions. Table 26. ODT Latency resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off th e ODT resistance. impedance. Both are measured from ODTLoff. registration of a write command until ODT is registered low. before the Read and enabled later after the Read than shown in this example.

Figure 22. ODT must be disabled externally during Reads by driving ODT low Two RTT values are available: RTT_Nom and RTT_WR.

• The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.
• The value for RTT_WR is preselected via bits A[10,9] in MR2.
• Nominal termination strength RTT_Nom is selected.
• Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
• A latency ODTLcnw after the write command, termination strength RTT_WR is selected.

selected OTF) after the write command, termination strength RTT_Nom is selected.

• Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.

MR2 [A10,A9 = [0,0], to disable Dynamic ODT externally. registration of Write command until ODT is register low.

Table 27. Latencies and timing parameters relevant for Dynamic ODT Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporar ily disabled (i.e. Precharge power down mode if DLL is disabled during precharge power down by MR0 bit A12. In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max. in time when the ODT resistance is fully on. tAONPDmin and tAONPDmax are measured from ODT being sampled high. Table 28. ODT timing parameters for Power Down (with DLL frozen) entry and exit

2Gb DDR3L – AS4C128M16D3L Confidential 52 Rev. 2.0 Aug. /2014  Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition period around power down entry, where the DDR3 L SDRAM may show either synchronous or asynchronous ODT behavior. The transition period is defined by the pa rameters tANPD and tCPDED(min). tANPD is equal to (WL -1) and is counted backwards in time from the cloc k cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED(min). If there is a Refresh comman d in progress while CKE goes low, then the transition period ends at the later one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period. ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and (ODTLon*tck+tAONmin) and as late as the larg er of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de - assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period.  Asynchronous to Synchronous ODT Mode transition during Power-Down Exit If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3L SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon* tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state chang e of ODT after the transition period with synchronous response.  Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap. In this case, the response of the DDR3 L SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period (even if the entry ends later than the exit period). If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may be synch ronous or asynchronous from the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered.

calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values. allowed a timing period of tZQoper. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. self-refresh exit, DDR3L SDRAM will not perform an IO cal ibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS. tZQinit, or tZQCS between ranks. Figure 23. ZQ Calibration Timing

1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.

on the ZQ pin must be limited.

with certain requirements for single-ended signals. following a valid transition. Table 29. Single-ended levels for CK, DQSL, DQSU, CK#, DQSL# or DQSU# Symbol Parameter -12 Unit Note Min. Max. NOTE 1: For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQSL, DQSL#, DQSU, DQSU#) use VIH/VIL(ac) of DQs. ac-high or ac-low level is used for a signal group, then the reduced level applies also here . complete signal to the midlevel between of VDD and VSS. Table 30. Cross point voltage for differential input signals (CK, DQS) Symbol Parameter -12 Unit Note Min. Max. NOTE 2: The relation between Vix Min/Max and VSEL/VSEH should satisfy following.

Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown below. Table 31. Differential Input Slew Rate Definition NOTE: The differential signal (i.e., CK, CK# and DQS, DQS#) must be linear between these thresholds. Table 32. Single-ended AC and DC Output Levels with a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2. Table 33. Differential AC and DC Output Levels

and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table. Table 34. Output Slew Rate Definition (Single-ended) NOTE: Output slew rate is verified by design and characterization, and may not be subject to production test. Table 35. Output Slew Rate (Single-ended) Symbol Parameter -12 Unit Min. Max. measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table. Table 36. Output Slew Rate Definition (Differential) NOTE: Output slew rate is verified by design and characterization, and may not be subject to production test . Table 37. Output Slew Rate (Differential) Symbol Parameter -12 Unit Min. Max.

parameters of the device as well as output slew rate measurements. more coaxial transmission lines terminated at the tester electronics. Figure 24. Reference Load for AC Timing and Output Slew Rate Table 38. AC Overshoot/Undershoot Specification for Address and Control Pins Table 39. AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask

tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS. tangent line to the actual signal from the ac level to dc level is used for derating value. valid input signal is still required to complete the transition and reach VIH/IL(ac). Table 40. ADD/CMD Setup and Hold Base - Values for 1V/ns Table 41. Derating values DDR3L-1600 tIS/tIH – (AC160)

Table 42. Derating values DDR3L-1600 tIS/tIH – (AC135)

tDS(base) an tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS. the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. These values are typically not subject to production test. They are verified by design and characterization. Table 43. Data Setup and Hold Base - Values for 1V/ns Table 44. Derating values for DDR3L-1600 tDS/tDH – (AC135)

Figure 25. MPR Readout of predefined pattern,BL8 fixed burst order, single readout

1. RD with BL8 either by MRS or OTF.
2. Memory Controller must drive 0 on A[2:0].

3 VALID 3

00 VALID 00

0 VALID 0

0 VALID 0A[13]

Figure 26. MPR Readout of predefined pattern,BL8 fixed burst order, back to back radout

1. RD with BL8 either by MRS or OTF.
2. Memory Controller must drive 0 on A[2:0].

Figure 27. MPR Readout of predefined pattern,BC4 lower nibble then upper nibble

1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].

Figure 28. MPR Readout of predefined pattern,BC4 upper nibble then lower nibble

1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].

Figure 40. Write Timing Definition and parameters

1. DIN n = data-in from column n.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
4. tDQSS must be met at each rising clock edge.

Figure 43. WRITE(BC4) to READ (BC4) operation

1. DIN n = data-in from column n.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0 and READ command at Tn.
4. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7.

Figure 44. WRITE(BC4) to Precharge Operation

1. DIN n = data-in from column n.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0.
4. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.

tWR specifies the last burst write cycle until the precharge command can be issued to the same bank . Figure 45. WRITE(BC4) OTF to Precharge operation

1. DIN n (or b) = data-in from column n.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 OTF setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
4. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).

4 Clocks tWR

Figure 46. WRITE(BC8) to WRITE(BC8)

1. DIN n (or b) = data-in from column n (or column b).
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0 and T4.
4. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.

4 Clocks

Figure 47. WRITE(BC4) to WRITE(BC4) OTF

1. DIN n (or b) = data-in from column n (or column b).
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0 and T4.
4. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge at T13 (4 clocks from T9).

Figure 48. WRITE(BC8) to READ(BC4,BC8) OTF

1. DIN n = data-in from column n; DOUT b = data-out from column b.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.

READ command at T13 can be either BC4 or BL8 depending on MR0[A1:0] and A12 status at T13.

Figure 49. WRITE(BC4) to READ(BC4,BC8) OTF

1. DIN n = data-in from column n; DOUT b = data-out from column b.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.

READ command at T13 can be either BC4 or BL8 depending on A12 status at T13. Figure 50. WRITE(BC4) to READ(BC4)

1. DIN n = data-in from column n; DOUT b = data-out from column b.
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 10].

Figure 51. WRITE(BC8) to WRITE(BC4) OTF

1. DIN n (or b) = data-in from column n (or column b).
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.

BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T4.

Figure 52. WRITE(BC4) to WRITE(BC8) OTF

1. DIN n (or b) = data-in from column n (or column b).
2. NOP commands are shown for ease of illustration; other commands may be valid at these times.
3. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.

BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T4. Figure 53. Refresh Command Timing

1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.

Figure 54. Self-Refresh Entry/Exit Timing

1. Valid commands not requiring a locked DLL.
2. Valid commands requiring a locked DLL.

Figure 77. 96-Ball BGA Package 9x13x1.2mm(max) Outline Drawing Information

2Gb DDR3L – AS4C128M16D3L Confidential 84 Rev. 2.0 Aug. /2014 Alliance Memory Inc. reserves the rights to change the specification s and products without notice. Alliance Memory, Inc., 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211