Memory

AS29F040-150T

Alliance Semiconductor ...

5V 512K x 8 CMOS FLASH EEPROM

Manufacturer: Alliance Semiconductor ...

Document: 18 Pages / 341Kb

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AS29F040 ALSC | Alldatasheet

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PDF pages: 18

Technical content

Organization:512K words × 8 bits
Industrial and commercial temperature
Sector architecture - Eight 64K byte sectors - Erase any combination of sectors or full chip
Single 5.0±0.5V power supply for read/write operations
Sector protection
High speed 55/70/90/120/150 ns address access time
Automated on-chip programming algorithm - Automatically programs/verifies data at specified address
Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors
10,000 write/erase cycle endurance
Low power consumption - 30 mA maximum read current - 60 mA maximum program current - 400 µA typical standby current
JEDEC standard software, packages and pinouts - 32-pin TSOP - 32-pin PLCC
Detection of program/erase cycle completion -D Q 7 D A T A polling - DQ6 toggle bit
Erase suspend/resume - Supports reading data from or programming data to a sector not being erased
Low VCC write lock-out below 2.8V /RJLF#EORFN#GLDJUDP X decoder VCC VSS Cell matr Y decoder Y gating Data latchChip enable Address latch Input/output buffers Sector protect Command register Program/erase control VCC detector Erase voltage generator Program voltage generator Timer A0–A18 CE OE STB STB Output enable Logic WE DQ0–DQ7switches 3LQ#DUUDQJHPHQW VCC WE A17 A14 A13 A11 OE A10 CE DQ7 DQ6 DQ5 A18 A16 A15 A12 A4 A3 DQ0 DQ1 DQ2 VSS DQ4 DQ3 32-pin TSOP 32-pin PLCC 123 2 3 1 3 043 DQ0 V SS DQ4 DQ6DQ1 1716 18 19 2014 15 DQ2 DQ3 DQ5 A14 A13 A11 OE A10 DQ7 CE A16 V CC A17A12 A15 A18 WE AS29F040 AS29F040 6HOHFWLRQ#JXLGH AS29F040-55 AS29F040-70 AS29F040-90 AS29F040-120 AS29F040-150 Unit Maximum access time t AA 55 70 90 120 150 ns Maximum chip enable access time t CE 55 70 90 120 150 ns Maximum output enable access time t OE 25 30 35 50 55 ns

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ )XQFWLRQDO#GHVFULSWLRQ The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an program capability , the 4 megabits of data is divided into eight 64K-byte sectors. The ×8 data appears on DQ0–DQ7. The AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an erased in-system with a single 5.0V V CC suppl y. The device can also be reprogrammed in standard EPROM programmers. The AS29F040 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high-speed microprocessors. To eliminate bus contention the device has separate chip enable (CE ), write enable (WE), and output enable (OE) controls The AS29F040 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register use standard microprocessor write timings. An internal state machine uses register contents to control the erase and programmin g circuitr y. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data operates from the device in the same manner as other Flash or EPROM devices. The program command sequence is used to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. The erase command sequence is used to invoke the automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other secto rs . A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operation s i n any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29F040 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into th e array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Eras e returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other se ctors. The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations during power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The device automatically resets to read mode after program and/or erase operations are completed. The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits the alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program and/or erase commands disabled when V CC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE , CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands. The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector sim ultaneously. Bytes are programme one at a time using the EPROM programming mechanism of hot electron injection.

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 2SHUDWLQJ#PRGHV L = Low (<VIL); H = High (>VIH); VID = 12.0 ± 0.5V; X = don’t car . 0RGH#GHILQLWLRQV Mode CE OE WE A0 A1 A6 A9 DQ0-DQ7 ID read MFR code L L H L L L V ID Code ID read device code L L H H L L V ID Code R e a d L L H A 0A 1A 6A 9D OUT S t a n d b y H XXXXXXH i g h Z Output disable L H H X X X X High Z Write L H L A0 A1 A6 A9 D IN Enable sector protect L V ID Pulse/L L H L V ID X Sector unprotect L V ID P u l s e / L L HHV ID X Verify sector protect L L H L H L V ID Code Item Description ID MFR code, device code Selected by A9 = VID(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29F040. Read mode Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low . Standby Selected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input levels and <100 µA for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation before entering standb y. Output disable Part remains powered up; but outputs disabled with OE pulled high. Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Enable sector protect Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. Sector unprotect Disables sector protection for all sectors using external programming equipment. All sectors must be protected prior to sector unprotection. Ver if y sector protect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A16–18 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ 6HFWRU#DUFKLWHFWXUH#DQG#DGGUHVV#WDEOH 5($'#FRGHV L = Low (<VIL); H = High (>VIH); X = Don’t care. &RPPDQG#IRUPDW 1 Bus operations defined in "Mode definitions," on page 3. 2 Reading from or programming to non-erasing sectors allowed in Erase Suspend mode. 3 Address bit A15 = X = Don’t care for all address commands except Program Address. 4 Address bit A16 = X = Don’t care for all address commands except Program Address and Sector Address. 5 Address bit A17 = X = Don’t care for all address commands except Program Address and Sector Address. 6 Address bit A18 = X = Don’t care for all address commands except Program Address and Sector Address. Sector Equal sector architecture ID sector address Addresses Size (Kbytes) A18 A17 A16 0 00000h–0FFFFh 64 0 0 0 1 10000h–1FFFFh 64 0 0 1 2 20000h–2FFFFh 64 0 1 0 3 30000h–3FFFFh 64 0 1 1 4 40000h–4FFFFh 64 1 0 0 5 50000h–5FFFFh 64 1 0 1 6 60000h–6FFFFh 64 1 1 0 7 70000h–7FFFFh 64 1 1 1 Mode A18–A16 A9 A8–A7 A6 A5–A2 A1 A0 Code on DQ0–DQ7 MFG code (Alliance Semiconductor) XV ID XLX LL5 2 h Device code X V ID XLX LH A 4 h Sector protection Sector address VID Sector address L Sector address HL 01h protected 00h unprotected Command sequence Required bus cycles 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus read/write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Reset/read 1 XXXXh F0h Read Address Read Data Reset/read 4 5555h AAh 2AAAh 55h 5555h F0h Read Address Read Data Autoselect ID read 4 5555h AAh 2AAAh 55h 5555h 90h 00h MFR code 52h 01h Device code A4h XXX02h Sector protection 01 = protected 00 = unprotected Program 4 5555h AAh 2AAAh 55h 5555h A0h Program Address Program Data Chip erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h Sector erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h Sector Address 30h Sector erase suspend 1 XXXXh B0h Sector erase resume 1 XXXXh 30h

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 &RPPDQG#GHILQLWLRQV Item Description Reset/read Initiate read or reset operations by writing the read/reset command sequence into the command register. This allows the microprocessor to retrieve data from the memor y. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. ID read AS29F040 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read the device code with only +5V , since multiplexing +12V on address lines is generally undesirable. Initiate device ID read by writing the ID read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFG code. Follow ID read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A16 produc e a1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Byte/word programming Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two unlock write cycles precede the program setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessar y. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29F040’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to complete the programming operation. The AS29F040 ignores commands written during the programming operation. AS29F040 allows programming in any sequence, across any sector boun dary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset command returns the device to read mode. Chip erase Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip erase command. Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip erase command sequence, AS29F040 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F040 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ Sector erase Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the sector erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE ; the command, 30h, is latched on the rising edge of WE. The sector erase operation begins after a 80 µs time-out. To erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be <80 µs, or the AS29F040 ignores the command and erasure begins. During the erase time-out period any falling edge of WE resets the time-out. Any command (other than sector erase or erase suspend) during the time-out period resets the AS29F040 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the sector erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29F040 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29F040 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling must be performed on addresses that fall within the sectors being erased. AS29F040 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. Erase suspend Erase suspend allows interruption of sector erase operations to perform data reads from or writes to a sector not being erased. Erase suspend applies only during sector erase operations, including the time- out period. Writing an erase suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29F040 ignores any commands during erase suspend other than read/reset, program, or erase resume commands. Writing the Erase Resume command continues erase operations. Addresses are DON’T CARE when writing Erase suspend or Erase resume commands. AS29F040 takes 0.2–15 µs to suspend erase operations after receiving erase suspend command. To determine completion of erase suspend, check DQ6 after selecting an address of a sector not being erased. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F040 ignores redundant writes of erase suspend. While in erase-suspend mode AS29F040 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase, treated as standard read or standard programming mode. AS29F040 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the resume command 30h to continue operation of sector erase. AS29F040 ignores redundant writes of the resume command. AS29F040 permits multiple suspend/resume operations during sector erase. Sector protect When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors. Item Description

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 6WDWXV#RSHUDWLRQV :ULWH#RSHUDWLRQ#VWDWXV DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip algorithm (1 after completion of erase agorithm). T oggle bit 1 (DQ6) Active during automated on-chip algorithms or sector time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. When the automated on-chip algorithm is complete, DQ6 stops toggling and valid data can be read. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during writes, and <5 µs during erase (if all selected sectors are protected). Exceeding time limit (DQ5) Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are defective; during sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors); during byte programming, that particular byte is defective. Attempting to program 0 to 1 will set DQ5 = 1. Sector erase timer (DQ3) Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept additional sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. T oggle bit 2 (DQ2) During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. Status DQ7 DQ6 DQ5 DQ3 DQ2 In progress Auto programming (byte) DQ

7 Toggle 0 0 No toggle

Program/erase in auto erase 0 Toggle 0 1 T oggle * * T oggles with OE or CE only for erasing or erase suspended sector addresses. Erase suspend mode Read erasing sector 1 No toggle 0 0 T oggle Read non-erasing sector Data Data Data Data Data Program in erase suspend DQ

7 Toggle 0 0 T oggle *

Auto programming (byte) DQ 7 Toggle 1 0 No toggle Program/erase in auto erase 0 Toggle 1 1 T oggle † † T oggles with OE or CE only for erasing or erase suspended sector addresses. Program in erase suspend DQ 7 Toggle 1 0 No toggle †

$XWRPDWHG#RQ0FKLS#SURJUDPPLQJ#DOJRULWKP IRU#HDFK#E\\WH $XWRPDWHG#RQ0FKLS#HUDVH#DOJRULWKP * The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. Write program command sequence (see below) DATA poll device-program Programming completed 5555h/AAh 2AAAh/55h 5555h/A0h Program address/program data Program command sequence Erase complete DATA polling or toggle bit successfully completed Write erase command sequence (see below) 5555h/AAh 2AAAh/55h 5555h/80h Chip erase command sequence 5555h/AAh 2AAAh/55h 5555h/10h Sector erase command sequence Sector address/30h Sector address/30h Sector address/30h Optional multiple sector erase commands* 5555h/AAh 2AAAh/55h 5555h/80h 5555h/AAh 2AAAh/55h

'$7$#SROOLQJ#DOJRULWKP * VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during sector erase. VA = valid address equals any non-protected sector group address during chip erase. † DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously . 7RJJOH#ELW#DOJRULWKP * DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. Read byte (DQ0–DQ7) Address = VA * Read byte (DQ0–DQ7) Address = VA * NO DONE NO NO YES YES YES DONE DQ7 = data? YES NO Is time elapsed = 1ms? DONE START Issue Reset/read command Addr = X Data = F0h DQ5 = 1? DQ7 = data†? Read byte (DQ0–DQ7) Address = don’t care Read byte (DQ0–DQ7) Address = don’t care NO DONE YES YES YES NO NO DONE DQ6 toggle? toggle*? DQ5 = 1? START two times with OE toggling Does two times with OE toggling Does DQ6 DONE Issue Reset/read command Addr = X Data = F0h

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ 3URJUDPPLQJ#DOJRULWKP#IRU#FKLS Start VA* = 0000h Is V A = V A_Start†? Increment V A NO YES Program byte with customer data ADDR = VA Increment V A I s VA = VA _ E n d**? NO Increment V A YES Program byte with 00h ADDR = V A Program byte with 00h ADDR = VA NO Increment V A Is V A = 7FFFFh? YES V erify data ADDR = V A Verify OK? NO FAIL YES I s VA = VA _ E n d ?Increment VA NO YES PASS Reset V A = 0000 * V A = Current Address † V A_Start = Starting Address of Customer Code ** V A_End = Ending Address of Customer Code

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 '&#HOHFWULFDO#FKDUDFWHULVWLFV 9&&# #813±3189 * Not more than one output tested simultaneousl y. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.) † The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is less than 2 mA/MHz with OE at VIH. ** ICC active while program or erase operations are in progress. 0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP 0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP Parameter Symbol T est conditions Min Max Unit Input load current I LI VIN = VSS to VCC, VCC = VCC MAX -± 1 µA A9 Input load current I LIT VCC = VCC MAX, A9 = 12.5V 90 µA Output leakage current I LO VOUT = VSS to VCC, VCC = VCC MAX -± 1 µA Output short circuit current* IOS VOUT = 0.5V - 200 mA Active current, read @ 6MHz† ICC CE = VIL, OE = VIH -3 0 m A Active current, program/erase** ICC2 CE = VIL, OE = VIH -6 0 m A Standby current (TTL) I SB1 CE = OE = VIH, VCC = VCC MAX -1 . 0 m A Standby current (CMOS) I SB2 CE = VCC + 0.5V , OE = VIH, VCC = VCC MAX -4 0 0 µ A Input low voltage V IL -0.5 0.8 V Input high voltage V IH 2.0 V CC + 0.5 V Output low voltage V OL IOL = 12mA, VCC = VCC MIN -0 . 4 5 V Output high voltage VOH1 IOH = -2.5 mA, VCC = VCC MIN 2.4 - V VOH2 IOH = -100 µA, VCC = VCC MIN VCC - 0.4 - V Low VCC lock out voltage V LKO 2.8 4.2 V Input HV select voltage V ID 11.5 12.5 V 20 ns20 ns20 ns -2.0V -0.5V +0.8V /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 20 ns20 ns20 ns VCC + 2.0V VCC + 0.5V + 2.0V /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ $&#SDUDPHWHUV=#UHDG#F\\FOH .H\\#WR#VZLWFKLQJ#ZDYHIRUPV 5HDG#ZDYHIRUP JEDEC Symbol Std Symbol Parameter -55 -70 -90 -120 -150 UnitMin Max Min Max Min Max Min Max Min Max tAVAV tRC Read cycle time 55 - 70 - 90 - 120 - 150 - ns tAVQV tACC Address to output delay - 55 - 70 - 90 - 120 - 150 ns tELQV tCE Chip enable to output - 55 - 70 - 90 - 120 - 150 ns tGLQV tOE Output enable to output - 25 - 30 - 35 - 50 - 55 ns tEHQZ tDF Chip enable to output High Z - 15 - 20 - 20 - 30 - 35 ns tGHQZ tDF Output enable to output High Z - 15 - 20 - 20 - 30 - 35 ns tAXQX tOH Output hold time from addresses, CE or OE, whichever occurs first 0-0-0-0-0-n s /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Undefined / don’t care /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Falling input /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Rising input /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0Addresses stableAddresses tRC tACC tOE tCE tOH tDF CE OE WE Outputs High Z High ZOutput valid

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 $&#SDUDPHWHUV#³#ZULWH#F\\FOH :(#FRQWUROOHG :ULWH#ZDYHIRUP :(#FRQWUROOHG JEDEC Symbol Std Symbol Parameter -55 -70 -90 -120 -150 UnitMin Max Min Max Min Max Min Max Min Max tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns tAVWL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns tWLAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns tDVWH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns tWHDX tDH D a t a h o l d t i m e 0 -0-0-0-0- n s tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: T oggle and DATA polling 10 - 10 - 10 - 10 - 10 - ns tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - 0 - ns tELWL tCS CE s e t u p t i m e 0 -0-0-0-0- n s tWHEH tCH CE h o l d t i m e 0 -0-0-0-0- n s tWLWH tWP Write pulse width 35 - 35 - 45 - 50 - 50 - ns tWHWL tWPH Write pulse width high 20 - 20 - 20 - 20 - 20 - ns tWHWH1 tWHWH1 Programming pulse time 15 - 15 - 15 - 15 - 15 - µs /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Addresses CE OE WE DATA VSS tWC tAS tAH tGHWL;tOES tWP tCS tWPH tDH tWHWH1 or 2 tDS DQ7 DOUT Program 5555h Program address Program address 3rd bus cycle tCH DATA polling dataA0h

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ $&#SDUDPHWHUV³ZULWH#F\\FOH#5 &(#FRQWUROOHG :ULWH#ZDYHIRUP#5 &(#FRQWUROOHG JEDEC Symbol Std Symbol Parameter -55 -70 -90 -120 -150 UnitMin Max Min Max Min Max Min Max Min Max tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns tAVEL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns tELAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns tDVEH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns tEHDX tDH D a t a h o l d t i m e 0-0-0-0-0- n s tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns tOEH Output enable hold time: Toggle and DATA polling 10 - 10 - 10 - 10 - 10 - ns tGHEL tGHEL Read recover time before write 0-0-0-0-0- n s tWLEL tWS WE s e t u p t i m e 0-0-0-0-0- n s tEHWH tWH WE h o l d t i m e 0-0-0-0-0- n s tELEH tCP CE pulse width 35 - 35 - 45 - 50 - 50 - ns tEHEL tCPH CE pulse width high 20 - 20 - 20 - 20 - 20 - ns tWHWH1 tWHWH1 Programming pulse time 15 - 15 - 15 - 15 - 15 - µs /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Addresses WE OE CE DATA Program address5555h Program address A0h Program DQ7D OUT tWC tAS tAH tCP tCPH tDH tDS tWHWH1 or 2 DATA polling data tGHEL, tOES tWS tWH

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 (UDVH#ZDYHIRUP '$7$#SROOLQJ#ZDYHIRUP 7RJJOH#ELW#ZDYHIRUP Addresses CE OE WE Data 5555h 2AAAh 5555h 5555h 2AAAh Sector address tWC tAS tAH tGHWL AAh 55h 80h AAh 55h 30h 10h for Chip Erase tWP tCS tWPH tDH tDS tWC /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CE OE WE DQ7 tCH tOH tWHWH1 or 2 tOE tOEH tCE tDF High ZInput DQ7 Output DQ7 Output /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 CE WE OE DQ6 tOEH tDH tOE

$65<)373$65<)373$65<)373$65<)373 3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ3UHOLPLQDU\\#LQIRUPDWLRQ (UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH /DWFKXS#WROHUDQFH# Includes all pins except VCC. Test conditions: VCC = 5.0V , one pin at a time. $&#WHVW#FRQGLWLRQV $EVROXWH#PD[LPXP#UDWLQJV NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilit y. Includes all pins except VCC. Test conditions: VCC = 5.0V , one pin at a time. Parameter Limits UnitMin Typical Max Sector erase and verify-1 time (excludes 00h programming prior to erase) - 1.0 - sec Byte program time - 45 - µs Chip programming time - 23 -s e c Erase/program cycles - - 10,000 cycles Parameter Min Max Unit Input voltage with respect to VSS on A9 and OE -1.0 +13.0 V Input voltage with respect to VSS on all DQ, address and control pins -1.0 V CC+1.0 V Current -100 +100 mA Parameter Symbol Min Max Unit Input voltage (Input or DQ pin) V IN –2.0 +7.0 V Input voltage (A9 pin, OE)V IN –2.0 +13.0 V Power supply voltage V CC -0.5 +5.5 V Operating temperature T OPR –55 +125 °C Storage temperature (plastic) T STG –65 +125 °C Short circuit output current I OUT -2 0 0 m A 100 pF* Device under Test *including scope and jig capacitance V SS T est condition Unit Output load 1 TTL gate Input rise and fall times 5 ns Input pulse levels 0.0-3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5

0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 5HFRPPHQGHG#RSHUDWLQJ#FRQGLWLRQV 7623#SLQ#FDSDFLWDQFH 3/&&#SLQ#FDSDFLWDQFH 'DWD#UHWHQWLRQ Parameter Symbol Min Typ Max Unit Supply voltage VSS 000V Input voltage VIH 2.0 - V CC + 0.5 V VIL –0.5 - 0.8 V Symbol Parameter T est setup Typ Max Unit CIN Input capacitance V IN = 0 6 7.5 pF COUT Output capacitance V OUT = 0 8.5 12 pF CIN2 Control pin capacitance V IN = 0 7.5 9 pF Symbol Parameter T est setup Typ Max Unit CIN Input capacitance V IN = 0 6 7.5 pF COUT Output capacitance V OUT = 0 8.5 12 pF CIN2 Control pin capacitance V IN = 0 7.5 9 pF Parameter T emp. (°C) Min Unit Minimum pattern data retention time 150° 10 years 125° 20 years

DID 11-20011-A. Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsi- bility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem- nify Alliance against all claims arising from such use. 0DUFK#53330DUFK#53330DUFK#53330DUFK#5333 3DFNDJH#GLPHQVLRQV $65<)373#RUGHULQJ#FRGHV- $65<)373#SDUW#QXPEHULQJ#V\\VWHP Package \\ Access time 55ns (commercial/industrial) 70 ns (commercial/industrial) 90 ns (commercial/industrial) 120 ns (commercial/industrial) 150 ns (commercial/industrial) TSOP , 8×20 mm, 32-pin AS29F040-55TC AS29F040-55TI AS29F040-70TC AS29F040-70TI AS29F040-90TC AS29F040-90TI AS29F040-120TC AS29F040-120TI AS29F040-150TC AS29F040-150T PLCC, 0.55×0.45”, 32-pin AS29F040-55LC AS29F040-55LI AS29F040-70LC AS29F040-70LI AS29F040-90LC AS29F040-90LI AS29F040-120LC AS29F040-120LI AS29F040-150LC AS29F040-150LI * Industrial and Commercial temperature range available AS29F 040 –XXX X X Flash EEPROM prefix Device number Address access time Package: L= PLCC T= TSOP T emperature range: C = Commercial: 0°C to 70°C I = Industrial: -40°C to 85°C e f g b a c d i h j 0–5° 32-pin TSOP min (mm) max (mm) a1 . 2 0 b0 . 2 5 c0 . 5 0 . 7 d0 . 1 0 . 2 1 e 18.30 18.50 f 19.80 20.20 g 7.90 8.10 h 0.95 1.05 i 0.05 0.15 j0 . 5 0 32-pin TSOP 32-pin PLCC 12 3 23 13 043 1716 18 19 2014 15 a b d c e f g h i j JEDEC outline MS-016 AE Body size 0.450 in. × 0.550 in. Package thickness 0.110 in. Board standoff 0.020 in. (min) Lead pitch 0.050 in. Coplanarity 0.004 in. (max) 32-pin PLCC typical (inch) a0 . 4 9 b0 . 4 5 c0 . 5 9 d0 . 5 5 e0 . 5 2 f0 . 0 9 g0 . 1 3 6 h0 . 0 7 5 i0 . 5 2 j0 . 0 2 8

Product Information

AS29F040-150T specifications and overview.

Summary

5V 512K x 8 CMOS FLASH EEPROM

Description

5V 512K x 8 CMOS FLASH EEPROM

Source title AS29F040-150T Datasheet(PDF) - Alliance Semiconductor Corporation

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