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128K X 8 Bit CMOS 5.0 Volt-only Document Title 128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

1.0 Preliminary July 8, 2019 Initial issue

  • 1 of 28 - Rev.1.0. July. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice

128K X 8 Bit CMOS 5.0 Volt-only

Features

„ 5.0V ± 10% for read and write operations „ Access times: - 55ns(max.) „ Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 μA typical CMOS standby „ Flexible sector architecture - 32 KbyteX4 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or eras e operations within that sector „ Embedded Erase Algorithms - Embedded Erase algorithm wi ll automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses „ Minimum 100,000 program/erase cycles per sector „ 20-year data re tention at 125°C - Reliable operation for the life of the system „ Compatible with JEDEC-standards - Pinout and softwa re compatible with single-power-supply Fl ash memory standard - Superior inadvertent write protection „ Data Polling and toggle bits - Provides a software method of detecting completion of program or eras e operations „ Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation „ Package options - 32-pin PLCC „ Industrial operating temperature range: -40°C to 85°C General Description The AS29CF010-55CCIN is a 5.0 volt-only Flash memory org anized as 131,072 bytes of 8 bits each. The 128 Kbytes of data are further divided into four sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 - I/ O7 while the addresses are input on A0 to A16. The AS29CF010-55CCIN is offered in 32-pin PLCC packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-sys tem write or erase operations . However, the AS29CF010-55CCIN can also be pro grammed in standard EPROM programmers. The AS29CF010-55CCIN has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the AS29CF010-55CCIN has a s econd toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The AS29CF010-55CCIN also offers the ability to program in the Erase Suspend mode. The standard AS29CF010-55CCIN offers access times of 55 ns allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable (OE ) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The AS29CF010-55CCIN is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machin e that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs b y writing the proper program command sequenc e. Th is initiates the Embedded Program algorithm - an intern al algorithm that automatically tim es the program pulse widths and verifies proper program margin. Device erasure occurs by exec uting the proper erase command seq uence. This initiates th e Embedded Erase algorithm - an internal algor ithm that automatically preprograms the array (if it is not already programmed) before executing the erase operati on. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The host system can detect whether a program or erase operation is complete by rea ding the I/O 7 ( Data Polli ng) and I/O6 (toggle) status bits. After a program or erase cy cle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows mem ory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The AS29CF010-55CCIN is fully eras ed when shipped from the factory. The hardw are sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power co nsumption is greatly reduced when the device is placed in the standb y mode. AS29CF010-55CCIN Confidential - 2 of 28 - Rev.1.0. July. 2019

„ PLCC I/O0 21 CE I/O7 A10 OE A11 A13 A14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A12 A15 A16 NC VCC WE NC AS29CF010-55CCIN AS29CF010-55CCIN Confidential - 3 of 28 - Rev.1.0. July. 2019

Pin No. Description A0 - A16 Address Inputs I/O0 - I/O7 Data Inputs/Outputs CE Chip Enable WE Write Enable OE Output Enable VSS Ground VCC Power Supply State Control Command Register Address Latch X-decoder Y-Decoder Chip Enable Output Enable Logic Cell Matrix Y-Gating VCC Detector PGM Voltage Generator Data Latch Input/Output BuffersErase Voltage Generator VCC VSS WE CE OE A0-A16 I/O0 - I/O7 Timer STB STB AS29CF010-55CCIN Confidential - 4 of 28 - Rev.1.0. July. 2019

Ambient Temperature with Power Applied ………………………..

  1. Minimum DC voltage on input or I/O pins is -0.5V. During

may overshoot to VCC +2.0V for periods up to 20ns.

  1. Minimum DC input voltage on A9 pins is -0.5V. During
  2. No more than one output is s horted at a time. Duration of

the short circuit should not be greater than one second. sections of these s pecification is not implied or intended. extended periods may affect device reliability. functionally of the device is guaranteed. these operations in further detail. Table 1. AS29CF010-55CCIN Device Bus Operations

array data upon device power-up, or after a hardware reset. register contents are altered. current specification for reading array data. suspending/resuming the erase operation. diagrams for write operations. and to each AC Characteristics section for timing diagrams. the high impedance state, independent of the OE input. access time (tCE) before it is ready to read data. device draws active current until the operation is completed. Table 2. AS29CF010-55CCIN Block Sector Address Table

accessed in-system through the command register. details on using the autoselect mode. Table 3. AS29CF010-55CCIN Autoselect Codes (High Voltage Method)

Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re -enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Hardware Data Protection The requirement of command unlocking sequence for programming or erasing provi des data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array. Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE , CE or WE do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE =VIL, CE = V IH or WE = V IH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Po wer-Up Write Inhibit If WE = CE = V IL and OE = V IH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on the initial power-up. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in th e improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O 5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autosel ect mode, and the system may read at any address any number of times, without initiating another command sequence. Byte Program Command Sequence Programming is a four-bus-cyc le operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al gorithm. The system is not required to provide further c ontrols or timings. The device automatically provides intern ally generated program pulses and verify the programmed cell margin. The Command Definitions table shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are AS29CF010-55CCIN Confidential - 8 of 28 - Rev.1.0. July. 2019

  1. See the appropriate Command Definitions table for erase

3 : Sector Erase Timer" for more information. Figure 2. Erase Operation "don't cares" when writing the Erase Suspend command. and suspends the erase operation. sequence when the device is in the Erase Suspend mode.

Table 4. AS29CF010-55CCIN Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16 - A15 select a unique sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles are write operation.
  4. Address bits A16 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
  5. No unlock or command cycles required when reading array data.
  6. The Reset command is required to return to reading arra y data when device is in the autoselect mode, or if I/O 5 goes high

(while the device is providing status data).

  1. The fourth cycle of the autoselec t command sequence is a read cycle.
  2. The data is 00h for an unprotected se ctor and 01h for a protected sector. See "Autoselect Command Sequence" for more
  3. The system may read and program in non- erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
  4. The Erase Resume command is valid only during the Erase Suspend mode.
  5. The time between each command cycle has to be less than 50μs

program or erase operation is complete or in progr ess. These three bits are discussed first. program or erase command sequence. on I/O7 the complement of the datum programmed to I/O7. read valid status information on I/O7. sectors, and ignores the selected sectors that are protected. I/O7. Figure 3 shows the Data Polling algorithm.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

  1. I/O7 should be rechecked even if I/O 5 = "1" because

I/O7 may change simultaneously with I/O 5. Figure 3. Data Polling Algorithm

I/O6: Toggle Bit I Toggle Bit I on I/O 6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O 6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O 6 toggles for approximately 100μs, then returns to reading array data. If not all selected sectors are pr otected, the Embedded Erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. The system can use I/O 6 and I/O 2 together to determine whether a sector is actively er asing or is erase-suspended. When the device is actively er asing (that is, the Embedded Erase algorithm is in progress), I/O6 toggles. When the device enters the Erase Suspend mode, I/O 6 stops toggling. However, the system must also use I/O 2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use I/O 7 (see the subsection on " I/O 7 : Data Polling"). If a program address falls within a protected sector, I/O toggles for approximately 2 μs after the program command sequence is written, then returns to reading array data. I/O 6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operatio n Status table shows the outputs for Toggle Bit I on I/O 6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O 6 in graphical form. See also the subsection on " I/O 2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 4 shows the toggle bit algorithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading t oggle bit status, it must read I/O 7 - I/O 0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O 7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragr aph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the begi nning of the algorithm when it returns to determine the status of the operation (top of Figure 4). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O 5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O 5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O 5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. I/O3: Sector Erase Timer After writing a sector erase command sequence, the system may read I/O3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O 3 switches from "0" to "1." The system may ignore I/O 3 if the system can guarantee that the time between additional sector erase commands will always be less than 50μs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O 7 ( Data Polling) or I/O 6 (Toggle Bit 1) to ensure the device has accepted the command sequence, and then read I/O 3. If I/O 3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the AS29CF010-55CCIN Confidential - 13 of 28 - Rev.1.0. July. 2019

accepted. Table 5 shows the outputs for I/O3.

  1. Read toggle bit twice to determine whether or not it is
  2. Recheck toggle bit because it may stop toggling as I/O5

Figure 4. Toggle Bit Algorithm

Table 5. Write Operation Status

1 No toggle 0 N/A Toggle

  1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See

“I/O5: Exceeded Timing Limits” for more information.

Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max ±1.0 μA ILIT A9 &OE Input Load Current VCC = VCC Max, A9 & OE = 12.5V 100 μA ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max ±1.0 μA ICC1 VCC Active Read Current (Notes 1, 2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE = VIL, OE =VIH 30 40 mA ICC3 VCC Standby Current (Note 2) CE = VIH 0.4 1.0 mA VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 VCC+0.5 V VID Voltage for Autoselect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12mA, VCC = VCC Min 0.45 V VOH Output High Voltage IOH = -2.5 mA, VCC = VCC Min 2.4 V CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 μA ILIT A9 & OE Input Load Current VCC = VCC Max, A9 & OE = 12.5V 100 μA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 μA ICC1 VCC Active Read Current (Notes 1,2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2,3,4) CE = VIL, OE = VIH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE = VCC ± 0.5 V 1 5 μA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC VCC+0.3 V VID Voltage for Autoselect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = -2.5 mA, VCC = VCC Min 0.85 x VCC V VOH2 IOH = -100 μA. VCC = VCC Min VCC-0.4 V Notes for DC characteristics (both tables): 1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, withOE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, ICC3 = 20μA max at extended temperatures (> +85°C). AS29CF010-55CCIN Confidential - 16 of 28 - Rev.1.0. July. 2019

tAVAV t RC Read Cycle Time (Note 2) Min. 55 ns tAVQV t ACC Address to Output Delay CE = VIL OE = VIL Max. 55 ns tELQV t CE Chip Enable to Output Delay OE = VIL Max. 55 ns tGLQV t OE Output Enable to Output Delay Max. 30 ns tOEH Output Enable Hold Time (Note 2) Read Min. 0 ns Toggle and Data Polling Min. 10 ns tEHQZ t DF Chip Enable to Output High Z Max. 18 ns tGHQZ t DF Output Enable to Output High Z 18 ns tAXQX t OH Output Hold Time from Addresses, CE or OE , Whichever Occurs First Min. 0 ns Notes: 1. Output driver disable time. 2. Not 100% tested. Timing Waveforms for Read Only Operation Addresses Addresses Stable CE OE WE Output Valid High-ZOutput tRC tOEH tOE tCE High-Z tOH tDF tACC AS29CF010-55CCIN Confidential - 17 of 28 - Rev.1.0. July. 2019

Erase and Program Operations Parameter Symbols Description Speed Unit JEDEC Std -55 tAVAV tWC Write Cycle Time (Note 1) Min. 55 ns tAVWL tAS Address Setup Time Min. 0 ns tWLAX tAH Address Hold Time Min. 40 ns tDVWH tDS Data Setup Time Min. 25 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL t CS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 ns tWHWL t WPH Write Pulse Width High Min. 20 ns Max. 50 μs tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ. 7 μs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 1 sec tVCS VCC Set Up Time (Note 1) Min. 50 μs Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. AS29CF010-55CCIN Confidential - 18 of 28 - Rev.1.0. July. 2019

Timing Waveforms for Program Operation Addresses CE OE WE Data VCC A0h PD tWC PA Program Command Sequence (last two cycles) PA DOUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tGHWL tWP tWPHtCS tDS tDH Note : PA = program addrss, PD = program data, Dout is the true data at the program address. AS29CF010-55CCIN Confidential - 19 of 28 - Rev.1.0. July. 2019

Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tGHWL tWP tWPH tCS tDS tDH Note : SA = Sector Address. VA = Valid Address for reading status data. 555h for chip erase 10h for chip erase Timing Waveforms for Chip/Sector Erase Operation AS29CF010-55CCIN Confidential - 20 of 28 - Rev.1.0. July. 2019

Timing Waveforms for Data Polling (During Embedded Algorithms) Timing Waveforms for Toggle Bit (During Embedded Algorithms) Note: VA = Valid Address; not required for I/O 6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O0 - I/O6 tAC C tCE tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O6 , I/O2 tRC VAVA VA Valid Status tACC tCE tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Status (first read) (second read) (stop togging) AS29CF010-55CCIN Confidential - 21 of 28 - Rev.1.0. July. 2019

Timing Waveforms for I/O2 vs. I/O6 AC Characteristics Erase and Program Operations Alternate CE Controlled Writes Parameter Symbols Desc ription Speed Unit JEDEC Std -55 tAVAV tWC Write Cycle Time (Note 1) Min. 55 ns tAVEL tAS Address Setup Time Min. 0 ns tELAX tAH Address Hold Time Min. 40 ns tDVEH tDS Data Setup Time Min. 25 ns tEHDX tDH Data Hold Time Min. 0 ns tGHEL t GHEL Read Recover Time Before Write Min. 0 ns tWLEL tWS WE Setup Time Min. 0 ns tEHWH tWH WE Hold Time Min. 0 ns tELEH tCP Write Pulse Width Min. 30 ns tEHEL tCPH Write Pulse Width High Min. 20 ns tWHWH1 t WHWH1 Byte Programming Operation (Note 2) Typ. 7 μs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 1 sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O6 I/O2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O2 and I/O6 toggle with OE and CE Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O 6 and I/O2 in the section "Write Operation Statue" for more information. Erase Suspend Program ~~~~ AS29CF010-55CCIN Confidential - 22 of 28 - Rev.1.0. July. 2019

Timing Waveforms for Alternate CE Controlled Write Operation Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 1 8 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time 8 64 sec Byte Programming Time 35 300 μs Excludes system-level overhead (Note 5) Chip Programming Time (Note 3) 3.6 10.8 sec Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 5.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If t he maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles. Addresses WE OE CE Data 555 for program 2AA for erase PA DOUT ~~~~ I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O 7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tGHEL tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH AS29CF010-55CCIN Confidential - 23 of 28 - Rev.1.0. July. 2019

Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE ) -1.0V 12.5V Includes all pins except VCC. Te st conditions: VCC = 5.0V, one pin at time. PLCC Pin Capacitance Parameter Symbol Parameter Descripti on Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 4 6 pF COUT Output Capacitance VOUT=0 8 12 pF CIN2 Control Pin Capacitance VPP=0 8 12 pF Notes: 3. Sampled, not 100% tested. 4. Test conditions TA = 25°C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years AS29CF010-55CCIN Confidential - 24 of 28 - Rev.1.0. July. 2019

Output Load Capacitance, CL(including jig capacitance) 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0.0 - 3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Test Setup 6.2 KΩ Device Under Test CL Diodes = IN3064 or Equivalent 2.7 KΩ 5.0 V AS29CF010-55CCIN Confidential - 25 of 28 - Rev.1.0. July. 2019

Package Information

PLCC 32L Outline Dimension unit: inches/mm A1 A2 A e D y HD D GD b GE c 21 29 E HE L θ Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions G D & GE are for PC Board surface mount pad pitch design reference only. AS29CF010-55CCIN Confidential - 26 of 28 - Rev.1.0. July. 2019

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package 55 20 30 1 AS29CF010-55CCIN 32Pin Pb-Free PLCC AS29CF010-55CCIN Confidential - 27 of 28 - Rev.1.0. July. 2019

  • 28 of 28 - Rev.1.0. July. 2019 Alliance Memory, Inc.

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San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. PART NUMBERING SYSTEM (-40°C+85°C) AS 29 C F010 -55 CC I N Alliance Memory Parallel Flash Device Voltage code C=5.0V (4.5V~5.5V) Flash device density Speed grade 55ns 32Pin Pb-Free PLCC Industrial temp ROHS compliant Pb and Halogen Free