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AR0260 DS Rev. G Pub. 4/15 EN 1 ©Semiconductor Components Industries, LLC,2015 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor AR0260 Datasheet, Rev. G For the latest datasheet, please visit www.onsemi.com
- Superior low-light performance Ultra-low-power 1080p Full HD video at 30 fps 1.4 m pixel with ON Semiconductor A-Pix™ technology Internal master clock generated by on-chip phase locked loop (PLL) oscillator Electronic rolling shutter (ERS), progressive scan Programmable controls: gain, horizontal and vertical blanking, auto black level offset correction, frame size/rate, exposure, left–right and top–bottom image reversal, window size, and panning. Arbitrary image scalin g with anti-aliasing Two-wire serial interface providing access to registers and microcontroller memory Selectable output data format: RAW8 and RAW8+2- bit Parallel and 1- or 2-lane MIPI data output Adaptive polynomial lens shading correction
Applications
Embedded tablet, notebook, and tethered PC cameras Game consoles Cell phones, mobile devices Consumer video communications General Description ON Semiconductor 's AR0260 is a 1/6-inch 2.0Mp Full HD CMOS digital image sensor with an active-pixel array of 1920H x 1080V . It incorporates sophisticated on-chip camera functions such as windowing, mirror- ing, column and row skip modes, and snapshot mode. It is programmable through a simple two-wire serial interface. It is designed for low light performance.The AR0260 produces extraordinarily clear, sharp digital pictures, making it the perfect choice for a wide range of applications, including PC and notebook cameras, gaming systems, and mobile phones. Notes: 1. Power consumption for typical voltages and full resolu- tion, maximum frame rate output, excluding I/O. Table 1: Key Parameters Parameter Typical Value Optical format 1/6-inch Active pixels 1920 x 1080 Pixel size 1.4 m Color filter array RGB Bayer Shutter type Electronic rolling shutter (ERS) Input clock range 6 – 54 MHz Output pixel clock maximum 96 MHz Output MIPI data rate maximum
768 Mb/s per lane
Frame Rate 1080p (full res) 30 fps 720p 60 fps VGA 60 fps QVGA 120 fps Responsivity 0.64 V/lux-sec SNR MAX 33 dB Pixel dynamic range 65 dB Supply voltage Digital 1.7 – 1.95 V Analog 2.5 – 3.1 V I/O 1.7 – 1.95 V or 2.5 – 3.1 V PHY 1.7 – 1.95 V Power consumption 1 270 mW Operating temperature –30 °C to +70° C Chief ray angle 28 ° Package options CSP , Bare die
AR0260 DS Rev. G Pub. 4/15 EN 2 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor
Ordering Information
Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0260LCSC28SUKAL-A-CR 2 MP 1/6" CIS Chip Tray without Protective Film
AR0260 DS Rev. G Pub. 4/15 EN 3 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Table of Contents Table of Contents
AR0260 DS Rev. G Pub. 4/15 EN 5 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor List of Tables List of Tables
AR0260 DS Rev. G Pub. 4/15 EN 6 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Functional Description Functional Description The ON Semiconductor AR0260 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080p- resolution image at 30 frames per second (fps). It outputs 8-bit or 10-bit raw data, using either the parallel or serial (MIPI) output ports. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0260 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, mirroring, and sub-sampling. Optional register information can be embedded in the first and last 2 lines of the image frame. The sensor is designed to operate in a wide temperature range (–30°C to +70°C). Architecture Overview The AR0260 is a 1/6-inch 2.0Mp progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 54 MHz. The maximum output pixel rate is 96 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: AR0260 Block Diagram User interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 2.0 Mp Active- Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an Sensor Core Control Registers System Control 10-Bit Data Out Parallel or MIPI G1/G2 R/B G1/G2 R/B Green1/Green2 Channel Red/Blue Channel 1080p Active-Pixel Sensor (APS) Array Analog Processing ADC Digital Processing Timing and Control
AR0260 DS Rev. G Pub. 4/15 EN 7 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Functional Description analog signal chain (providing offset correction and gain), and then through an analog- to-digital converter (ADC). The output from the ADC is a 10-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). Finally, the output from the digital processing chain is passed either to the parallel or serial (MIPI) data port for transmission to the host system. The AR0260 also includes programmable I/O slew rate to minimize EMI. System Interfaces Figure 2 on page 8 shows typical AR0260 device connections. For low-noise operation, the AR0260 requires separate power supplies for analog and digital sections of the die. Both power supply rails must be decoupled from ground using capacitors as close as possible to the die. The use of inductance filters is not recommended on the power supplies or output signals. The AR0260 provides dedicated inputs for digital core, PHY, and I/O power domains that can be at different voltages. The PLL and analog circuitry require clean power sources. Table 3 on page 9 provides the signal descriptions for the AR0260.
AR0260 DS Rev. G Pub. 4/15 EN 8 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Functional Description Figure 2: Typical Configuration Notes: 1. This typical configuration shows only one scenar io out of multiple possible variations for this sen- sor. 2. If a MIPI Interface is not required, the MIPI serial port must be left floating. The V DD_PHY power sig- nal must always be connected to the 1.8V supply. 3. Only one of the output modes (serial or parallel) can be used at any time. 4. ON Semiconductor recommends a 1.5k resistor value for the two-wire serial interface RPULL-UP; however, greater values may be used for slower transmission speed. 5. All inputs must be configured with V DD_IO. 6. RESET_BAR has an internal pull-up resistor and can be left floating. 7. ON Semiconductor recommends that 0.1 F and 1F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and numbers may vary depending on layout and design considerations. 8. TRST_BAR and GPIO1 connect to GND for normal operation. VAA7 SDATA SCLK SADDR AGND I/O5 power VDDVAA VAA_PIX Two-wire serial interface RPULL-UP RESET_BAR6 Analog power EXTCLKExternal clock in (6–54 MHz) Active LOW reset DGND VDD_PHY2, 7VDD_IO5, 7 VDD_PHYVDD_IO TRST_BAR8 SHUTDOWNActive HIGH Shutdown GPIO1 FRAME_VALID PIXCLK LINE_VALID DOUT[7:0] DATA_2P DATA_2N Parallel Port OR3 CLK_N DATA_P MIPI Serial Port2 DATA_N CLK_P REG_OUT REG_FBREG_IN0 0.1µF Digital power
AR0260 DS Rev. G Pub. 4/15 EN 9 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Functional Description Notes: 1. A GND and DGND are not connected internally. 2. To be left floating if not using feature. 3. Must always be connected even when not using MIPI. 4. The V DD and REG_FB pins must be connected together and have a 0.1F decoupling capacitor attached. 5. GPIO1 pin functions as CONFIG during power-on cycle. GPIO1 pin must be driven low during power-on cycle. GPIO1 pin should be either connected to DGND or needs pull-down resistor. Table 3: Pin Descriptions Name Type Description Note EXTCLK Input Input clock signal. RESET_BAR Input/PU Master reset signal, active LOW. This signal has an internal pull up. SCLK Input Two-wire serial interface clock. SDATA I/O Two-wire serial interface data. SADDR Input Selects device address for the two-wire serial interface. FRAME_VALID (FV) Output Identifies rows in the active image. LINE_VALID (LV) Output Identifies pixels in the active line. PIXCLK Output Pixel clock. DOUT[7:0] Output D OUT[7:0] for 8-bit image data output or DOUT[9:2] for 10-bit image data output. CLK_N Output Differential MIPI clock (sub-LVDS, negative). 2 CLK_P Output Differential MIPI clock (sub-LVDS, positive). 2 DATA_N Output Differential MIPI data (sub-LVDS, negative). 2 DATA_P Output Differential MIPI data (sub-LVDS, positive). 2 DATA_2N Output Differential MIPI data (sub-LVDS, negative). 2 DATA_2P Output Differential MIPI data (sub-LVDS, positive). 2 GPIO0 Input/Output General purpose input/output. GPIO1 Input/Output General purpose input/output. 5 GPIO2 Input/Output General purpose input/output. SHUTDOWN Input Low power shutdown control, active HIGH. TRST_BAR Input Must be tied to D GND in normal operation. VDD Supply Digital power. Must connect to REG_FB. 4 DGND Supply Digital ground. 1 VDD_IO Supply I/O power supply. VAA Supply Analog power. VAA_PIX Supply Analog pixel power. AGND Supply Analog ground. 1 VPP Supply Reserved. To be left floating in normal operation. REG_IN0 Supply Digital power. Must connect to V DD_PHY. REG_OUT Supply Digital power output. REG_FB Supply Digital power. Must connect to V DD.4 VDD_PHY Supply I/O power supply for the MIPI interface. Must connect to REG_IN0 3
AR0260 DS Rev. G Pub. 4/15 EN 12 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Power-Down Sequence Reset Modes Three types of reset are available: A n i n t e r n a l p o w e r - o n r e s e t A hard reset is issued by toggling the RESET_BAR signal A soft reset is issued by writing commands through the two-wire serial interface Power-On Reset The AR0260 includes a power-on reset feature that initiates a reset upon power-up. The RESET_BAR signal has an internal pull-up resistor and can be left floating. Hard Reset The AR0260 enters the reset state when the external RESET_BAR signal is asserted LOW, as shown in Figure 5. Parallel data output signals will be in High-Z state. Figure 5: Hard Reset Operation Notes: 1. This delay is depend ent on EXTCLK frequency. Table 6: Hard Reset Symbol Definition Min Typ Max Unit t1 RESET_BAR pulse width 50 – – EXTCLK cyclest2 Active EXTCLK required after RESET_BAR asserted 10 – – t3 Active EXTCLK required before RESET_BAR de-asserted 10 – – t4 Maximum internal boot time 1 –– 3 5 m s EXTCLK Reset RESET_BAR Mode Internal Boot Time SDATA Enter standy mode All Outputs Data Active
AR0260 DS Rev. G Pub. 4/15 EN 13 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Power-Down Sequence The output states during hard reset are shown in Table 7. Soft Reset The host processor can reset the AR0260 using the two-wire serial interface by writing to SYSCTL 0x001A. SYSCTL 0x001A[0] is used to reset the AR0260 which is similar to external RESET_BAR signal. 1. Set SYSCTL 0x001A[0] to 0x1 to initiate internal reset cycle. 2. Reset SYSCTL 0x001A[0] to 0x0 for normal operation. 3. Delay up to 35 ms, depending on EXTCLK frequency. Figure 6: Soft Reset Operation Notes: 1. This delay is depe ndent on EXTCLK frequency. Table 7: Status of Output Signals During Hard Reset Signal Reset DOUT[7:0] High-Z PIXCLK High-Z LV High-Z FV High-Z DATA_N 0 DATA_P 0 DATA_2N 0 DATA_2P 0 CLK_N 0 CLK_P 0 Table 8: Soft Reset Signal Timing Symbol Parameter Min Typ Max Unit t1 Maximum soft reset time1 –– 3 5 m s EXTCLK SDATA Mode Write soft reset comand Internal boot time Enter standby mode SCLK
AR0260 DS Rev. G Pub. 4/15 EN 14 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Shutdown Mode Shutdown Mode The shutdown mode is entered when the SHUTDOWN pin is asserted. All power to the AR0260 is disabled and no state, register, or patch information is retained. VDD_IO and REG_IN0/VDD_PHY must be powered during Shutdown. Analog power (VAA and VAA_PIX) is optional but typically would also be left on. All pins hold their state (Input, output or tristate) during shutdown. Inputs are ignored during Shutdown and can be high, low or tristate. EXTCLK can be turned off or left running. An internal POR is auto- matically generated on exit from Shutdown. Figure 7: Shutdown Operation Notes: 1. This delay is depend ent on EXTCLK frequency. Table 9: Shutdown Symbol Definition Min Typ Max Unit t1 SHUTDOWN pulse width 50 – – EXTCLK cyclest2 Active EXTCLK required after SHUTDOWN asserted 0 – – t3 Active EXTCLK required before SHUTDOWN de-asserted 0 – – t4 Maximum internal boot time 1 –– 3 5 m s EXTCLK Shutdown SHUTDOWN Mode Internal Boot Time SDATA Enter standy mode All Outputs Data Active
AR0260 DS Rev. G Pub. 4/15 EN 15 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Pixel Data Format Pixel Data Format The AR0260 pixel array is configured as 1928 columns by 1088 rows, (see Figure 8). The dark pixels are optically black and are used internally to monitor black level. There are 1936 columns by 1096 rows of optically active pixels. While the sensor's format is 1920 x 1080, the additional active columns and active rows are included for use when hori- zontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or dark pixels can be read out. Figure 8: Pixel Array Description 8 light dummy + 8 barrier + 51 dark + 4 barrier Dark pixel Barrier pixel Light dummy pixel Active pixel 8 light dummy + 4 barrier 2072 8 light dummy + 4 barrier 8 light dummy +127 dark + 4 barrier 1159 1920 x 1080 (1936 x 1096 active)
AR0260 DS Rev. G Pub. 4/15 EN 19 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Image Data Output Interface 4. If the sensor is reset, any frame in prog ress is aborted immediately and the MIPI sig- nals switch to indicate the ULPS. 5. If the sensor is taken out of the streaming system state and reset_register[4] = 1 (standby end-of-frame), any frame in progress is completed and the MIPI signals switch to indicate the ULPS. If the sensor is taken out of the streaming system state and reset_register[4] = 0 (standby end-of-frame), any frame in progress is aborted as follows: 1. Any long packet in transmission is completed. 2. The end of frame short packet is transmitted. After the frame has been aborted, the MIPI signals switch to indicate the ULPS. Uncompressed Bayer Bypass Output Raw or processed 10-bit Bayer data from the sensor core can be output in bypass mode by: 1. Using both DOUT[7:0] and DOUT_LSB[1:0]. 2. Using only DOUT[7:0] with a special 8 + 2 data format, shown in Table 10. Readout Order The sensor core supports different readout options to modify the image before it is sent to the host system. The readout can be limited to a specific window size of the original pixel array. By changing the readout directions, the image can be flipped in the vertical direction and/or mirrored in the horizontal direction. The image output size is set by programming row and column start and end address variables. When the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed, so that readout starts from the last column address and ends at the first column address. Figure 14 shows a sequence of 3 pixels being read out with normal readout and reverse readout (Bayer8 + 2 mode shown). Table 10: 2-Byte Bayer Format 2-Byte Bayer Format Bits Used Bit Sequence Odd bytes 8 data bits D 9D8D7D6D5D4D3D2 Even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 D 1D0
AR0260 DS Rev. G Pub. 4/15 EN 23 ©Semiconductor Components Industries, LLC,2015. aliasing artifacts that can be a characteristic side effect of subsampling. require sensor window size adjustment when binning is enabled. The effect of binning is shown in Figure 21. Table 11. It is recommended that these registers are configured before streaming images.
AR0260 DS Rev. G Pub. 4/15 EN 24 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Analog Gain Frame Rate Control The formulas for calculating the frame rate of the AR0260 are shown below. The line length is programmed directly in pixel clock periods through register line_length_pck. For a specific window size, the minimum line length can be found in Equation 1: (EQ 1) Note that line_length_pck also needs to meet the minimum line length requirement set by min_line_length_pck. The row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in “Minimum Row Time” on page 24. The frame length is programmed directly in number of lines in the register frame_length_lines. For a specific window size, the minimum frame length can be found in Equation 2: (EQ 2) The frame rate can be calculated from these variables and the pixel clock speed as shown in Equation 3: (EQ 3) If coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. Minimum Row Time The minimum row time and blanking values with default register settings are shown in Table 12. In addition, enough time must be given to the output FIFO so it can output all data at the set frequency within one row time. There are therefore two checks that must all be met when programming line_length_pck: line_length_pck > min_line_length_pck in Table 12. line_length_pck > (x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck in Table 12. Table 12: Minimum Row Time and Blanking Numbers No Row Binning Row Binning min_line_blanking_pck 0x0492 0x07C4 min_line_length_pck 0x05D8 0x09C8 minimum line_length_pck x_addr_end - x_addr_start 1+ = minimum frame_length_lines y_addr_end - y_addr_start 1+ = frame rate 2 cam_sensor_cfg_pixclk
AR0260 DS Rev. G Pub. 4/15 EN 25 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Analog Gain Minimum Frame Time The minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2). Integration Time The integration (exposure) time of the AR0260 is controlled by the fine_integration_time and coarse_integration_time registers. The actual integration time is given by: (EQ 4) The limits for the coarse integration time are defined by: coarse_integration_time > 0 (EQ 5) The limits for the fine integration time are defined by: fine_integration_time_min < fine_integration_time < (line_length_pck – (EQ 6) fine_integration_time_max_margin) Fine Integration Time Limits The limits for the fine_integration_time can be found from fine_integration_time_min and fine_integration_time_max_margin. Values for different mode combinations are shown in Table 14. Table 13: Minimum Frame Blanking Numbers No Row Binning Row Binning min_frame_blanking_lines 0x0051 0x004D Table 14: fine_integration_time Limits No Row Binning Row Binning fine_integration_time_min 0x0336 0x06A4 fine_integration_time_max_margin 0x01BE 0x0322 integration_time coarse_integration_time*line_length_pck fine_integration_time+
AR0260 DS Rev. G Pub. 4/15 EN 26 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor PLL fine_correction For the fine_integration_time limits, the fine_correction constant will change with the binning mode. It is necessary to fine_correction when binning is enabled. The corre- sponding fine_correction values are shown in Table 15. PLL A PLL is provided to create the required PIXCLK from the input EXTCLK. The PLL is programmed through variable settings. Table 15: fine_correction Values No Row Binning Row Binning fine_correction 0x00D4 0x01D9
AR0260 DS Rev. G Pub. 4/15 EN 27 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Digital Processing Chain Digital Processing Chain The AR0260 features a digital processing chain to provide further data path corrections and apply digital gain. Figure 22: Color Bar Test Pattern Test Pattern Example Flat Field R0x3070 = 0x1 100% Color Bars R0x3070 = 0x2 Walking 1s, 8-bit R0x3070=0x0101 Fade-to-Gray Color Bars R0x3070 = 0x3 Walking 1s, 10-bit R0x3070=0x0100
AR0260 DS Rev. G Pub. 4/15 EN 28 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Digital Processing Chain Digital Gain Image stream processing starts with multiplication of all pixel values by a programmable digital gain. Independent color channel digital gain can be adjusted with registers. Adaptive PGA (APGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The AR0260 has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. In some cases, different illuminants can introduce different color shading response. The APGA feature on the AR0260 will compensate for the dependency of the lens shading of the illuminant. The AR0260 will allow for up to three different illuminants to be compen- sated for. Image Scaling and Cropping To ensure that the size of images output by the AR0260 can be tailored to the needs of all users, the IFP includes a scaler module. When enabled, this module performs rescaling of incoming images—shrinks them to arbi trarily selected width and height without reducing the field of view and without discarding any pixel values. By configuring the cropped and output windows to various sizes, different zooming levels including 4X, 2X, and 1X can be achieved. The location of the cropped window is configurable so that panning is also supported. The height and width definitions for the output window must be equal to or smaller than the cropped image. The image crop- ping and scaler module can be used together to implement a digital zoom and pan.
AR0260 DS Rev. G Pub. 4/15 EN 29 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Camera Control and Auto Functions Camera Control and Auto Functions General Purpose I/Os The three general purpose I/Os (GPIOs) of the AR0260 can be configured in multiple ways. Each of the I/Os can be used for multiple purposes and can be programmed from the host. The GPIOs are powered by their own power supply. Hardware Functions Two-Wire Serial Interface The two-wire serial interface bus enables read and write access to control and status registers and variables within the AR0260. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The AR0260 always operates in slave mode. The host (master) gener- ates a clock (S CLK) that is an input to the AR0260 and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements, as follows: 1. a (repeated) start condition 2. a slave address/data direction byte 3. a 16-bit register address (8-bit addresses are not supported) 4. an (a no) acknowledge bit 5. a 16-bit data transfer (8-bit data transfers are not supported) 6. a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a repeated start or restart condition. A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data is transferred serially, 8 bits at a time, with the most significant bit (MSB) trans- mitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. If the S ADDR signal is driven LOW, then addresses used by the AR0260 are R0x090 (write address) and R0x091 (read address). If the SADDR signal is driven HIGH, then addresses used by the AR0260 are R0x0BA (write address) and R0x0BB (read address).
AR0260 DS Rev. G Pub. 4/15 EN 30 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Hardware Functions Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW . As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA low during the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi- nate a read sequence. Stop Condition A stop condition is defined as a LOW -to-HIGH transition on SDATA while SCLK is HIGH. Typical Serial Transfer A typical read or write sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indi- cates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. If the request was a write, the master then transfers the 16-bit register address to which a write should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends acknowledge bit at the end of the sequence. After 8 bits have been transferred, the slave’ s internal register address is automatically incremented, so that the next 8 bits are written to the next register address. The master stops writing by generating a (re)start or stop condition. If the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8- bit transfer. The slave’ s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowl- edge bit. Note: If a customer is using direct memory writes (XDMA), AND the first write ends on an odd address boundary AND the second write starts on an even address boundary AND the first write is not terminated by a STOP , the write data can become corrupted. To avoid this, ensure that a serial write is terminated by a STOP .
AR0260 DS Rev. G Pub. 4/15 EN 33 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Hardware Functions Sequential Write, Start at Random Location This sequence (Figure 28) starts in the same way as the single write to random location (Figure 27). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte writes until L bytes have been written. The write is terminated by the master gener- ating a stop condition. Figure 28: Sequential Write, Start at Random Location Slave Address 0S A Reg Address[15:8] AWrite Data Write Data A Reg Address[7:0] A Write Data Previous Reg Address, N Reg Address, M M+1 M+2 M+1 M+3 A A AWrite Data Write Data M+L-2 M+L-1 M+L A A S
AR0260 DS Rev. G Pub. 4/15 EN 34 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 29: Quantum Efficiency vs. Wavelength 350 550 750 950 1150 QE Wavelength (nm) R Gr Gb B
AR0260 DS Rev. G Pub. 4/15 EN 35 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Chief Ray Angle Chief Ray Angle Table 16: Chief Ray Angle Characteristics Image Height CRA (%) (mm) (deg) 00 0 5 0.077 2.54 10 0.154 5.04 15 0.231 7.52 20 0.308 9.98 25 0.386 12.40 30 0.463 14.76 35 0.540 17.02 40 0.617 19.15 45 0.694 21.12 50 0.771 22.89 55 0.848 24.45 60 0.925 25.78 65 1.002 26.87 70 1.079 27.70 75 1.157 28.28 80 1.234 28.61 85 1.311 28.66 90 1.388 28.43 95 1.465 27.88 100 1.542 26.95 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 CRA (deg) Image Height (%)
AR0260 DS Rev. G Pub. 4/15 EN 36 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor AR0260 sensor is also available in chip scale package (CSP) and this section provides the relevant CSP package details necessary for the optical design of camera system. Table 17: Package Dimension Parameter Symbol Millimeters Inches Nominal Min Max Nominal Min Max Cavity wall + epoxy thickness glass to the wafer bonding top point) Total Ball Count 54 Ball Count X axis N1 9 Ball Count Y axis N2 6 BGA ball center to package center offset in X-direction X 0 -0.025 0.025 0 -0.00098 0.00098 BGA ball center to package center offset in Y-direction Y 0 -0.025 0.025 0 -0.00098 0.00098 BGA ball center to chip center offset in X-direction BGA ball center to chip center offset in Y-direction Edge to Ball Center Distance along X Edge to Ball Center Distance along Y
AR0260 DS Rev. G Pub. 4/15 EN 37 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Figure 30: CSP Mechanical Drawing Notes: 1. TRST_BAR connects to D GND for normal operation. 2. Reserved pins must be left floating. Table 18: Ball Matrix J H G F E D C B A
1 DGND DOUT5D GND DOUT0 GPIO1 LINE_VALID REG_IN0 D GND DGND
2 DGND DOUTT6 D OUT4V DD_IO GPIO0 D GND REG_OUT CLK_P CLK_N
GPIO2 D OUT7 V DD_IO D OUT3D OUT1 FRAME_VALI D REG_FB DATA2_N DATA2_P
4 VDD_IO PIXCLK V DD D OUT2 D GND VDD_IO V DD DATA_N DATA_P
5 SDATA EXTCLK D GND D GND SHUTDOWN A GND D GND V DD_PHY V PP
6 TRST_BAR Reserved S CLK RESET_BAR S ADDR AGND AGND VAA_PIX V AA
CROSS SECTION VIEW (E-E) C B A A First clear active pixel Last clear active pixel S1 J1 S2J2 D Optical Center(-74.7,-212) Package Center=Die Center(0,0) E E TOP VIEW(Image side) BOTTOM VIEW(BGA side) Unit: µm Package size: 6004.55 x 4157.55 Ball pitch: 620 Ball Diameter: 280 BCDEFGHJ ABCDE F G HJ Optical Center(74.7,-212) Package Center=Die Center(0,0) Notch
AR0260 DS Rev. G Pub. 4/15 EN 38 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Electrical Specifications Caution Stresses above those listed in Table 19 may cause permanent damage to the device. Notes: 1. This is a stress rating only, and functional op eration of the device at these or any other conditions above those indicated in the product specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Table 19: Absolute Maximum Ratings Symbol Parameter Rating UnitMin Max VDD_IO_MAX I/O digital voltage –0.3 4.0 V VAA_MAX Analog voltage –0.3 4.0 V VAA_PIX_MAX Analog pixel supply voltage –0.3 4.0 V REG_IN0_MAX Digital supply voltage –0.3 2.4 V VDD_PHY_MAX PHY supply voltage –0.3 2.4 V VIN DC input voltage –0.3 V DD_IO + 0.3 V IIN Transient input current (0.5 sec. duration) – 150 mA TOP Operating temperature (measure at junction) –30 70 °C TSTG
1 Storage temperature –40 85 °C
Table 20: Operating Conditions Symbol Parameter Min Typ Max Units VDD_IO I/O digital voltage 2.5 2.8 3.1 V 1.7 1.8 1.95 V VAA Analog voltage 2.5 2.8 3.1 V VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V REG_IN0 Digital supply voltage 1.7 1.8 1.95 V VDD_PHY PHY supply voltage 1.7 1.8 1.95 V TJ Operating temperature (at junction) –30 55 70 °C Table 21: DC Electrical Characteristics Symbol Parameter Condition Min Max Unit VIH Input HIGH voltage V DD_IO * 0.7 V DD_IO + 0.3 V VIL Input LOW voltage –0.3 V DD_IO * 0.3 V IIN Input leakage current V IN = 0V or VIN = VDD_IO 10 A VOH Output HIGH voltage V DD_IO = 1.8V, IOH = 2mA V DD_IO – 0.3 V VOL Output LOW voltage V DD_IO = 1.8V, IOH = 2mA – 0.4 V
AR0260 DS Rev. G Pub. 4/15 EN 39 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Table 22: Operating Current Consumption (Parallel) Default Setup Conditions: fEXTCLK= 24 Mhz, fPIXCLK = 96 Mhz, VAA = VAA_PIX = VDD_IO = 2.8V, VDD_PHY = REG_IN0 = 1.8V, Tj = 25°C, unless otherwise stated Symbol Parameter Conditions Min Typ Max Unit IAA Analog supply current 1080p Full resolution 30 fps – 57 75 mA 720p, 30 fps – 53 70 mA VGA, 60 fps – 54 71 mA IAA_PIX Pixel supply current 1080p Fu ll resolution 30 fps – 1.7 2.9 mA 720p, 30 fps – 1.2 1.6 mA VGA, 60 fps – 1.6 2.2 mA IREG_IN0 and IDD_PHY Digital and PHY supply currents 1080p Full resolution 30 fps – 52 68 mA 720p, 30 fps – 42 55 mA VGA, 60 fps – 39 51 mA IDD_IO I/O supply current (at 20pF load) 1080p Full resolution 30 fps – 6.4 8.4 mA 720p, 30 fps – 6.3 8.2 mA VGA, 60 fps – 7 9.1 mA Total power consumption 1080p Fu ll resolution 30 fps – 277 360 mW 720p, 30 fps – 245 318 mW VGA, 60 fps – 245 318 mW Table 23: Operating Current Consumption (MIPI) Default Setup Conditions: fEXTCLK= 24 Mhz, fPIXCLK = 96 Mhz, VAA = VAA_PIX = VDD_IO = 2.8V, VDD_PHY = REG_IN0 = 1.8V, Tj = 25°C, unless otherwise stated Symbol Parameter Conditions Min Typ Max Unit IAA Analog supply current 1080p Full resolution 30 fps – 57 75 mA 720p, 30 fps – 53 70 mA VGA, 60 fps – 54 71 mA IAA_PIX Pixel supply current 1080p Fu ll resolution 30 fps – 1.7 2.3 mA 720p, 30 fps – 1.2 1.6 mA VGA, 60 fps – 1.6 2.2 mA IREG_IN0 and IDD_PHY Digital and PHY supply currents 1080p Full resolution 30 fps – 58 75 mA 720p, 30 fps – 47 61 mA VGA, 60 fps – 45 58 mA IDD_IO I/O (non-MIPI) supply current 1080p Full resolution 30 fps – 0.1 0.2 mA 720p, 30 fps – 0.1 0.2 mA VGA, 60 fps – 0.1 0.2 mA Total power consumption 1080p Fu ll resolution 30 fps – 270 351 mW 720p, 30 fps – 236 307 mW VGA, 60 fps – 236 307 mW
AR0260 DS Rev. G Pub. 4/15 EN 40 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Table 24: Non-Operating Current Consumption Default Setup Conditions: fEXTCLK= 24 Mhz, fPIXCLK = 96 Mhz, VAA = VAA_PIX = VDD_IO = 2.8V, VDD_PHY = REG_IN0 = 1.8V, Tj = 25°C, unless otherwise stated Symbol Parameter Conditions Min Typ Max Unit IAA Analog supply current Hard Reset (with EXTCLK) – 12 16 A Hard Reset (without EXTCLK) – 12 16 A Shutdown(with EXTCLK) – 1.0 1.5 A Shutdown(without EXTCLK) – 1.0 1.5 A IAA_PIX Pixel supply current Hard Reset (with EXTCLK) – 0 0 A Hard Reset (without EXTCLK) – 0 0 A Shutdown(with EXTCLK) – 0 0 A Shutdown(without EXTCLK) – 0 0 A IREG_IN0 and IDD_PHY Digital and PHY supply currents Hard Reset (with EXTCLK) – 2.8 3.6 mA Hard Reset (without EXTCLK) – 2.3 3.0 mA Shutdown(with EXTCLK) – 5.0 6.6 A Shutdown(without EXTCLK) – 5.0 6.6 A IDD_IO I/O supply current Hard Reset (with EXTCLK) – 0.2 0.3 mA Hard Reset (without EXTCLK) – 0.2 0.2 mA Shutdown(with EXTCLK) – 1.3 1.8 A Shutdown(without EXTCLK) – 1.3 1.8 A Total power consumption Hard Reset (with EXTCLK) – 5.5 7.2 mW Hard Reset (without EXTCLK) – 4.6 6.0 mW Shutdown(with EXTCLK) – 13 18 W Shutdown(without EXTCLK) – 13 18 W
AR0260 DS Rev. G Pub. 4/15 EN 41 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Notes: 1. V IH/VIL restrictions apply. Table 25: AC Electrical Characteristics EXTCLK = 24 MHz; REG_IN0 = VDD_PHY = 1.8V; VDD_IO = VAA = VAA_PIX = 2.8V; TJ = 25°C unless otherwise stated Symbol Parameter Conditions Min Typ Max Unit Note s fEXTCLK External clock frequency 6 54 MHz 1 DEXTCLK External input clock duty cycle 40 50 60 % tJITTER External input clock jitter – 500 – ps fPIXCLK Pixel clock frequency 6 96 MHz tRPIXCLK Pixel clock rise time C LOAD =2 5 p f – 4 n s tFPIXCLK Pixel clock fall time C LOAD =2 5 p f – 4 n s tPD PIXCLK to data valid – 21 0.1 * tPIXCLK ns tPFH PIXCLK to FV HIGH – 21 0.1 * tPIXCLK ns tPFL PIXCLK to FV LOW – 21 0.1 * tPIXCLK ns tPLH PIXCLK to LV HIGH – 21 0.1 * tPIXCLK ns tPLL PIXCLK to LV LOW – 21 0.1 * tPIXCLK ns PIXCLK slew rate Programmable Slew = 7 V DD_IO = 2.8V, CLOAD = 25pf – 0.83 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.45 – V/ns Programmable Slew = 4 V DD_IO = 2.8V, CLOAD = 25pf – 0.73 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.42 – V/ns Programmable Slew = 0 V DD_IO = 2.8V, CLOAD = 25pf – 0.38 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.26 – V/ns Output slew rate Programmable Slew = 7 V DD_IO = 2.8V, CLOAD = 25pf – 0.70 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.39 – V/ns Programmable Slew = 4 V DD_IO = 2.8V, CLOAD = 25pf – 0.67 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.31 – V/ns Programmable Slew = 0 V DD_IO = 2.8V, CLOAD = 25pf – 0.35 – V/ns VDD_IO = 1.8V, CLOAD = 25pf – 0.16 – V/ns
AR0260 DS Rev. G Pub. 4/15 EN 42 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Figure 31: Parallel Pixel Bus Timing Diagram Notes: 1. FRAME_VALID leads LINE_VALID by 6 PIXCLKs. 2. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. 3. D OUT[7:0], FRAME_VALID, and LINE_VALID are shown with respect to the rising edge of PIXCLK. This feature is programmable and DOUT[7:0], FRAME_VALID, and LINE_VALID can be synchronized to the falling edge of PIXCLK. Table 26: Two-Wire Serial Interface Timing Data Symbol Parameter Conditions Min Typ Max Unit fSCLK Serial interface input clock frequency 100 – 400 kHz tSCLK Serial interface input clock period 2.5 – 10 s SCLK duty cycle 45 50 55 % tr SCLK/SDATA rise time – 65 300 ns tSRTS Start setup time Master write to slave 600 – – tSRTH Start hold time Master write to slave 300 – – ns tSDH SDATA hold Master write to slave 300 – – ns tSDS SDATA setup Master write to slave 300 – – ns tSHAW SDATA hold to ack Master read from slave 150 – – ns tAHSW Ack hold to SDATA Master read from slave 150 – – ns tSTPS Stop setup time Master write to slave 300 – – ns tSTPH Stop hold time Master write to slave 600 – – ns tSHAR SDATA hold to ack Master write to slave 300 – – ns tAHSR Ack hold to SDATA Master write to slave 300 – – ns tSDHR SDATA hold Master read from slave 300 – – ns tSDSR SDATA setup Master read from slave 350 – – ns PIXCLK FRAME_VALID, LINE_VALID tPFL tPLL tPFH tPLH tPD 1 2 DOUT[7:0]
AR0260 DS Rev. G Pub. 4/15 EN 43 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor Electrical Specifications Figure 32: Two-Wire Serial Bus Timing Parameters SCLK SDATA SCLK SDATA Write Start Ack Read Start Ack tSHAR tAHSR tSDHR tSDSR Read Sequence Write Sequence Read Address Bit 7 Read Address Bit 0 Register Value Bit 7 Register Value Bit 0 Write Address Bit 7 Write Address Bit 0 Register Value Bit 7 Register Value Bit 0 tSRTS tSCLK tSDH tSDS tSHAW tAHSW Stop tSTPS tSTPH tSRTH Ack
AR0260 DS Rev. G Pub. 4/15 EN 44 ©Semiconductor Components Industries, LLC,2015. AR0260: 1/6-Inch 1080P High-Definition (HD) Digital Image Sensor MIPI Specification Reference MIPI AC and DC Electrical Characteristics MIPI Specification Reference The AR0260 design and this documentation is based on the following reference docu- ments: MIPI Alliance Standard for CSI-2 version 1.0 MIPI Alliance Standard for D-PHY version 1.0 Table 27: MIPI High-Speed Transmitter DC Characteristics Symbol Parameter Min Typ Max Unit VOD HS transmit differential voltage 140 – 270 mV VCMTX HS transmit static common mode voltage 150 – 250 mV VOD VOD mismatch when output is Differential-1 or Differential-0 – – 13 mV VCMTX(1,0) VCMTX mismatch when output is Differential-1 or Differential-0 – – 5 mV VOHHSH S o u t p u t H I G H v o l t a g e – – 3 6 0 m V ZOS Single-ended output impedance 40 – 62.5 ZOS Single-ended output impedance mismatch – – 17 % Table 28: MIPI High-Speed Transmitter AC Characteristics Symbol Parameter Min Typ Max Unit Data bit rate – – 768 Mb/s trise 20–80% rise time 150 – 500 ps tfall 20–80% fall time 150 – 500 ps Table 29: MIPI Low-Power Tran smitter DC Characteristics Symbol Parameter Min Typ Max Unit VOL Thevenin output low level – – 55 mV VOH Thevenin output high level 1.1 1.15 1.3 V ZOLP Output impedance of LP transmitter 110 – – Table 30: MIPI Low-Power Transmitter AC Characteristics Symbol Parameter Min Typ Max Unit trise 15–85% rise time – – 25 ns tfall 15–85% fall time – – 25 ns Slew Slew rate (C LOAD 5–20pf) – – 200 mV/ns Slew Slew rate ( CLOAD 20–70pf) – – 150 mV/ns
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Revision History
AR0260 DS Rev. G Pub. 4/15 EN 45 ©Semiconductor Components Industries, LLC,2015 . Updated “Ordering Information” on page 2 Removed Confidential marking Updated Table of Contents to new format Updated to ON Semiconductor template Updated Table 2, “ Available Part Numbers,” on page 1 Updated to Production Updated Table 2, “ Available Part Numbers,” on page 1 Updated Table 3, “Pin Descriptions,” on page 9 Updated Table 22, “Operating Current Consumption (Parallel),” on page 39 Updated Table 23, “Operating Current Consumption (MIPI),” on page 39 Updated Table 24, “Non-Operating Current Consumption,” on page 40 Updated Table 25, “ AC Electrical Characteristics,” on page 41 Updated Table 32, “Two-Wire Serial Bus Timing Parameters,” on page 43 Updated Table 27, “MIPI High-Speed Tran smitter DC Characteristics,” on page 44 Updated Table 28, “MIPI High-Speed Tran smitter AC Characteristics,” on page 44 Updated Table 29, “MIPI Low-Power Tran smitter DC Characteristics,” on page 44 Updated Table 30, “MIPI Low-Power Tran smitter AC Characteristics,” on page 44 Updated to Preliminary Updated Table 1: “Key Parameters,” on page 1 Updated “Shutdown Mode” on page 14 Removed “Soft Standby” Updated Table 11, “Recommended Sensor Analog Gain Tables,” on page 23 Added “fine_correction” on page 26 Removed “One-Time Programmable Memory” Updated Table 20, “Operating Conditions,” on page 38 Updated Table 21, “DC Electric al Characteristics,” on page 38 Updated Table 22, “Operating Current Consumption (Parallel),” on page 39 Updated Table 23, “Operating Current Consumption (MIPI),” on page 39 I n i t i a l r e l e a s e