AS21P2THB STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Pin settings
- 2 Logic diagram
- 3 Dedicated port charging detecti on
- 4 Maximum rating
- 4.1 Recommended operating conditions
- 5 Electrical characteristics
- 6 Test circuit
- 7 Package mechanical data
- 8 Revision history
Features
Ultra low power dissipation: –I CC = 1 A (max.) at TA = 85 °C Low “ON” resistance: –R ON = 4.8 (TA = 25 °C) at VCC = 4.3 V –R ON = 5.9 (TA = 25 °C) at VCC = 3.0 V Wide operating voltage range: –V CC (opr.) = 1.65 V to 4.3 V 4.3 V tolerant and 1.8 V compatible threshold on digital control input at VCC = 2.3 V to 3.0 V Typical bandwidth (-3 dB) at 800 MHz on all channels USB (2.0) high speed (480 Mbps) signal switching compliant Integrated fail safe function Interrupt function to indicate to the processor that the device is in dedicated port charging mode Latch-up performance exceeds 500 mA per JESD 78, Class II ESD performance exceeds JESD22: – Dn pins: 4000-V human body model (A114- – All other pins: 2000-V human body model (A114-A)
Applications
Wearable Sport and fitness Portable equipment
Description
The AS21P2THB is a high-speed CMOS low voltage dual analog SPDT (single pole double throw) switch or 2:1 multiplexer/demultiplexer switch fabricated in silicon gate C²MOS technology. It is designed to operate from 1.65 V to 4.3 V, thus making this device the ideal selection for portable applications. The SEL input is provided to control the switch. The switch nS1 is ON (connected to common ports Dn) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low, the switch nS2 is ON (it is connected to common port Dn) when the SEL input is held low and OFF (high impedance state exists between the two ports) when SEL is held high. AS21P2THB has an integrated fail safe function to withstand over-voltage condition when the device is powered off. The AS21P2THB also has an interrupt pin which sends a signal to the processor when the device is in dedicated port charging mode. Additional key features are fast switching speed, break-before- make-delay time and ultralow power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. QFN10 (1.8 x 1.4 mm) Table 1. Device summary
1 Pin settings
Figure 1. Pin connection (top through view) Table 2. Pin description
1 INT Interrupt
2 VCC Positive supply voltage
3 SEL Control
6 D2 Common channel for switch 2
7 GND Ground (0 V)
8 D1 Common channel for switch 1
2 Logic diagram
Figure 2. Logic block diagram Figure 3. Logic equivalent circuit Table 3. Truth table
3 Dedicated port charging detection
dedicated port charging mode. Figure 4. Interrupt function logic representation
4 Maximum rating
extended periods may affect device reliability.
- Derate above 70 °C by 18.5 mW/°C.
4.1 Recommended operating conditions
Table 4. Absolute maximum ratings Table 5. Recommended operating conditions
5 Electrical characteristics
Table 6. DC specifications
3.0 VS = 3 V
- Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges. Table 6. DC specifications (continued)
Table 7. AC characteristics (CL = 35 pf, RL: 50 , TR = Tf 5 ns)
Table 8. AC electrical characteristics (CL = 5 pF, RL = 50 , TA = 25 °C)
- Off isolation = 20 Log10 (V D/VS), VD = output, VS = input to off switch.
Table 9. USB related AC electrical characteristics
6 Test circuit
Figure 5. ON resistance
Figure 10. Test circuit
- C L = 5/35 pF or equivalent (includes jig and probe capacitance)
- R T =Z OUT of pulse generator (typically 50 )
7 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
8 Revision history
Table 11. Document revision history 07-Mar-2014 1 Initial release.