AS0142AT ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Latest 3.0 /C0109m pixel with ON Semiconductor DR−Pix™ technology
- Superior Low−light Performance
- 45 fps at 1.0 MP, 60 fps at 720p
- Linear or High Dynamic Range Video
- Color Processing Optimized for HDR Video Operation
- Color and Gamma Correction
- Auto Exposure, Auto White Balance, 50/60 Hz Auto Flicker Detection and Avoidance
- Adaptive Local Tone Mapping (ALTM)
- Programmable Spatial Transform Engine (STE)
- Pre−rendered Graphical Overlay ♦ Line and Arc support ♦ 191 characters from UTF−8/Unicode ♦ 64 user−defined characters
- Two−wire Serial Programming Interface (CCIS)
- Parallel output, OpenLDI to directly drive displays
- Supports 1−clock or 2−clocks per pixel output modes
- Interface to low−cost Flash or EEPROM through SPI bus (to configure and load patches, etc.)
- High−level host command interface
- Standalone operation supported
- Up to 7 GPIO
- Fail−safe IO
- Multi−Camera synchronization support
Applications
- Automotive ADAS
- Automotive surround and rear−view
- ADAS + Viewing Fusion
- High dynamic range imaging
- Mirror Replacement (CMS)
Table 1. KEY PARAMETERS
125 MHz (Note 2)
- Maximum frame rates depend on output interface and data for-
- Maximum pixel clock rates depend on IO voltage. Please see ta-
- Excluding VDDIO (Host) and VDDIO (Sensor)
herein are subject to change without notice.
ORDERING INFORMATION
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Table 2. ORDERING INFORMATION
Figure 3. Typical Parallel Configuration (Legacy Mode) @ AS0142AT Internal Regulator
- Minimum “Bypass Capacitor Set” recommendation
- ON Semiconductor recommends a 1.5 k/C0087 resistor value for the two−wire serial interface RPULL-UP. However, greater values may
be used for slower two−wire serial transmission speed.
- RESET_BAR has an internal pull−up resistor and can be left floating if not used.
- The decoupling capacitors for the regulator input and output should have a value of 1.0 /C0109F and 0.1 uF each. The capacitors should
be ceramic and need to have X5R or X7R dielectric.
- PU_1 & PD_1 connection are mandatory; PD_2 are strongly recommended.
- Decoupling capacitors for each power supply should be mounted as close as possible to the supply pin(s). Actual values and
numbers may vary, depending on layout and design consideration.
- The diagram is showing typical parallel configuration. If Crossbar mode is used, the 27 parallel outputs can be assigned to any
output pad. Refer to crossbar section for more details.
- Contact ON Semiconductor for case of “VDD_1V2” being supplied by external voltage source.
Co−Processor, via stream settings command. higher temperature applications. Figure 4. Using a Crystal Instead of an External PCB_EXTCLK) and C2' = (C2 + COUT + PCB_XTAL).
Table 3. PINOUT DESCRIPTION
- Sense Line embedded VDD_1V2 Supply A11, A12, B11 3 • Host Digital Core Supply, 1.2V nominal AGND Supply – GND H11, H12, J11, J12, K11, K12 6 • Analog related Stack Chip Ground DGND Supply − GND D4 to D9, E4 to E9, F4 to F9, G4 to G9, H4 to H9, J4 to J9 36 • Digital related Stack Chip Ground Host Regu- lator Con- trol ENLDO Input B9 1 • Host Regulator enable (REG_1V8 domain) EXT_REG Input A8 1 • External Supply enable (VDD_1V2 domain) Master Clock EXTCLK Input C8 1 • This can either be a square−wave generated from an oscillator (in which case the XTAL input must be left unconnected), or direct connection to a crystal XTAL Output B7 1 • If EXTCLK is connected to one pin of a crystal, the other pin of the crystal is connected to XTAL pin; otherwise this signal must be left unconnected.
- Pin with Internal Pull Up Resistor
- When no SPI device detected, the logic state of this pin decides whether AS0142AT should perform Auto−Configure ♦ 0: Do not Auto−Configure; Two−wire interface will be used to configure the device (i.e. Host−Configure mode) ♦ 1: Auto−Configure SPI_SDO Output L3 1 • Data out to SPI flash or EEPROM memory Two Wired SCLK Input G1 1 • Host two−wire serial clock
- Recommended 1.5 k/C0087 to 1V8/2V8/3V3_IO SDATA I/O K2 1 • Host two−wire serial data
- Recommended 1.5 k/C0087 to 1V8/2V8/3V3_IO General Purpose I/O GPIO[6:1] I/O L2, J2, K6, L7, K4, 6 • Configurable Host I/O interface Inactive Control RESET_BAR Input F2 1 • Hard Reset Control, Active Low
- No Hardware State Retention
- Pin with Internal Pull Up Resistor STANDBY Input H3 1 • Hard Standby Control, Active High
- Hardware State Retention possible Two Wire Address Definition SADDR Input K3 1 • Selects device address for the two−wire slave serial interface ♦ When connected to GND the device ID is 0x90 ♦ When wired to 1V8/2V8/3V3_IO, the device ID is 0xBA
- There is an option to allow META_LINE_VALID to be reflected in LINE_VALID DOUT[23:0] Output K9, M9, K10, H10, K7, J10, G11, G10, F11, F10, E11, E10, D10, C10, B10, D11, B8, C12, C9, C7, C11, A10, A7, 24 • Host pixel data output (synchronous to PIXCLK) FRAME_SYNC Input K8 1 • Pass through to TRIGGER_OUT
- This signal should be connected to GND if not used TRIGGER_OUT Output L11 1 • Host Trigger signal to embedded image sensor FLASH Output H1 1 • External Flash Light Control Output Special Pins NC DO NOT CONNECT B3, C2, C4, D1, D2, L1, M1 to M7, M11 14 • ON Internal Monitor Function Only Reserved DO NOT CONNECT G12 1 • ON Internal Debug Only PU_1 I/O F1, G2 2 • Embedded Image Sensor Two−Wires Pins (for Stack Chip internal communication)
- Recommended 1.5 K/C0087 to 1V8_IO PD_1 I/O B12, E1, E2, J3, L6, L9, L12 7 • Must be at Logic Low for proper Stack Chip Operation
- Recommended 10 K/C0087 to GND PD_2 I/O H2, J1, K1, M12 4 • Pull down to GND for proper Stack Chip Operation
- Recommended 1 K/C0087 to GND
Table 4. PACKAGE PINOUT AS0142AT internal regulator. Table 5. AS0142AT REGULATOR MODE CONFIGURATION
a power−on reset feature that initiates a reset upon power up. Figure 5. Power−Up and Power−Down Sequence (AS0142AT Internal Regulator Mode)
- When using XTAL the setting should be taken into account.
- RESET_BAR can be either @ 1V8/2V8/3V3_IO or GND at power−up.
Table 6. POWER−UP AND POWER−DOWN SIGNAL TIMING (AS0142AT INTERNAL REGULATOR MODE)
- A hard reset is issued by toggling the RESET_BAR signal
- A soft reset is issued by writing commands through the two−wire serial interface
- An internal power−on reset Table 7 shows the output states when the part is in various states.
Table 7. OUTPUT STATES Driven if used Driven if used Driven if used Driven if used Input/ Output.
state. AS0142AT settings will not be preserved. Figure 6. Hard Reset Operation Table 8. HARD RESET writing to a register through the two−wire serial interface. AS0142A T settings will not be preserved.
Figure 7. Hard Standby Operation Table 9. HARD STANDBY SIGNAL TIMING writing to a register through the two−wire serial interface. AS0142A T settings could be preserved. Config, Auto Config, and Host Config.
- If a device is detected, the firmware switches to the Flash−Config mode.
- If no device is detected, the firmware then samples the SPI_SDI pin state to determine the next mode: ♦ If SPI_SDI is low, then it enters the Host−Config mode. ♦ If SPI_SDI is high, then it enters the Auto−Config mode. In the Flash Config mode, the firmware interrogates the device to determine if it contains valid configuration records:
- If no records are detected, then the firmware enters the Host Config mode.
- If records are detected, the firmware processes them. By default, when all Flash records are processed the firmware switches to the Host−Config mode. However, the records encoded into the Flash can optionally be used to instruct the firmware to proceed to Auto Config, or to start streaming (via a Change−Config). In the Host Config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. The System Configuration phase is effectively complete and the AS0142AT will take no actions until the host issues commands. USAGE MODES How a camera based on the AS0142AT will be configured depends on what features are used. In the simplest case, an AS0142A T operating in Auto −Config mode with no customized settings might be sufficient. A back−up camera with dynamic input from the steering system will require a /C0109C with a system bus interface. Flash sizes supported up to 2 GB. The two−wire bus is adequate since only high−level commands are used. In the simplest case no EEPROM or Flash memory or /C0109C is required, as shown in Figure 8.
www.onsemi.com ADACD (ADAPTIVE COLOR DIFFERENCE) The next step in the image stream process is noise reduction. The AS0142AT uses a noise reduction filter called AdaCD which focuses on removing color noise while preserving edge details. Automotive applications require good performance in extremely low light , even at high temperature conditions. In these stringent conditions the image sensor is prone to higher noise levels. Efficient noise reduction techniques are required to circumvent this sensor limitation and deliver a high quality image. BLACK LEVEL SUBTRACTION AND DIGITAL GAIN After noise reduction, the pixel data goes through black level subtraction and multiplication by a programmable digital gain . This digital gain can be programmed independently per color channel registers. Black level subtraction (to compensate for sensor data pedestal) is a single value applied to all color channels. If the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. POSITIONAL GAIN ADJUSTMENTS (PGA) Lens has tendency to produce images whose brightness is significantly attenuated near the edges . On top of other factors causing fixed pattern signal gradients in images captured by image sensors, image shading occurs . The AS0142A T has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. THE CORRECTION FUNCTION The correction functions can then be applied to each pixel value to equalize the response across the image as per following relation: Pcorrected(row, col) /C0043Psensor(row, col)/C0032f(row, col) (eq. 1) where P is the pixel value and f is the color dependent correction functions for each color channel. ADAPTIVE LOCAL TONE MAPPING (ALTM) Real world scenes often have very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest object in a scene. In recent years many technologies have been developed to capture the full dynamic range of real world scenes. For example, the multiple exposure method is widely adopted for capturing high dynamic range images, which combines a series of low dynamic range images of the same scene taken under different exposure times into a single HDR image. Even though the new digital imaging technology enables the capture of the full dynamic range, low dynamic range display devices can be the limiting factor. Typical LCD monitor nowaday has contrast ratio around 1,000:1 which is not enough for an HDR image (the contrast ratio for an HDR image is around 250,000:1). Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. Tone mapping methods can be classified into global tone mapping and local tone mapping. Global tone mapping methods apply the same mapping function to all pixels. While global tone mapping methods provide computationally simple and easy to use solutions, they often cause loss of contrast and detail. A local tone mapping is thus necessary in addition to global tone mapping , for the reproduction of visually higher appealing images that could reveal scene details which are important for automotive safety and surveillance applications. Local tone mapping methods use a spatially variable mapping function determined by the neighborhood of a pixel, which allows it to increase the local contrast and the visibility of some details of the image. Local methods usually yield more pleasing results because they exploit the fact that human vision is more sensitive to local contrast. ON Semiconductor’s ALTM solution significantly improves the performance over global tone mapping. ALTM is directly applied to the Bayer domain to compress the dynamic range from 20 -bit to 12 −bit. This allows the regular color pipeline to be used for HDR image rendering. COLOR INTERPOLATION In the raw data stream fed by the embedded sensor to the IFP, each pixel is represented by a 20 − or 12 −bit integer number, which can be considered proportional to the pixel’s response to a one−color light stimulus, red, green, or blue, depending on the pixel’s position under the color filter array. Initial data processing steps , up to and including ALTM, preserve the one−color−per−pixel nature of the data stream, but after ALTM it must be converted to a three−colors−per−pixel stream appropriate for standard color processing. The conversion is done by an edge sensitive color interpolation module. The module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. The algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas . The edge threshold can be set through register settings. COLOR CORRECTION AND APERTURE CORRECTION To achieve good color fidelity of the IFP output , interpolated RGB values of all pixels are subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x 3 color correction matrix . The three components of the resulting color vector are all sums of three 10−bit numbers. The color correction matrix (CCM) can be either programmed by the user or automatically selected by the auto white balance (AWB) algorithm implemented in the IFP. Color correction should ideally produce output colors that are corrected for the spectral sensitivity and color
adjusted through register settings. correction can be defined through register settings. method is for the host to program the 33 knee point curve. in extreme low light conditions. difference between their luminance and the threshold. sensor and color pipeline to achieve the desired exposure. windows organized as a 5 x 5 grid. Figure 12. 5 x 5 Grid
switched in/out; this option adds cost to the camera system. AS0142A T developer guide for details. applied to all slaves concurrently under host control. and blue gains to compensate. the slaves, and all changes are then applied at the same time. appropriate integration times and gains. control over exposure and gains.
50 Hz or 60 Hz, which emit light with alternating inverted
is designed only to detect a 50Hz or 60Hz flicker source. an 8− to 24−bit word over one or two clocks. Table 10. YCbCr OUTPUT DATA ORDERING
Table 11. YCbCr OUTPUT MODES (Default mode; CAM_PORT_PARALLEL_MSB_ALIGN = 0x1) NOTE: Odd means first cycle; even means second cycle . Table 12. YCbCr OUTPUT MODES (Default mode; CAM_PORT_PARALLEL_MSB_ALIGN = 0x0)
Figure 13. 8−bit YCbCr Output (YCbCr_422_8_8)
- CAM_PORT_PARALLEL_MSB_ALIGN = 0x0
Figure 14. 10−bit YCbCr Output (YCbCr_422_10_10)
- CAM_PORT_PARALLEL_MSB_ALIGN = 0x0
Figure 15. 16−bit YCbCr Output (YCbCr_422_16)
- CAM_PORT_PARALLEL_MSB_ALIGN = 0x0
Figure 16. 20−bit YCbCr Output (YCbCr_422_20)
- CAM_PORT_PARALLEL_MSB_ALIGN = 0x0
The AS0142AT supports progressive CCIR656 mode. Figure 17. CCIR656 (Progressive) Output Table 13. RGB888 OUTPUT MODES (CAM_PORT_PARALLEL_MSB_ALIGN = 0x01) NOTE: Odd means first cycle; even means second cycle . Table 14. RGB888 OUTPUT MODES (CAM_PORT_PARALLEL_MSB_ALIGN = 0x0)
Figure 18. 24−bit RGB888 Output
Figure 19. 12+12−bit RGB888 Output Table 15. RGB565OUTPUT MODES (cam_port_parallel_msb_align=0x01) NOTE: Odd means first cycle; even means second cycle . Table 16. RGB565 OUTPUT MODES (cam_port_parallel_msb_align=0x0)
Figure 20. RGB565_16
Figure 21. RGB565_8_8
Table 17. ALTM BAYER OUTPUT MODES register setting to obtain MSB−aligned data as well. Table 18. 12−bit BAYER OUTPUT MODE Table 19. 14−bit BAYER OUTPUT MODE Table 20. 16−bit BAYER OUTPUT MODE Table 21. 20−bit BAYER OUTPUT MODE was captured, e.g. mean values, intensity histograms, etc. signal may even be assigned to multiple outputs at once. feature affords a large amount of flexibility for the customer. minimize crossovers and optimize routing paths.
least a noticeable amount of barrel distortion. magnification the further away from the optical axis. the image so that the resulting distortion is much smaller. visibility by virtually elevating the point of viewing objects. Figure 22. Vertical Perspective Adjustment
viewing at a junction is required. Figure 27. Multi−Panel The AS0142AT supports graphic overlays. can be defined for each layer. easier and are therefore more useful for dynamic overlays. as circle segments and can be linked to create general curves. Again these are useful for dynamic overlays. These will be 32x32 in size.
access to control and status registers within the AS0142AT. a master controls one or more slave devices.
- A start or restart condition
- A slave address/data direction byte
- A 16−bit register address
- An acknowledge or a no−acknowledge bit
- Data bytes
- A stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xBA . See Table 22 below . The user can change the slave address by changing a register value.
Table 22. TWO−WIRE INTERFACE ID ADDRESS “repeated start” or “restart” condition. low and must be stable while SCLK is HIGH. the two−wire serial interface specification. is LOW and must be stable while SCLK is HIGH. on SDATA while SCLK is HIGH. 16−bit register address to which a WRITE will take place.
requirements. The maximum supported device size is 2 Gb. commands for later execution. Table 23. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
Table 24. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Internal Regulator) Figure 34. I/O Timing Diagram Table 25. I/O TIMING CHARACTERISTICS − PARALLEL MODE (1V8/2V3/3V3 @ 2.8V) (Notes 4 and 5)
- Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
- Max PIXCLK frequency varies with IO voltage. Refer to Table 29, “Output Clocks,” for details.
Table 26. I/O TIMING CHARACTERISTICS − PARALLEL MODE (1V8/2V8/3V3 @ 1.8 V) (Notes 7 and 8)
- Jitter from PIXCLK_OUT is already taken into account in the data for all of the output parameters.
Table 27. DC ELECTRICAL CHARACTERISTICS
- VIL and VIH have min/max limitations specified by absolute ratings.
10.Excludes pins that have internal PU resistors.
- Excludes power pins and pins that cannot be Tri−State (e.g. XTAL pin).
Table 28. INPUT CLOCKS 20-29 MHz, otherwise 10-29 MHz. Table 29. Output Clocks PIXCLK 18 74.25/25 80/125 Clock of parallel output bus. If pad voltage is 1.8 V nominal, then max frequency is 80 MHz. If pad voltage is 3.3V, then the max frequency is 125Mhz. SPI_SCLK 1.2 20 SPI clock to nonvolatile external memory.
Figure 35. FRAME_SYNC (Operation) Diagram Table 30. TRIGGER TIMING
Table 31. STANDBY CURRENT CONSUMPTION Table 32. INRUSH CURRENT Table 33. OPERATING CURRENT CONSUMPTION − STE AND OVERLAY BOTH ON
Table 34. OPERATING CURRENT CONSUMPTION − STE ON AND OVERLAY OFF Table 35. OPERATING CURRENT CONSUMPTION − STE AND OVERLAY BOTH OFF
Figure 36. Slave Two Wire Serial Bus Timing Parameters (CCIS) Table 36. SLAVE TWO−WIRE SERIAL BUS CHARACTERISTICS (CCIS) 12.All values referred to VIHmin = 0.9 * 1V8/2V8/3V3_IO and VILmax = 0.1 * 1V8/2V8/3V3_IO levels. 13.A device must internally provide a hold time of at least 300 nS for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 14.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 15.Cb = total capacitance of one bus line in pF.
www.onsemi.com PACKAGE DIMENSIONS IBGA143 8.5x8.5 CASE 503BH ISSUE O
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