ARMV5TE

LPC2921 PHILIPS | Alldatasheet

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DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA 1. General description The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller, CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, communication, and automotive markets. To optimize system power consumption, the LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features „ ARM968E-S processor running at frequencies of up to 125 MHz maximum. „ Multilayer AHB system bus at 125 MHz with four separate layers. „ On-chip memory: ‹ Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data TCM (DTCM). ‹ On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each. ‹ On the LPC2923 and LPC2921, one 16 kB SRAM block. ‹ 8 kB ETB SRAM, also usable for code execution and data. ‹ Up to 512 kB high-speed flash-program memory. ‹ 16 kB true EEPROM, byte-erasable/programmable. „ Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can be used with both I2C interfaces, the SPI interfaces, and the UARTs, as well as for memory-to-memory transfers including the TCM memories. „ Serial interfaces: ‹ USB 2.0 full-speed device controller with dedicated DMA controller and on-chip device PHY. ‹ Two-channel CAN controller supporting Full-CAN and extensive message filtering. ‹ Two LIN master controllers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces. ‹ Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485 (9-bit) support. ‹ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO. ‹ Two I 2C-bus interfaces. LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB device Rev. 00.01 — 24 October 2008 Preliminary data sheet

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 2 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN „ Other peripherals: ‹ Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8 analog inputs each with conversion times as low as 2.44 μs per channel. Each channel provides a compare function to minimize interrupts. ‹ Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external signal input. ‹ Four 32-bit timers each containing four capture-and-compare registers linked to I/Os. ‹ Four six-channel PWMs (Pulse-Width Modulators) with capture and trap functionality. ‹ Two dedicated 32-bit timers to schedule and synchronize PWM and ADC. ‹ Quadrature encoder interface that can monitor one external quadrature encoder. ‹ 32-bit watchdog with timer change protection, running on safe clock. „ Up to 60 general-purpose I/O pins with programmable pull-up, pull-down, or bus keeper. „ Vectored Interrupt Controller (VIC) with 16 priority levels. „ Up to 16 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up features. „ Configurable clock-out pin for driving external system clocks. „ Processor wake-up from power-down via external interrupt pins; CAN or LIN activity. „ Flexible Reset Generator Unit (RGU) able to control resets of individual modules. „ Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual modules: ‹ On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring. ‹ On-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz. PLL input range 10 MHz to 25 MHz. ‹ On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz. ‹ Generation of up to 11 base clocks. ‹ Seven fractional dividers. „ Second, dedicated CGU with its own PLL generates the USB clock and a configurable clock output. „ Highly configurable system Power Management Unit (PMU): ‹ clock control of individual modules. ‹ allows minimization of system operating power consumption in any configuration. „ Standard ARM test and debug interface with real-time in-circuit emulator. „ Boundary-scan test supported. „ ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for application code and data storage. „ Dual power supply: ‹ CPU operating voltage: 1.8 V ± 5% . ‹ I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V. „ 100-pin LQFP package. „ −40 °C to +85 °C ambient operating temperature range.

3.1 Ordering options

Table 1. Ordering information Table 2. Part options

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 4 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN 4. Block diagram Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2921/2923/2925 block diagram 002aae224 ARM968E-S DTCM 16 kB ITCM 16 kB TEST/DEBUG INTERFACE slave master 1 master 2 slaves master GPDMA CONTROLLER GPDMA REGISTERS EMBEDDED FLASH 512/256/128 kB 16 kB EEPROM EMBEDDED SRAM 16 kB (LPC2925 only) SYSTEM CONTROL TIMER0/1 MTMR CAN0/1 GLOBAL ACCEPTANCE FILTER PWM0/1/2/3

3.3 V ADC1/2

power. clock, and reset subsystem MSC subsystem networking subsystem peripheral subsystem

5.1 Pinning

5.2 Pin description

5.2.1 General description

shown in the pin description tables in this section.

5.2.2 LQFP100 pin assignment

Table 3. LQFP100 pin assignment

Table 3. LQFP100 pin assignment …continued

boundary scan and flash programming; pulled up internally.

[3] Analog Pad; Analog Input Output.

6.1 Architectural overview

• An ARM968E-S processor with real-time emulation support
• An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers
• Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem).
• Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems.
• One ARM Peripheral Bus for event router and system control. The LPC2921/2923/2925 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place. Completion of a second write to the same subsystem will not be executed until the first write is finished.

6.2 ARM968E-S processor

• Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces P0[23]/IN2[7]/ PMAT2[5]/A19 99[4] GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 - TDI 100[1] IEEE 1149.1 data in, pulled up internally

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 10 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

• Write buffers for the AHB and TCM buses
• Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed- point DSP instructions to accelerate signal-processing algorithms and applications. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline architecture. Typically, in a three-stage pipeline architecture, while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory. In the five-stage pipeline additional stages are added for memory access and write-back cycles. The ARM968E-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions or to applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM968E-S processor has two instruction sets:
• Standard 32-bit ARMv5TE set
• 16-bit THUMB set The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit controller using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM controller connected to a 16-bit memory system. The ARM968E-S processor is described in detail in the ARM968E-S data sheet Ref. 2

6.3 On-chip flash memory system

The LPC2921/2923/2925 includes a 128 kB, 256 kB, or 512 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated on the LPC2921/2923/2925.

6.4 On-chip static RAM

In addition to the two 16 kB TCMs, the LPC2921/2923/2925 includes up two static RAM memories of 16 kB each for a total of 32 kB (LPC2925 only) or 1 block of 16 kB (LPC2921/2923). Both may be used for code and/or data storage. The 8 kB SRAM block for the ETB can be used as static memory for code and data storage as well. However, DMA access to this memory region is not supported.

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 11 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.5 Memory map

Fig 3. LPC2921/2923/2925 memory map reserved DMA interface to TCM PCR/VIC control 0x0000 00000 GB 1 GB 4 GB 2 GB 0x4000 0000 0x2000 0000 0x8000 0000 0x8000 4000 0x8000 8000 0x8000 C000 0xE000 0000 0xE002 0000 0xE004 0000 0xE006 0000 0xE008 0000 0xE00A 0000 0xE00C 0000 0xE00E 0000 0xE010 0000 0xE014 0000 0xE018 3000 0xF000 0000 0xF080 0000 0xFFFF 8000 0xFFFF FFFF reserved reserved reserved reserved reserved reserved reserved peripheral subsystem #0 peripheral subsystem #2 peripheral subsystem #4 peripheral subsystem #6 0xE018 2000 0xE018 0000 16 kB AHB SRAM 16 kB AHB SRAM (LPC2925 only) reserved USB controller DMA controller 8 kB ETB SRAM ETB control reserved ITCM/DTCM on-chip flash 0x2020 4000 0x0000 0000 0x0040 0000 0x0000 4000 0x0040 4000 0x0080 0000 0x2000 0000 16 kB ITCM 16 kB DTCM reserved reserved no physical memory peripherals #6 MSCSS subsystem ITCM/DTCM memory peripherals #2 peripheral subsystem 0xE004 1000 0xE004 2000 0xE004 3000 0xE004 4000 0xE004 6000 0xE004 8000 0xE004 A000 0xE004 B000 0xE004 F000 0xE005 0000 0xE006 0000 0xE004 C000 0xE004 9000 0xE004 7000 0xE004 5000 0xE004 0000 SPI0 WDT TIMER0 TIMER1 TIMER2 TIMER3 UART0 UART1 SPI1 SPI2 GPIO0 GPIO1 reserved reserved peripherals #0 general subsystem 0xE000 1000 0xE000 2000 0xE000 2000 0xE002 0000 0xE000 0000CFID SCU event router peripherals #4 networking subsystem 0xE008 1000 0xE008 0000CAN0 CAN1 0xE008 2000 0xE008 3000 0xE008 4000 0xE008 7000 0xE008 9000 0xE008 B000 0xE00A 0000 0xE008 A000 0xE008 8000 0xE008 6000 I2C0 I2C1 reserved CAN ID LUT CAN common regs LIN0 LIN1 CAN AF regs 0xE00C 0000 0xE00C 1000 0xE00C 2000 0xE00C 3000 0xE00C 4000 0xE00C 5000 0xE00C 6000 0xE00C 7000 0xE00C 8000 0xE00C 9000 0xE00C A000 0xE00E 0000 reserved ADC1 ADC2 PWM0 PWM1 PWM3 quadrature encoder PWM2 MSCSS timer0 MSCSS timer1 PCR/VIC subsystem 0xFFFF 8000 0xFFFF 9000 0xFFFF A000 0xFFFF B000 0xFFFF C000 0xFFFF F000 0xFFFF FFFF PMU CGU1 reserved reserved reserved GPIO5 reserved VIC CGU0 RGU

512 MB shadow area

6.6 Reset, debug, test, and power description

6.6.1 Reset and power-up behavior

reached a stable state. See Section 8 for trip levels of the internal power-up reset circuit1. running at LP_OSC speed is too low for the external debugging environment.

6.6.2 Reset strategy

monitoring functions needed for tracing a reset back to source.

1. Only for 1.8 V power sources

Table 4. Reset pin Table 5. IEEE 1149.1 boundary-scan test and debug interface

6.6.3.1 ETM/ETB

trace data produced by the ETM.

• Closely tracks the instructions that the ARM core is executing.
• On-chip trace data storage (ETB).
• All registers are programmed through JTAG interface.
• Does not consume power when trace is not being used.
• THUMB/Java instruction set support.

6.6.4 Power supply pins

Table 6 shows the power supply pins.

6.7 Clocking strategy

6.7.1 Clock architecture

unrelated in frequency and phase and can have different clock sources within the CGU. for an overview of the clock areas within the device. more details of clock and power control within the device. the base clock for the USB controller and one base clock for an independent clock output. Table 6. Power supply pins

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 14 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.7.2 Base clock and branch clock relationship

Table 7 contains an overview of all the base blocks in the LPC2921/2923/2925 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should not be switched off. See Section 6.15.5 for more details of how to control the individual branch clocks. Fig 4. LPC2921/2923/2925 overview of clock areas TIMER0/1 MTMR PWM0/1/2/3 ADC1/2 QEI modulation and sampling control subsystem BASE_MSCSS_CLK branch clocks branch clocks BASE_ADC_CLK BA SE_ICLK0_CLK BASE_ICLK1_CLK CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0/1 I2C0/1 networking subsystem BASE_IVNSS_CLK branch clocks RESET/CLOCK GENERATION & POWER MANAGEMENT power control subsystem BASE_PCR_CLK branch clock GPIO0/1/5 TIMER 0/1/2/3 SPI0/1/2 UART0/1 WDT BASE_SYS_CLK CPU AHB MULTILAYER MATRIX VIC GPDMA USB REGISTERS FLASH/SRAM general subsytem peripheral subsystem AHB TO APB BRIDGES SYSTEM CONTROL EVENT ROUTER CFID branch clocks BASE_SAFE_CLK BASE_UART_CLK BASE_SPI_CLK BASE_TMR_CLK 002aae238 CGU0 CGU1 BASE_USB_CLK BASE_OUT_CLK USB CLOCK OUT

Table 7. Base clock and branch clock overview

source. See Section 6.12 for details. source. See Section 6.15 for details. [4] The clock should remain activated when syst em wake-up on timer or UART is required.

6.8 Flash memory controller

• Memory data transfer
• Memory configuration via triggering, programming, and erasing The key features are: BASE_UART_CLK CLK_UART0 UART 0 interface clock CLK_UART1 UART 1 interface clock BASE_ICLK0_CLK - clock for CGU1 input BASE_SPI_CLK CLK_SPI0 SPI 0 interface clock CLK_SPI1 SPI 1 interface clock CLK_SPI2 SPI 2 interface clock BASE_TMR_CLK CLK_TMR0 Timer 0 clock for counter part CLK_TMR1 Timer 1 clock for counter part CLK_TMR2 Timer 2 clock for counter part CLK_TMR3 Timer 3 clock for counter part BASE_ADC_CLK CLK_ADC1 Control of ADC 1, capture sample result CLK_ADC2 Control of ADC 2, capture sample result reserved - - BASE_ICLK1_CLK - clock for CGU1 input

Table 8. CGU1 base clock and branch clock overview Table 7. Base clock and branch clock overview …continued

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 17 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

• Programming by CPU via AHB
• Programming by external programmer via JTAG
• JTAG access protection
• Burn-finished and erase-finished interrupt

6.8.1 Functional description

After reset flash initialization is started. During this initialization, flash access is not possible and AHB transfers to flash are stalled, blocking the AHB bus. During flash initialization, the index sector is read to identify the status of the JTAG access protection and sector security. If JTAG access protection is active, the flash is not accessible via JTAG. In this case, ARM debug facilities are disabled and flash-memory contents cannot be read. If sector security is active, only the unsecured sections can be read. Flash can be read synchronously or asynchronously to the system clock. In synchronous operation, the flash goes into standby after returning the read data. Started reads cannot be stopped, and speculative reading and dual buffering are therefore not supported. With asynchronous reading, transfer of the address to the flash and of read data from the flash is done asynchronously, giving the fastest possible response time. Started reads can be stopped, so speculative reading and dual buffering are supported. Buffering is offered because the flash has a 128-bit wide data interface while the AHB interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash word, from which four words can be read. Without buffering every AHB data port read starts a flash read. A flash read is a slow process compared to the minimum AHB cycle time, so with buffering the average read time is reduced improving system performance. With single buffering, the most recently read flash word remains available until the next flash read. When an AHB data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles. When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer. On a primary buffer, hit data can be copied to the secondary buffer line, which allows the flash to start a speculative read of the next flash word. Both buffer lines are invalidated after:

• Initialization
• Configuration-register access
• Data-latch reading
• Index-sector reading The modes of operation are listed in Table 9.

6.8.2 Flash layout

of 128 bits (four 32-bit AHB bus words, hence 16 bytes). sector contains 16 pages; a large sector contains 128 pages. gives an overview of the flash-sector base addresses. Table 9. Flash read modes Table 10. Flash sector overview

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 19 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector’s address space. Note that the index sector, once programmed, cannot be erased. Any flash operation must be executed out of SRAM (internal or external).

6.8.3 Flash bridge wait-states

To eliminate the delay associated with synchronizing flash-read data, a predefined number of wait-states must be programmed. These depend on flash-memory response time and system clock period. The minimum wait-states value can be calculated with the following formulas: Synchronous reading: (1) Asynchronous reading: (2) Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active.

6.8.4 Pin description

The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see Section 6.6.3.

6.8.5 Clock description

The flash memory controller is clocked by CLK_SYS_FMC, see Section 6.7.2.

6.8.6 EEPROM

EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller.

6.9 General Purpose DM A (GPDMA) controller

The GPDMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same AHB master or one area by each master. WST tacc clk() tttclk sys() WST tacc addr() ttclk sys()

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 20 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN The GPDMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. Incrementing or non-incrementing addressing for source and destination are supported, as well as programmable DMA burst size. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.

6.9.1 DMA support for peripherals

The GPDMA supports the following peripherals: SPI0/1/2, UART0/1, and the I2C0/1-interfaces. The GPDMA can access both embedded SRAM blocks, both TCMs, external static memory, and flash memory.

6.9.2 Clock description

The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see Section 6.7.2.

6.10 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host controller. The LPC2921/2923/2925 USB interface includes a device controller with on-chip PHY for device. Details on typical USB interfacing solutions can be found in Section 10.2

6.10.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. The USB device controller has the following features:

• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, the LPC2921/2923/2925 can enter the reduced power mode and wake up on USB activity.
• Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints.
• Allows dynamic switching between CPU-controlled slave and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.

6.10.2 Pin description

6.10.3 Clock description

the USB block, BASE_USB_CLK (see Section 6.15.3). Table 11. USB device port pins

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 22 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.11 General subsystem

6.11.1 General subsystem clock description

The general subsystem is clocked by CLK_SYS_GESS, see Section 6.7.2.

6.11.2 Chip and feature identification

The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains an ID to identify the silicon and also registers containing information about the features enabled or disabled on the chip. The key features are:

• Identification of product
• Identification of features enabled The CFID has no external pins.

6.11.3 System Control Unit (SCU)

The system control unit contains system-related functions.The key feature is configuration of the I/O port-pins multiplexer. It defines the function of each I/O pin of the LPC2921/2923/2925. The I/O pin configuration should be consistent with peripheral function usage. The SCU has no external pins.

6.11.4 Event router

The event router provides bus-controlled routing of input events to the vectored interrupt controller for use as interrupt or wake-up signals. Key features:

• Up to 16 level-sensitive external interrupt pins, including the receive pins of SPI, CAN, LIN, and UART, as well as the I2C-bus SCL pins plus three internal event sources.
• Input events can be used as interrupt source either directly or latched (edge-detected).
• Direct events disappear when the event becomes inactive.
• Latched events remain active until they are explicitly cleared.
• Programmable input level and edge polarity.
• Event detection maskable.
• Event detection is fully asynchronous, so no clock is required. The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. The vectored interrupt-controller inputs are active HIGH.

6.11.4.1 Pin description

The event router module in the LPC2921/2923/2925 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 12 shows the pins connected to the event router.

6.12 Peripheral subsystem

6.12.1 Peripheral subsystem clock description

• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
• CLK_SAFE see Section 6.7.2

6.12.2 Watchdog timer

reset if the user program fails to trigger it correctly within a predetermined amount of time.

• Internal chip reset if not periodically triggered
• Timer counter register runs on always-on safe clock
• Optional interrupt generation on watchdog time-out

Table 12. Event-router pin connections

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 24 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

• Debug mode with disabling of reset
• Watchdog control register change-protected with key
• Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.

6.12.2.1 Functional description

The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted. When the watchdog times out, it generates a reset through the RGU. To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing to the clear-interrupt register. Another way to prevent resets during debug mode is via the Pause feature of the watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the PAUSE_ENABLE bit in the watchdog timer control register is set. The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains a reset source register to identify the reset source when the device has gone through a reset. See Section 6.15.4.

6.12.2.2 Clock description

The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE, see Section 6.7.2. The register interface towards the system bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on.

6.12.3 Timer

The LPC2921/2923/2925 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each timer has four capture inputs and/or match outputs. Connection to device pins depends on the configuration programmed into the port function-select registers. The two timers located in the MSCSS have no external capture or match pins, but the memory map is identical, see Section 6.14.6 . One of these timers has an external input for a pause function. The key features are:

• 32-bit timer/counter with programmable 32-bit prescaler
• Up to four 32-bit capture channels per timer. These take a snapshot of the timer value when an external signal connected to the TIMERx CAPn input changes state. A capture event may also optionally generate an interrupt
• Four 32-bit match registers per timer that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation
• Up to four external outputs per timer corresponding to match registers, with the following capabilities:

• Pause input pin (MSCSS timers only) The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. They also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt. The core function of the timers consists of a 32 bit prescale counter triggering the 32 bit timer counter. Both counters run on clock CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this clock. Note that each timer has its individual clock source within the Peripheral SubSystem. In the Modulation and Sampling SubSystem each timer also has its own individual clock source. See section Section 6.15.5 for information on generation of these clocks.

6.12.3.1 Pin description

Table 13 shows the timer pins (x runs from 0 to 3). [1] Note that CAP0 and CAP1 are not pinned out on Timer1.

6.12.3.2 Clock description

6.12.4 UARTs

Table 13. Timer pins

• 16-byte receive and transmit FIFOs.
• Register locations conform to 550 industry standard.
• Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes.
• Built-in baud rate generator.
• Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART is commonly used to implement a serial interface such as RS232. The LPC2921/2923/2925 contains two industry-standard 550 UARTs with 16-byte transmit and receive FIFOs, but they can also be put into 450 mode without FIFOs. Remark: The LIN controller can be configured to provide two additional standard UART interfaces (see Section 6.13.2

6.12.4.1 Pin description

LPC2921/2923/2925. Table 14 shows the UART pins (x runs from 0 to 1).

6.12.4.2 Clock description

6.12.5 Serial peripheral interface (SPI)

allow synchronous serial communication with slave or master peripherals.

• Master or slave operation
• Each SPI supports up to four slaves in sequential multi-slave operation
• Supports timer-triggered operation
• Programmable clock bit rate and prescale based on SPI source clock (BASE_SPI_CLK), independent of system clock
• Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep
• Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces
• Programmable data-frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
• Serial clock-rate master mode: fserial_clk ≤ fCLK(SPI)/2

Table 14. UART pins

• Serial clock-rate slave mode: fserial_clk = fCLK(SPI)/4
• Internal loopback test mode The SPI module can operate in:
• Master mode: – Normal transmission mode – Sequential slave mode
• Slave mode

6.12.5.1 Functional description

32 words deep). Serial data is transmitted on SPI_TXD and received on SPI_RXD. the SPI serial clock from the input clock CLK_SPIx. the SLVn_SETTINGS registers. interrupts are asserted and unmasked. frame format or an active-LOW chip select for SPI. programmed, and is transmitted starting with the MSB.

6.12.5.2 Pin description

master mode, input in slave mode. Table 15. SPI pins

6.12.5.3 Clock description

is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.

6.12.6 General-purpose I/O

programmed in the port function-select registers.

• General-purpose parallel inputs and outputs
• Direction control of individual bits
• Synchronized input sampling for stable input-data values
• All I/O defaults to input at reset to avoid any possible bus conflicts

6.12.6.1 Functional description

To generate an open-drain output, set the bit in the output register to the desired value. pulled up internally or externally.

6.12.6.2 Pin description

Table 16. GPIO pins

6.12.6.3 Clock description

CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.

6.13 Networking subsystem

6.13.1 CAN gateway

• Supports 11-bit as well as 29-bit identifiers
• Double receive buffer and triple transmit buffer
• Programmable error-warning limit and error counters with read/write access
• Arbitration-lost capture and error-code capture with detailed bit position
• Single-shot transmission (i.e. no re-transmission)
• Listen-only mode (no acknowledge; no active error flags)
• Reception of ‘own’ messages (self-reception request)
• Full CAN mode for message reception

6.13.1.1 Global acceptance filter

also possible to define identifier groups for standard and extended message formats.

6.13.1.2 Pin description

pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 17 shows the CAN pins (x runs from 0 to 1). Table 17. CAN pins

6.13.2 LIN

with hardware implementation of the LIN protocol according to spec 2.0.

• Complete LIN 2.0 message handling and transfer
• One interrupt per LIN message
• Slave response time-out detection
• Programmable sync-break length
• Automatic sync-field and sync-break generation
• Programmable inter-byte space
• Hardware or software parity generation
• Automatic checksum generation
• Fault confinement
• Fractional baud rate generator

6.13.2.1 Pin description

The two LIN 2.0 master controllers in the LPC2921/2923/2925 have the pins listed below. subsection 3.43, LIN master controller. Remark: Both LIN channels can be also configured as UART channels.

6.13.3 I 2C-bus serial I/O controllers

The LPC2921/2923/2925 each contain two I2C-bus controllers. controlled by more than one bus master connected to it.

• I2C0 and I2C1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus) and do not support powering off of individual devices connected to the same bus lines.
• Easy to configure as master, slave, or master/slave.

Table 18. LIN controller pins

• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.

6.13.3.1 Pin description

[1] Note that the pins are not I 2C-bus compliant open-drain pins.

6.14 Modulation and samp ling control subsystem

Analog-to-Digital Converters (ADCs) and two timers.

• Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger- start options.
• Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality.
• Two dedicated timers to schedule and synchronize the PWMs and ADCs.
• Quadrature encoder interface.

6.14.1 Functional description

Table 19. I 2C-bus pins[1]

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 32 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. Capture inputs are provided to measure event phases compared to the main counter. Depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. Interrupt signals are generated on several events to closely interact with the CPU. The ADCs can be used for any application needing accurate digitized data from analog sources. To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section 6.15.2

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 33 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Fig 5. Modulation and Sampling Control Sub System (MSCSS) block diagram 002aae248 PWM0 MAT[5:0] PWM1 MAT[5:0] PWM2 MAT[5:0] PWM3 MAT[5:0] PWM0 CAP[2:0] PAUSE MSCSS TIMER0 MSCSS TIMER1 ADC1 ADC2 PWM0 PWM1 ADC1 IN[7:0] ADC2 IN[7:0] ADC2 EXT START QEI PWM1 CAP[2:0] PWM2 TRAP PWM2 CAP[2:0] PWM3 TRAP PWM3 CAP[2:0] start start start synch PWM2 synch PWM3 synch carrier carrier carrier carrier PHA0 PHB0 MSCSS AHB-TO-APB BRIDGE capture capture

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 34 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.14.2 Pin description

The pins of the LPC2921/2923/2925 MSCSS associated with the two ADC modules are described in Section 6.14.4.2. Pins connected to the four PWM modules are described in Section 6.14.5.4, pins directly connected to the MSCSS timer 1 module are described in Section 6.14.6.1, and pins connected to the quadrature encoder interface are described in Section 6.14.7.1. Remark: The IDX0 function for the QEI, the external start function for ADC1, and the TRAP0/1 functions for the PWM0/1 are not pinned out on the LPC2921/2923/2925.

6.14.3 Clock description

The MSCSS is clocked from a number of different sources:

• CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge
• CLK_MSCSS_APB clocks the subsystem APB bus
• CLK_MSCSS_MTMR0/1 clocks the timers
• CLK_MSCSS_PWM0..3 clocks the PWMs. Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 1 or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see Section 6.7.2. All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding clocks can be switched off.

6.14.4 Analog-to-digital converter

The MSCSS in the LPC2921/2923/2925 includes two 10-bit successive-approximation analog-to-digital converters. The key features of the ADC interface module are:

• ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to 3.3 V.
• External reference-level inputs.
• 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit resolution.
• Programmable resolution from 2-bit to 10-bit.
• Single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode.
• Optional conversion on transition on external start input, timer capture/match signal, PWM_sync or ‘previous’ ADC.
• Converted digital values are stored in a register for each channel.
• Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’ compare-value indication for each channel.
• Power-down mode.

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 35 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.14.4.1 Functional description

The ADC block diagram, Figure 6, shows the basic architecture of each ADC. The ADC functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain. A mechanism is provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain. The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency. To meet this constraint or to select the desired lower sampling frequency, the clock generation unit provides a programmable fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined by the ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC registers requires an enabled ADC clock, which is controllable via the clock generation unit, see Section 6.15.2. Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs are connected at MSCSS level, see Section 6.14 for details.

6.14.4.2 Pin description

The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2921/2923/2925. The VREFN and VREFP pins are common for both ADCs. Table 20 shows the ADC pins. Fig 6. ADC block diagram 002aae251 ADC start 2 ADC start 0 APB clock (BASE_MSCSS_CLK) ADC clock (up to 4.5 MHz) (BASE_ADC_CLK) APB system bus IRQ scan IRQ compare ADC2 IN[7:0] ADC start 1 ADC start 3 sync_out ADC DOMAINSYSTEM DOMAIN ADC CONTROL ADC REGISTERS 3.3 V ADC2 3.3 V ADC1 ANALOG MUX conversion data update configuration data IRQ ADC1 IN[7:0] ANALOG MUX

3.3 V IN

Table 31) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant.

6.14.4.3 Clock description

unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off. since they are derived from the same base clock BASE_ADC_CLK. The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB.

6.14.5 Pulse Width Modulator (PWM)

• Six pulse-width modulated output signals
• Double edge features (rising and falling edges programmed individually)
• Optional interrupt generation on match (each edge)
• Different operation modes: continuous or run-once
• 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods
• A protective mode (TRAP) holding the output in a software-controllable state and with optional interrupt generation on a trap event
• Three capture registers and capture trigger pins with optional interrupt generation on a capture event
• Interrupt generation on match event, capture event, PWM counter overflow or trap event
• A burst mode mixing the external carrier signal with internally generated PWM
• Programmable sync-delay output to trigger other PWM modules (master/slave behavior)

Table 20. Analog to digital converter pins

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6.14.5.1 Functional description

The ability to provide flexible waveforms allows PWM blocks to be used in multiple applications; e.g. dimmer/lamp control and fan control. Pulse-width modulation is the preferred method for regulating power since no additional heat is generated, and it is energy-efficient when compared with linear-regulating voltage control networks. The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A very basic application of these pulses can be in controlling the amount of power transferred to a load. Since the duty cycle of the pulses can be controlled, the desired amount of power can be transferred for a controlled duration. Two examples of such applications are:

• Dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle period allows the PWM to control the amount of power to be transferred to the load. The PWM functions as a dimmer controller in this application
• Motor controller: The PWM provides multi-phase outputs, and these outputs can be controlled to have a certain pattern sequence. In this way the force/torque of the motor can be adjusted as desired. This makes the PWM function as a motor drive. The PWM block diagram in Figure 7 shows the basic architecture of each PWM. PWM functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective. The actual PWM and prescale counters are located in the PWM domain but system control takes place in the APB domain. Fig 7. PWM block diagram 002aad837 APB system bus IRQ pwm IRQ capt_match PWM CONTROL REGISTERS update capture data PWM counter value config data IRQ's PWM, COUNTER, PRESCALE COUNTER SHADOW REGISTERS match outputs capture inputs trap input carrier inputs sync_in sync_out transfer_enable_in transfer_enable_out APB DOMAIN PWM DOMAIN

6.14.5.2 Synchronizing the PWM counters

synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.

6.14.5.3 Master and slave mode

generation of trans_enable_out and sync_out. internal PWM counter and the transfer of shadow registers (Slave mode).

6.14.5.4 Pin description

PWM0 to PWM3 pins (n = 0 to 3). Table 21. PWM pins

6.14.5.5 Clock description

The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 - 3), see Section 6.7.2. they are derived from the same base clock BASE_MSCSS_CLK. CLK_MSCSS_APB. This clock is independent of the AHB system clock. If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.

6.14.6 Timers in the MSCSS

modules as outlined in the description of the MSCSS, see Section 6.14.1. See section Section 6.12.3 for a functional description of the timers.

6.14.6.1 Pin description

MSCSS timer 0 has no external pins.

6.14.6.2 Clock description

since they are derived from the same base clock BASE_MSCSS_CLK. clock is independent of the AHB system clock. If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.

6.14.7 Quadrature Encoder Interface (QEI)

addition, the QEI can capture the velocity of the encoder wheel. Table 22. MSCSS timer 1 pin

• Tracks encoder position.
• Increments/ decrements depending on direction.
• Programmable for 2X or 4X position counting.
• Velocity capture using built-in timer.
• Velocity compare function with less than interrupt.
• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
• Connected to APB.

6.14.7.1 Pin description

functions on the port pins of the LPC2921/2923/2925. Table 23 shows the QEI pins. Remark: The index function for the QEI is not pinned out on the LPC2921/2923/2925.

6.14.7.2 Clock description

If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off.

6.15 Power, clock, and Reset control Sub System (PCRSS)

communication with the AHB system bus. Table 23. QEI pins

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 41 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.15.1 Clock description

The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see Section 6.7.2. CLK_SYS_PCRSS is derived from BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. Fig 8. Power, Clock, and Reset control Sub System (PCRSS) block diagram 002aae249 AHB2DTL BRIDGE RESET OUTPUT DELAY LOGIC INPUT DEGLITCH/ SYNC branch clocks grant request wakeup_a AHB_RST SCU_RST WARM_RST COLD_RST PCR_RST RGU_RST POR_RST RST_N (device pin) reset from watchdog counter EXTERNAL OSCILLATOR PMU REGISTERS CLOCK ENABLE CONTROL CLOCK GATESLOW POWER RING OSCILLATOR CGU0/1 REGISTERS RGU REGISTERS POR OUT0 OUT1 OUT5 OUT7 OUT9 OUT6 OUT11 OUT0 OUT2 PLL FDIV[6:0] PLL FDIV CGU0 CGU1 PMU RGU AHB master disable:

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 42 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN

6.15.2 Clock Generation Unit (CGU0)

The key features are:

• Generation of 11 base clocks selectable from several embedded clock sources.
• Crystal oscillator with power-down.
• Control PLL with power-down.
• Very low-power ring oscillator, always on to provide a safe clock.
• Seven fractional clock dividers with L/D division.
• Individual source selector for each base clock, with glitch-free switching.
• Autonomous clock-activity detection on every clock source.
• Protection against switching to invalid or inactive clock sources.
• Embedded frequency counter.
• Register write-protection mechanism to prevent unintentional alteration of clocks. Remark: Any clock-frequency adjustment has a direct impact on the timing of all on-board peripherals.

6.15.2.1 Functional description

The clock generation unit provides 11 internal clock sources as described in Table 24. [1] Maximum frequency that guarantees stable operation of the LPC2921/2923/2925. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. Table 24. CGU0 base clocks

Description

0 BASE_SAFE_CLK 0.4 base safe clock (always on)

1 BASE_SYS_CLK 100 base system clock

2 BASE_PCR_CLK 0.4 [2] base PCR subsystem clock

3 BASE_IVNSS_CLK 100 base IVNSS subsystem clock

4 BASE_MSCSS_CLK 100 base MSCSS subsystem clock

5 BASE_ICLK0_CLK 160 base inte rnal clock 0, for CGU1

6 BASE_UART_CLK 100 base UART clock

7 BASE_SPI_CLK 50 base SPI clock

8 BASE_TMR_CLK 100 base timers clock

9 BASE_ADC_CLK 4.5 base ADCs clock 10 reserved - -

11 BASE_ICLK1_CLK 160 base inte rnal clock 1, for CGU1

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 43 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 9. LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted. Configuration of the CGU0: For every output generator generating the base clocks a choice can be made from the primary and secondary clock generators according to Figure 10. Fig 9. Block diagram of the CGU0 (see Table 24 for all base clocks) 400 kHz LP_OSC PLL FDIV0 EXTERNAL OSCLLLATOR FDIV1 FDIV6 OUT 0 OUT 1 OUT 11 002aae147 clkout clkout120 clkout240 CLOCK GENERATION UNIT (CGU0) FREQUENCY MONITOR CLOCK DETECTION AHB TO DTL BRIDGE BASE_SYS_CLK BASE_ICLK1_CLK OUT 3 BASE_IVNSS_CLK OUT 2 BASE_PCR_CLK BASE_SAFE_CLK

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 44 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only LP_OSC as source. The fractional dividers can be connected to one of the outputs of the PLL or directly to LP_OSC/crystal Oscillator. The PLL is connected to the crystal oscillator. In this way every output generating the base clocks can be configured to get the required clock. Multiple output generators can be connected to the same primary or secondary clock source, and multiple secondary clock sources can be connected to the same PLL output or primary clock source. Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL outputs itself for example - will be blocked by hardware. The control register will not be written, the previous value will be kept, although all other fields will be written with new data. This prevents clocks being blocked by incorrect programming. Default Clock Sources: Every secondary clock generator or output generator is connected to LP_OSC at reset. In this way the device runs at a low frequency after reset. It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as (one of) the first step(s) in the boot code after verifying that the high-frequency clock generator is running. Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid, and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock generator. The RDET register keeps track of which clocks are active and inactive, and the Fig 10. Structure of the clock generation scheme LP_OSC PLL FDIV0..6 EXTERNAL OSCILLATOR 002aad834 clkout clkout120 clkout240 OUTPUT CONTROL clock outputs

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 45 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After reset all clocks are assumed to be ‘non-present’, so the RDET status register will be correct only after 32 BASE_PCR_CLK cycles. Note that this mechanism cannot protect against a currently-selected clock going from active to inactive state. Therefore an inactive clock may still be sent to the system under special circumstances, although an interrupt can still be generated to notify the system. Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators. In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch will occur as quickly as possible, although there will always be a period when the clock is held low due to synchronization requirements. If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the interface.

6.15.2.2 PLL functional description

A block diagram of the PLL is shown in Figure 11 . The input clock is fed directly to the analog section. This block compares the phase and frequency of the inputs and generates the main clock2. These clocks are either divided by 2 × P by the programmable post divider to create the output clock, or sent directly to the output. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock. 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 32, Dynamic characteristics. Fig 11. PLL block diagram CCO / 2PDIV P23 / MDIV 002aad833 bypass direct clkout120 clkout240 clkout clkout input clock PSEL bits P23EN bit MSEL bits

PLL, thus giving three clocks with a 120° phase difference.

6.15.2.3 Pin description

6.15.3 Clock generation for USB (CGU1)

can be configured to drive the output clock directly. Table 25. CGU0 pins

6.15.3.1 Pin description

The CGU1 module in the LPC2921/2923/2925 has the pins listed in Table 25 below.

6.15.4 Reset Generation Unit (RGU)

The RGU controls all internal resets.

• Reset controlled individually per subsystem
• Automatic reset stretching and release
• Monitor function to trace resets back to source
• Register write-protection mechanism to prevent unintentional resets

6.15.4.1 Functional description

the listed reset sources causes the output to go active. Table 26. CGU1 pins

6.15.4.2 Pin description

6.15.5 Power Management Unit (PMU)

disabling clocks not required in a particular operating mode. Table 27. Reset output configuration Table 28. RGU pins

• Individual clock control for all LPC2921/2923/2925 sub-modules
• Activates sleeping clocks when a wake-up event is detected
• Clocks can be individually disabled by software
• Supports AHB master-disable protocol when AUTO mode is set
• Disables wake-up of enabled clocks when Power-down mode is set
• Activates wake-up of enabled clocks when a wake-up event is received
• Status register is available to indicate if an input base clock can be safely switched off (i.e. all branch clocks are disabled)

6.15.5.1 Functional description

register. Some branch clocks controlling vital parts of the device operate in a fixed mode. Table 29 shows which mode- control bits are supported by each branch clock. on or off, and which clocks are switched off when entering Power-down mode. into power-down should be controlled by disabling the branch clock for the CPU. clocks must be running (controlled by the CGU0). shows the relation between branch and base clocks, see also Section 6.7.1. source of a branch clock in the PMU. Table 29. Branch clock overview

Table 29. Branch clock overview …continued

6.16 Vectored interrupt controller

Controller (VIC) to interrupt the ARM processor on request.

• Level-active interrupt request with programmable polarity.
• 56 interrupt-request inputs.
• Software-interrupt request capability associated with each request input.
• Interrupt request state can be observed before masking.
• Software-programmable priority assignments to interrupt requests up to 15 levels.
• Software-programmable routing of interrupt requests towards the ARM-processor inputs IRQ and FIQ.
• Fast identification of interrupt requests through vector.
• Support for nesting of interrupt service routines.

6.16.1 Functional description

processor. The interrupt target is configured for each interrupt request input of the VIC.

• Target 0 is ARM processor FIQ (fast interrupt service)
• Target 1 is ARM processor IRQ (standard interrupt service) Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows:
• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never lead to an interrupt) CLK_TMR0 BASE_TMR_CLK + + + CLK_TMR1 BASE_TMR_CLK + + + CLK_TMR2 BASE_TMR_CLK + + + CLK_TMR3 BASE_TMR_CLK + + + CLK_ADC1 BASE_ADC_CLK + + + CLK_ADC2 BASE_ADC_CLK + + + CLK_TESTSHELL_IP BAS E_CLK_TESTSHELL 0 0 1 CLK_USB BASE_USB_CLK + + +

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• Priority 1 corresponds to the lowest priority
• Priority 15 corresponds to the highest priority Software interrupt support is provided and can be supplied for:
• Testing RTOS (Real-Time Operating System) interrupt handling without using device-specific interrupt service routines
• Software emulation of an interrupt-requesting device, including interrupts

6.16.2 Clock description

The VIC is clocked by CLK_SYS_VIC, see Section 6.7.2.

Table 30. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

[1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximu m input voltage is defined by VI(ADC). [4] Only when V DD(IO) is present. [6] Note that pull-up should be off. With pull-up do not exceed 3.6 V. [7] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor. DD(IO) or VSS(IO) should not be exceeded. Table 30. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).

Table 31. Static characteristics

Table 31. Static characteristics …continued

the specified temperature and power-supply voltage range. −38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted. [5] C xtal is crystal load capacitance and Cext are the two external load capacitors. Vtrip(low) for 11 μs before internal reset is asserted. [7] Not 5 V-tolerant when pull-up is on. [8] For I/O Port 0, the maximu m input voltage is defined by VI(ADC). based on simulation results.

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 58 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Fig 13. ADC characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 10241018 1019 1020 1021 1022 10237123456 1018 (5) (4) (3)

1 LSB

(ideal) code out VDDA − VSSA 1024 offset error EO gain error EG offset error EO VIA (LSBideal)

1 LSB =

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8.1 Power consumption

Conditions: Tamb = 25 °C; active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 14. I DD(CORE) at different core frequencies (active mode) Conditions: Tamb = 25 °C; active mode entered executing code from flash; all peripherals enabled but not configured to run. Fig 15. I DD(CORE) at different core voltages VDD(CORE) (active mode) core frequency (MHz) 10 1309050 002aae241 IDD(CORE) (mA) core voltage (V) 1.7 1.91.8 002aae240 IDD(CORE) (mA)

10 MHz

40 MHz

80 MHz

100 MHz

125 MHz

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8.2 Electrical pin characteristics

Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 16. I DD(CORE) at different temperatures (active mode) temperature (°C) −40 856010 35−15 002aae239 IDD(CORE) (mA) Measured on pins Pn.m; VDDIO = <tbd> V. Fig 17. Typical LOW-level output I OLcurrent versus LOW-level output VOL X (X) X XXXX 001aac984 X X X X X X (X) X <tbd>

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 61 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Measured on pins Pn.m; VDDIO = <tbd> V. Fig 18. Typical HIGH-level output I OH current versus HIGH-level output voltage VOH Measured on pins Pn.m; VDDIO = <tbd> V. Fig 19. Typical pull-up current I pu versus input voltage Vi X (X) X XXXX 001aac984 X X X X X X (X) X <tbd> X (X) X XXXX 001aac984 X X X X X X (X) X <tbd>

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 62 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Measured on pins Pn.m; VDDIO = <tbd> V. Fig 20. Typical pull-down current I pd versus input voltage Vi X (X) X XXXX 001aac984 X X X X X X (X) X <tbd>

9.1 Dynamic characteristics: I/O pins, in ternal clock, oscillators, PLL, and

test conditions to cover the specified temperature and power supply voltage range. [3] This parameter is not part of production testing or final testing, hence only a typical value is stated. Table 32. Dynamic characteristics

9.2 USB interface

[1] Characterized but not implemented as production test. Guaranteed by design. Table 33. Dynamic characteris tics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified.

9.3 Dynamic characteristics: I 2C-bus interface

test conditions to cover the specified temperature and power supply voltage range. [2] Typical ratings are not guaranteed. The va lues listed are at room temperature (25 °C), nominal supply voltages. [3] Bus capacitance C b in pF, from 10 pF to 400 pF. Table 34. Dynamic characteristic: I 2C-bus pins

9.4 Dynamic characteristics: SPI

test conditions to cover the specified temperature and power supply voltage range. Table 35. Dynamic characteristics of SPI pins

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 67 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Fig 24. SPI master timing (CPHA = 0) Fig 25. SPI slave timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad987 tSPICLK tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID tSPIQV SCK (CPOL = 0) MOSI MISO 002aad988 tSPICLK tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 68 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Fig 26. SPI slave timing (CPHA = 0) SCK (CPOL = 0) MOSI MISO 002aad989 tSPICLK tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID

9.5 Dynamic characteristics: flash memory

test conditions to cover the specified temperature and power supply voltage range. Table 36. Flash characteristics

9.6 Dynamic characteristics: ADC1/2

test conditions to cover the specified temperature and power supply voltage range. [2] Duty cycle clock should be as close as possible to 50 %.

10.1 Operating frequency selection

Table 37. ADC dynamic characteristics

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10.2 Suggested USB interface solutions

Fig 28. LPC29xx core operating frequency versus core voltage for different temperatures core voltage (V) 1.65 1.951.851.75 002aae193 125 115 135 145 core frequency (MHz) 105 25 °C 45 °C 65 °C 85 °C Fig 29. LPC2921/2923/2925 USB interface on a self-powered device LPC29xx USB-B connector USB_D+ USB_CONNECT soft-connect switch USB_D− USB_VBUS VSS(IO) VDD(IO) 1.5 kΩ RS = 33 Ω 002aae149 RS = 33 Ω USB_UP_LED

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 72 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN Fig 30. LPC2921/2923/2925 USB interface on a bus-powered device LPC29xx VDD(IO) 1.5 kΩ USB_UP_LED 002aae150 USB-B connector USB_D+ USB_D− USB_VBUS VSS(IO) RS = 33 Ω RS = 33 Ω

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 73 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN 11. Package outline Fig 31. Package outline (LQFP100) UNIT A max. A1 A2 A3 bp cE (1) eH E LL p Zy w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 o o0.08 0.080.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT407-1 136E20 MS-026 00-02-01 03-02-20 D (1) (1) (1) 14.1 13.9 H D 16.25 15.75 EZ 1.15 0.85 D bp e θ E A Lp detail X L (A )3 B c DH bp EH A2 v M B D ZD A ZE e v M A X 100 75 51 y pin 1 index w M w M 0 5 10 mm scale LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 74 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

12.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
• Solder bath specifications, including temperature and impurities

12.4 Reflow soldering

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 38 and 39 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.

Table 38. SnPb eutectic process (from J-STD-020C) Table 39. Lead-free process (from J-STD-020C)

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA LPC2921_2923_2925_0 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 00.01 — 24 October 2008 76 of 81 NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature

Table 40. Abbreviations list

Table 41. Revision history

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16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GoodLink — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. SoftConnect — is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

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6.15 Power, clock, and Reset control Sub System

DRAFT DRAFT DRAFT DRAFT DRAFT DDRAFT DRAFT DRA FT DRAFT DRAFT DRAFT DRA NXP Semiconductors LPC2921/2923/2925 ARM9 microcontroller with CAN and LIN © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 October 2008 Document identifier: LPC2921_2923_2925_0 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

9.1 Dynamic characteristics: I/O pins, internal clock,

9.3 Dynamic characteristics: I

2C-bus interface. . . 65