ARINC-429 LFTECH | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 4

Technical content

429 IP CORE

A ll data sheet.com

LFT ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps. Various functionalities like Parity & gap generators and checkers are implemented to ensure high data integrity. The module can be configured as a transmitter, receiver or both using Generic Parameters. A set of indicators are used in IP to indicate the status of IP during runtime. Overview Key Features 806, 8th Floor BPTP Park Centra Sector–30, NH–8 Gurgaon – 122001 Haryana (India) +91-0124 4643950 +1-408 338 9743 info@logic-fruit.com us@logic-fruit.com Technologies ARINC 429 IP Core ARINC 429 Wrapper RST_ASYNC CONFIG_CLK ARINC429_TX_P ARINC429_TX_N ARINC429_TX_SLP ARINC429 ARINC429 axil_rstn AXI_BUS ARINC429_RX_P CNFG_CLK_FREQ_TX TX_PRESENT RX_PRESENT CNFG_CLK_FREQ_RX BASE_ADDRESS REGISTER_NBR ARINC429_RX_N TEST_A/B_RX Register Interface (Configuration & Status Control) ARINC429 Receiver ARINC429 Transmitter Multichannel module supporting ARINC429 Receiver/Transmitter Configurable module supporting any number of receivers and transmitters (Standard with 16 receivers & 8 transmitters) Configurable data rate supporting from 12.5 Kbps to

1 Mbps

Parity & Gap generators & checkers for high data integrity Configurable parity and data types AXI Lite Compatibility for user interface IP portable to any available standard FPGA A ll data sheet.com

806, 8th Floor BPTP Park Centra Sector–30, NH–8 Gurgaon – 122001 Haryana (India) +91-0124 4643950 +1-408 338 9743 info@logic-fruit.com us@logic-fruit.com Technologies TECHNICAL SPECIFICATION ARINC429 Data Packet Flow Transmitter tandard module with eight transmitters and configurable to support any number of transmitters. Configurable ARINC429 dword data fields. Supported Configurable Data Rates- 12.5, 25, 48, 50, 100 Kbps and 1 Mbps. Synchronous FIFO for buffering incoming data to maintain desired data rate. Parity generator to assign odd parity as an error checking measure. Parity is configurable via the user interface. Configurable arinc429 data type of encoding the data. PISO (Parallel-in-serial-out) module to support RZ encoding. Transmitter Active Status, Error Status and Configuration Control. ARINC429 transmitter chip (level shifter) controlling. config_clk rst_async tx_lable tx_sdi tx_data tx_ssm tx_interript tx_ready tx_overflow_err tx_data_count TX_PARITY CNFG_CLK_FREQ(Generic) ARINC429_DATA_RATE_TX ARINC429_ DATA_TYPE_TX ARINC429_TX_P ARINC429_TX_N Parallel-In-Serial-Out (RZ Encoding) Pulse Calculator TX BUFFER Parity Generator ARINC429 Encoding ARINC 429 Transmitter ARINC429 Transmitter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P SSM MSB LSB SDI LabelData ARINC429 Data Packet A ll data sheet.com

ARINC 429 IP Core supports various encoding/decoding schemes: BNR Word Format (Signed Binary Number) – Encoded and transmitted by using 2s complement fractional binary notation BCD Word Format (Binary coded Decimal) Discrete Data-combination of Both BNR and BCD – Combination of BNR, BCD or individual bit representation (9-bit BNR and 10 bits individual are supported) Normal Binary Data 806, 8th Floor BPTP Park Centra Sector–30, NH–8 Gurgaon – 122001 Haryana (India) +91-0124 4643950 +1-408 338 9743 info@logic-fruit.com us@logic-fruit.com Technologies ARINC429 Data Type Receiver Standard module with 16 Receivers configurable to support any number of receivers. Data sync block and SIPO (Serial-in-Parallel Out) module using RZ decoding to test for data integrity. Supported Configurable Data Rates- 12.5, 25, 48, 50, 100 Kbps and 1 Mbps. Configurable arinc429 data type of decoding the data. Parity checker and Configurable parity hecking. Various data filed filtering from arinc429 dword. Receiver Active Status. Error Status and Configuration Control for configuring parameters. ARINC429 receiver (level shifter) chip controlling. Additional Support for Demonstration Axi Lite Bus support is compatible with any type of serial protocol (i.e. UART, USB, SPI, PCIe etc.) ARINC429 TX&Rx can run in loopback mode based on the configuration to communicate with the third- party arinc429 tx/rx devices. Standard GUI is implemented using TCL script for testing. UART(RS422) serial interface is implemented to communicate with the host PC. ARINC429 Core is tested with the third-party ARINC429 Tx & Rx (Holt HW) HI-8448 arinc429 receiver level shifter chip and HI-8596 transmitter level shifter chip are used on board along with Xilinx Kintex-7 FPGA to demonstrate this IP. config_clk rst_async rx_lable rx_data_read rx_sdi rx_data rx_ssm rx_data_valid sipo_clock rx_gap_error rx_parity_error rx_ready rx_overflow_err rx_data_count ARINC429_RX_N ARINC429_TX_P sync data & enable gen CNFG_CLK_FREQ(Generic) ARINC429_DATA_RATE_RX ARINC429_DATA_TYPE_RX RX_PARITY Serial-In-Parallel-Out (RZ decoding, Parity&Gap Checking) Pulse Calculator RX BUFFER ARINC429 Decoder ARINC 429 Receiver ARINC429 Receiver A ll data sheet.com