AR0833

AR0833_17 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• High-speed Sensor Supporting 8 Mp (4:3) 30 fps Still Images and Full HD 1080p30 Video
• 1.4 μ Pixel with ON Semiconductor A-PixHS™ Technology Providing Best-in-class Low-light Performance.
• Optional On-chip high-quality Bayer Scaler to Resize Image to Desired Size www.onsemi.com Features (Continued)
• Data Interfaces: Two-, Three-, and Four-lane Serial Mobile Industry Processor Interface (MIPI)
• Bit-depth Compression Available for MIPI Interface: 10-8 and 10-6 to Enable Lower Bandwidth Receivers for Full Frame Rate

Applications

• On-chip Temperature Sensor
• On-die phase-locked Loop (PLL) Oscillator
• 5.6 Kb One-time Programmable Memory (OTPM) for Storing Module Information
• On-chip 8-bit VCM Driver
• 3D Synchronization Controls to Enable Stereo Video Capture
• Interlaced Multi-exposure Readout Enabling High Dynamic Range (HDR) Still and Vide o
• Programmable Controls: Gain, Horizontal and Vertical Blanking, Auto Black Level Offset Correction, Frame Size/rate, Exposure, Left–right and Top–bottom Image Reversal, Window Size, and Panning
• Support for External Mechanical Shutter
• Support for External LED or Xenon Flash
• Smart phones
• PC cameras
• Tablets See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

www.onsemi.com Table 2. MODES OF OPERATION AND POWER CONSUMPTION AT 100% FOV

1. 732 Mbps/lane MIPI data transfer rate
2. Scaled image using internal High Quality Bayer Scaler
3. Electronic Image Stabilization
4. Values measured at T = 25 °C and nominal voltages

Table 3. AVAILABLE PART NUMBERS please visit our web site at www.onsemi.com. integration advantages of CMOS.

Figure 3. Typical Application Circuit − MIPI Connection

1. All power supplies should be adequately decoupled; recommended cap values are:
2. Resistor value 1.5 k /C0087 is recommended, but may be greater for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. V PP, 6−7 V, is used for programming OTPM. This pad is left unconnected if OTPM is not being programmed.
5. V DD_1V8 can be combined with VDD_IO, if VDD_IO = 1.8 V.
6. V DD_1V2 and VDD1_1V2_PHY can be tied together.
7. ATEST1 can be left floating.
8. TEST pin must be tied to D GND.

10.DVDD_1V8 is the OTPM read voltage (must always be provided).

Table 4. PAD DESCRIPTIONS DATA[4:1]P Output Differential serial data (positive). VCM_GND Input/Output Ground connection to VCM Driver. If not used, needs to be connected to ground (DGND).

Table 4. PAD DESCRIPTIONS (continued) domains from the ESD perspective. Table 5. INDEPENDENT POWER AND GROUND DOMAINS

diagram in Figure 4 and described in subsequent sections. states: hardware standby, software standby, and streaming. amount of clock cycles as outlined in Figure 4 and Figure 5. Figure 4. System States

recommended as shown in Figure 5. Table 6. INRUSH CONSIDERATION

0 Present Present Present Powered Down State

1 Present Present Present Powered Up State

Figure 5. Recommended Power-Up Sequence

Table 7. POWER-UP SEQUENCE

1. Disable streaming if output is active by setting
2. After disabling the internal clock EXTCLK,
3. After XSHUTDOWN is LOW disable the
4. After the 2.8 V/1.8 V supply is LOW disable the
5. After the 1.2 V supply is LOW disable the

Figure 6. Recommended Power-Down Sequence Table 8. POWER-DOWN SEQUENCE

www.onsemi.com TWO-WIRE SERIAL REGISTER INTERFACE A two-wire serial interface bus enables read/write access to control and status registers within the AR0833. The two-wire serial interface is fully compatible with the I standard. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (S CLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). S DATA is pulled up to V DD off-chip by a 1.5 k Ω resistor. Either the slave or master device can drive S DATA LOW-the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0833 uses S CLK as an input only and therefore never drives it LOW. The electrical and timing specifications are further detailed on “Two-Wire Serial Register Interface”. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on S DATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on S DATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when S CLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0833 for the MIPI configured sensor are 0x6C (write address) and 0x6D (read address) in accordance with the MIPI specification. Alternate slave addresses of 0x6E(write address) and 0x6F(read address) can be selected by enabling and asserting the S ADDR signal through the GPI pad. The alternate slave addresses can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving S DATA LOW. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

Table 9. ADDRESS SPACE REGIONS contiguous locations in the address space. model_id is a 16-bit register. is that some registers are decoded at multiple addresses. a register through any of its aliases is identical. for these formats is shown in Table 10.

Table 10. DATA FORMATS FIX16 Signed fixed-point, 16-bit number: two’s complement number, 8 fractional bits. UFIX16 Unsigned fixed-point, 16-bit number: 8.8 format. FLP32 Signed floating-point, 32-bit number: IEEE 754 format. register. The live register controls the sensor operation. register fields are double-buffered in this way.

• An external auto exposure algorithm might want to change both gain and integration time between two frames. If the next frame starts between these operations, it will have the new gain, but not the new integration time, which would return a frame with the wrong brightness that might lead to a feedback loop with the AE algorithm resulting in flickering. Bad Frames A bad frame is a frame where all rows do not have the same integration time or where offsets to the pixel values have changed during the frame. Many changes to the sensor register settings can cause a bad frame. For example, when line_length_pck (R0x300C) is changed, the new register value does not affect sensor behavior until the next frame start. However, the frame that would be read out at that frame start will have been integrated using the old row width, so reading it out using the new row width would result in a frame with an incorrect integration time. By default, bad frames are masked. If the masked bad frame option is enabled, both LV and FV are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. In the register tables, the “Bad Frame” column shows where changing a register or register field will cause a bad frame. This notation is used:
• N − No. Changing the register value will not produce a bad frame.
• Y − Y es. Changing the register value might produce a bad frame.
• YM − Y es; but the bad frame will be masked out when mask_corrupted_frames (R0x301A[9]) is set to “1.” Changes to Integration Time If the integration time is changed while FV is asserted for frame n, the first frame output using the new integration time is frame (n + 2). The sequence is as follows: 1. During frame n, the new integration time is held in the pending register. 2. At the start of frame (n + 1), the new integration time is transferred to the live register. Integration for each row of frame (n + 1) has been completed using the old integration time. 3. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent upon the new value of the integration time. 4. When frame (n + 2) is read out, it will have been integrated using the new integration time. If the integration time is changed on successive frames, each value written will be applied for a single frame; the latency between writing a value and it affecting the frame readout remains at two frames.

www.onsemi.com op_sys_clk_freq_mhz /C0043 ext_clk_freq_mhz /C0032pll_multiplier pre_pll_clk_div /C0032op_sys_clk_div (eq. 3) PLL Clocking The PLL divisors should be programmed while the AR0833 is in the software standby state. After programming the divisors, it is necessary to wait for the VCO lock time before enabling the PLL. The PLL is enabled by entering the streaming state. An external timer will need to delay the entrance of the streaming mode by 1 millisecond so that the PLL can lock. The effect of programming the PLL divisors while the AR0833 is in the streaming state is undefined. Clock Control The AR0833 uses an aggressive clock-gating methodology to reduce power consumption. The clocked logic is divided into a number of separate domains, each of which is only clocked when required. When the AR0833 enters a soft standby state, almost all of the internal clocks are stopped. The only exception is that a small amount of logic is clocked so that the two-wire serial interface continues to respond to read and write requests. The sensor enables HDR by outputting frames where even and odd row pairs within a single frame are captured at different integration times. This output is then matched with an algorithm designed to reconstruct this output into an HDR still image or video. The sensor HDR is controlled by two shutter pointers (Shutter pointer1, Shutter pointer2) that control the integration of the odd (Shutter pointer1) and even (Shutter pointer 2) row pairs. Figure 16. HDR Integration Time

1. Set R0x400 = 2 // Enable the on-chip scalar.
2. Set R0x306E to 0x90B0 // Configure the on-chip

scalar to resample Bayer data.

1. Set R0x400 = 0 // Disable the on-chip scalar.
2. Set R0x306E to 0x9080 // Configure the on-chip

scalar to resample Bayer data. when using the resample feature. Figure 19. Illustration of Resampling Operation programming and read operations. the module, it should be left floating inside the module. setting of the status bit through the two-wire serial interface.

1. Apply power to all the power rails of the sensor

be at their nominal voltage.

1. Provide a 12-MHz EXTCLK clock input.
2. Set R0x301A = 0x18, to put sensor in the soft
3. Set R0x3130 = 0xFF01 (Timing configuration)
4. Set R0x304C[7:0] = Length of the record which is
5. Set R0x3054[9] = 0 to ensure that the error

checking and correction is enabled.

1. Write data into all the OTPM data registers:
2. Set the otpm_control_auto_wr_start bit in the

program the data into the OTPM.

1. Poll otpm_control_auto_wr_end (R0x304A [1]) to
2. Verify that the otpm_control_auto_wr_

success(0x304A[2]) bit is set.

1. If the above bits are not set to 1, then examine

OTPM memory is insufficient.

1. Remove the high voltage (V
2. Apply power to all the power rails of the sensor
3. Set EXTCLK to normal operating frequency.
4. Perform proper reset sequence to the sensor.
5. Set R0x3134 = 0xCD95 (Timing Configuration)

1. Set R0x304C[15:8] = Record Type (for example,
2. Set R0x304C[7:0] = Length of the record which is
3. Initiate the auto read sequence by setting the
4. Poll the otpm_control_auto_rd_end bit

was read successfully or not.

1. Data can now be read back from the otpm_data

registers (R0x3800-R0x39FE).

1. Electronic rolling shutter (ERS) mode.
2. Global reset release (GRR) mode.

x_output_size and y_output_size registers. x_output_size, and y_output_size registers accordingly. These border pixels can be used but are disabled by default. value of the pixel_order register. Figure 20. Effect of horizontal_mirror on Readout Order

integration times to be used in each mode.

• x_addr_start should be a multiple of x_skip_factor x 4
• (x_addr_end − x_addr_start + x_odd_inc) should be a multiple of x_skip_factor x 4
• (y_addr_end − y_addr_start + y_odd_inc) should be a multiple of y_skip_factor x 4 The number of columns/rows read out with subsampling can be found from the equation below:
• columns/rows = (addr_end − addr_start + odd_inc) / skip_factor Table 11 shows the row or column address sequencing for normal and subsampled readout. In the 2X skip case, there are two possible subsampling sequences (because the subsampling sequence only reads half of the pixels) depending upon the alignment of the start address. Similarly, there will be four possible subsampling sequences in the 4X skip case (though only the first two are shown in Table 11).

Table 11. ROW ADDRESS SEQUENCING DURING SUBSAMPLING artifacts that can be a characteristic side effect of skipping. shown in Figure 27 below and Figure 28. is used to achieve 4X subsampling with better image quality. The effect of this subsampling mode is shown in Figure 28.

implementation of the binning itself. address sequences are shown in Table 12. Table 12. COLUMN ADDRESS SEQUENCING DURING BINNING y_addr_start. The possible sequences are shown in Table 13. Table 13. ROW ADDRESS SEQUENCING DURING BINNING

times the sensitivity compared to the binning only mode. Table 14. AVAILABLE SKIP , BIN, AND SUM MODES Figure 29. Pixel Binning and Summing

the scaler is in Bayer format. steps, is used for horizontal and vertical scalers. full (horizontal and vertical) scaling.

• n, which is fixed at 16
• m, which is adjustable with register R0x0404
• Legal values for m are 16 through 96, giving the user the ability to scale from 1:1 (m = 16) to 1:6 (m = 96) Frame Rate Control The formulas for calculating the frame rate of the AR0833 are shown below. The line length is programmed directly in pixel clock periods through register line_length_pck. For a specific window size, the minimum line length can be found from Equation 8: minimum line_length_pck /C0043/C0466x_addr_end /C0042x_addr_start /C00411 subsampling factor /C0041min_line_blanking_pck/C0467(eq. 8) Note that line_length_pck also needs to meet the minimum line length requirement set in register min_line_length_pck. The row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in “Minimum Row Time”. The frame length is programmed directly in number of lines in the register frame_line_length. For a specific window size, the minimum frame length can be found in Equation 9: minimum frame_length_lines /C0043/C0466 y_addr_end /C0042y_addr_start /C00411 subsampling factor /C0041min_frame_blanking_lines/C0467(eq. 9) The frame rate can be calculated from these variables and the pixel clock speed as shown in Equation 10: frame rate /C0043 vt_pixel_clock_mhz /C00321 /C0032106 line_length_pck /C0032frame_length_lines (eq. 10) If coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. Minimum Row Time Enough time must be given to the output FIFO so it can output all data at the set frequency within one row time. There are therefore two checks that must all be met when programming line_length_pck:
• line_length_pck ≥ min_line_length_pck in Table 15
• The row time must allow the FIFO to output all data during each row. That is, line_length_pck ≥ (x_output_size × 2 + 0x005E) × “vt_pix_clk period” / “op_pix_clk period” Minimum Frame Time The minimum number of rows in the image is 1, so min_frame_length_lines will always equal (min_frame _blanking_lines + 1).

Table 15. MINIMUM FRAME TIME controlled by the coarse_integration_time register.

could automatically accommodate). global_seq_trigger[0] under software control. and requires a short amount of time.

• global_read_start > global_shutter_start
• global_shutter_start > global_rst_end
• global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted)

Figure 39. Global Reset Bulb associated with the trigger function has been negated. after the negation of FV for the global reset readout phase.

AR0833 supports both analog and digital gain. Table 16. RECOMMENDED ANALOG GAIN SETTING where X is 6, 8, A, C, for Gr, B, R and Gb, respectively. registers mentioned above for gain settings.

to provide a low impedance path for the ground connection. Figure 42. VCM Driver Typical Diagram Table 17. VCM DRIVER TYPICAL

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ELECTRICAL CHARACTERISTICS

Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 45 and Table 18. Table 19 shows the timing specification for the Figure 45. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 18. TWO-WIRE SERIAL REGISTER INTERFACE ELECTRICAL CHARACTERISTICS Table 19. TWO-WIRE SERIAL INTERFACE TIMING SPECIFICATIONS

Table 19. TWO-WIRE SERIAL INTERFACE TIMING SPECIFICATIONS (continued) Table 20. ELECTRICAL CHARACTERISTICS (EXTCLK) performance may not be indicated by the Electrical Characteristics if operated under different conditions.

DATA[4:1]_N) are shown in Table 21. Table 21. ELECTRICAL CHARACTERISTICS (SERIAL MIPI PIXEL DATA INTERFACE) Table 22. DC ELECTRICAL CHARACTERISTICS (CONTROL INTERFACE) correct operation of the AR0833. Table 23. MAXIMUM VALUE RANGES

Table 23. MAXIMUM VALUE RANGES(continued) Table 24. TYPICAL OPERATING CURRENT CONSUMPTION (MIPI)

Table 24. TYPICAL OPERATING CURRENT CONSUMPTION (MIPI) (continued) Table 25. ABSOLUTE MAX VOLTAGES should not be assumed, damage may occur and reliability may be affected.

• MIPI Alliance Standard for CSI−2 version 1.0
• MIPI Alliance Standard for D−PHY version 1.0

www.onsemi.com PACKAGE DIMENSIONS CLCC48 10x10 CASE 848AJ ISSUE O

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