AR0542

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AR0542_DS Rev. H Pub. 5/15 EN 1 ©Semiconductor Components Industries, LLC 2015, 1/4-Inch 5 Mp CMOS Digital Image Sensor AR0542 Datasheet, Rev. H For the latest datasheet, please visit www.onsemi.com

• L o w d a r k c u r r e n t  Simple two-wire serial interface  Auto black level calibration  Support for external LED or Xenon flash  High frame rate preview mode with arbitrary down- size scaling from maximum resolution  Programmable controls: gain, horizontal and vertical blanking, auto black level offset correction, frame size/rate, exposure, left–right and top–bottom image reversal, window size, and panning  Data interfaces: parallel or single/dual lanes serial mobile industry processor interface (MIPI)  On-die phase-locked loop (PLL) oscillator  Bayer pattern down-size scaler  Superior low-light performance  Integrated position and color-based shading correction  7.7 Kb one-time programmable memory (OTPM) for storing shading correction coefficients of three light sources and module information  Extended Flash duration that is up to start of frame readout  On-chip VCM driver

Applications

 Cellular phones  Digital still cameras P C c a m e r a s P D A s General Description The ON Semiconductor AR0542 is a 1/4-inch CMOS active-pixel digital image sensor with a pixel array of 2592H x 1944V (2608H x 1960V including border pix- els). It incorporates sophisticated on-chip camera functions such as windowing, mirroring, column and row skip modes, and snapshot mode. It is programma- ble through a simple two-wire serial interface and has very low power consumption. Note: * Hard Standby by pulling XShutdown LOW. Table 1: Key Performance Parameters Parameter Value Optical format 1/4-inch (4:3) Active imager size 3.63 mm (H) x 2.72(V):4.54 mm diagonal Active pixels 2592H x 1944V Pixel size 1.4 m x 1.4 m Chief ray angle 25.0° Color filter array RGB Bayer pattern Shutter type Electronic rolling shutter (ERS) Input clock frequency 6–27 MHz Maximum data rate Parallel 84 Mbps at 84 MHz PIXCLK MIPI 840 Mbps per lane Frame rate Full resolution (2592 x1944) 15 fps 1080P 19.8 fps (100% FOV, crop to 16:9) 30 fps(77% FOV, crop to 16:9) 720P 30 fps (98% FOV, crop to 16:9, bin2) 60 fps (98% FOV, crop to 16:9, skip2) VGA (640x480) 60 fps (100% FOV, bin2skip2) 115 fps (100% FOV, skip4) ADC resolution 10-bit, on-die Responsivity 0.82 V/lux-sec (550 nm) Dynamic range 66 dB SNR MAX 36.5 dB Supply voltage Digital I/O 1.7–1.9 V (1.8 V nominal) or 2.4–3.1 V (2.8 V nominal) Digital Core 1.15-1.25 V(1.2 V nominal) Analog 2.6–3.1 V (2.8 V nominal) Digital 1.8 V 1.7–1.9 V (1.8 V nominal) Power Consump- tion Full resolution Parallel: 288.2 mW at 70°C (TYP) MIPI: 215 mW at 70°C (TYP) Standby* 25 W at 70°C (TYP) Package Bare die Operating temperature –30°C to +70°C (at junction)

AR0542_DS Rev. H Pub. 5/15 EN 2 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor

Ordering Information

Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0542MBSC25SUD20 5 MP 1/4" CIS RGB Bare die AR0542MBSC25SUFAD-GEVK 5 MP 1/4" CIS DK Demo Kit AR0542MBSC25SUFAH-GEVB 5 MP 1/4" CIS HB Headboard

AR0542_DS Rev. H Pub. 5/15 EN 3 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Table of Contents Table of Contents

AR0542_DS Rev. H Pub. 5/15 EN 5 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor List of Tables List of Tables

AR0542_DS Rev. H Pub. 5/15 EN 6 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor General Description General Description The AR0542 digital image sensor features ON Semiconductor’ s breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte- gration advantages of CMOS. The AR0542 sensor can generate full resolution image at up to 15 frames per second (fps). An on-chip analog-to-digital converter (ADC) generates a 10-bit value for each pixel. Functional Overview The AR0542 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 6 and 27 MHz. The maximum pixel rate is 84 Mp/s, corresponding to a pixel clock rate of 84 MHz. A block diagram of the sensor is shown in Figure 1. Figure 1: Block Diagram The core of the sensor is a 5Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row inte- grate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns are sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel array contains optically active and light-shielded (“dark”) pixels. The dark pixels are used to provide data for on-chip offset-correction algorithms (“black level” control). The sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. These registers can be accessed through a two-wire serial interface. Active-Pixel Sensor (APS) Array Analog Processing ADC Scaler LimiterShading Correction FiFo Timing Control Control Registers Data Out Two-wire Serial Interface Sync Signals

AR0542_DS Rev. H Pub. 5/15 EN 8 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Operating Modes Operating Modes By default, the AR0542 powers up with the serial pixel data interface enabled. The sensor can operate in serial MIPI mode. This mode is preconfigured at the factory. In either case, the sensor has a SMIA-compatible register interface while the two-wire serial device address is compliant with SMIA or MIPI requirements as appropriate. The reset level on the TEST pin must be tied in a way that is compatible with the configured serial interface of the sensor, for instance, TEST = 1 for MIPI. The AR0542 also supports parallel data out in MIPI configuration. Typical configurations are shown in Figure 3 on page 8, Figure 15 on page 9, and Figure 4 on page 10. These operating modes are described in “Control of the Signal Interface” on page 24. For low-noise operation, the AR0542 requires separate power supplies for analog and digital. Incoming digital and analog ground conductors can be tied together next to the die. Both power supply rails should be decoupled from the ground using capacitors as close as possible to the die. Caution ON Semiconductor does not recommend the use of inductance filters on the power supplies or output signals. Figure 3: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies mu st be adequately decoupled. DOUT[9:0] PIXCLK LINE_VALID Analog power Digital core power Digital IO Power Digital REG_IN 1.8V power VDD_IO VDD VDD_PLLVDD_TX VAA VAA_PIXREG_OUTREG_FBREG_IN EXTCLK RESET_BAR XSHUTDOWN TEST From Controller SDATA SCLK 1.5kΩ 1.5kΩ Digital IO power Master Clock (6 - 27 MHz) DGND AGND Digital ground Analog ground Digital Core power Digital 1.8V power 0.1μF0.1μF0.1μF FRAME_VALID To controller Analog power 1.0μF0.1μF

AR0542_DS Rev. H Pub. 5/15 EN 9 ©Semiconductor Components Industries, LLC, 2015.

1. ON Semiconductor recommends a resistor value of 1.5k , but a greater value may be used for
2. V AA and VAA_PIX must be tied together.
3. V DD and VDD_PLL must be tied together
4. The serial interface output pads can be left un connected if the parallel output interface is used.
5. ON Semiconductor recommends having 0.1 F and 1.0F decoupling capacitors for analog power

depending on layout and design considerations.

1. TEST can be tied to D GND (Device ID address = 0x20) or VDD_IO (Device ID address = 0x6C).
2. V DD _TX and REG_IN must be tied together.
3. Refer to the power-up sequence for XSHUTDOWN and RESET_BAR control.
4. The frequency range for EXTCLK must be 6-27 MHz.
5. V PP, which can be used during the module manufacturing process, is not shown in Figure 3. This

pad is left unconnected during normal operation.

1. VCM_ISINK and VCM_GND, which can be used for internal VCM AF driver, are not shown in

Figure 3. VCM_ISINK must be tied to the VCM actuator and VCM_GND must be tied to the DGND

1. The GPI[3:0] pins, which can be ei ther statically pulled HIGH/LOW to be used as module IDs, or they

dynamically controlled, are not shown in Figure 3.

1. The FLASH, which can be used for flash control, is not shown in Figure 3.

AR0542_DS Rev. H Pub. 5/15 EN 11 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Signal Descriptions Signal Descriptions Table 3 provides signal descriptions for AR0542 die. For pad location and aperture infor- mation, refer to the AR0542 die data sheet. Table 3: Signal Descriptions Pad Name Pad Type Description EXTCLK Input Master clock input, 6–27 MHz. RESET_BAR Input Asynchronous active LOW reset. When asserted , data output stops and all internal registers are restored to their factory default settings. XSHUTDOWN Input Asynchronous active LOW reset. When asserted , data output stops and all internal registers are restored to their factory default settings. This pin will turn off the digital power domain and is the lowest power state of the sensor. SCLK Input Serial clock for access to control and status registers. GPI[3:0] Input General purpose inputs. After reset, these pads ar e powered-down by default; this means that it is not necessary to bond to these pads. Any of these pads can be configured to provide hardware control of the standby, output enable, SADDR select, and shutter trigger functions. ON Semiconductor recommends that unused GPI pins be tied to DGND, but can also be left floating. TEST Input Enable manufacturing test modes. Connect to V DD_IO power for the MIPI-configured sensor. SDATA I/O Serial data from reads and writes to control and status registers. VCM_ISINK I/O Connected to VCM actuator. 100mA max. 3.3V max. VCM_GND I/O Connected to D GND. REG_OUT I/O 1.2V on-chip regulator output node. REG_IN I/O On-chip regulator input node. It needs to be connected to external 1.8V. REG_FB I/O This pad is receiving the 1.2V feedback fr om REG_OUT. It needs to be connected to REG_OUT. DATA0_P Output Differential MIPI (sub-LVDS) serial data (positive). DATA0_N Output Differential MIPI (sub-LVDS) serial data (negative). DATA1_P Output Differential MIPI (sub-LVDS) serial data 2nd lane (positive). Can be left floating when using one-lane MIPI serial interface. DATA1_N Output Differential MIPI (sub-LVDS) serial data second lane (negative). Can be left floating when using one-lane MIPI serial interface. CLK_P Output Differential MIPI (sub-LVDS) serial clock/strobe (positive). CLK_N Output Differential MIPI (sub-LVDS) serial clock/strobe (negative). LINE_VALID Output LINE_VALID (LV) output. Qualified by PIXCLK. FRAME_VALID Output FRAME_VALID (FV) output. Qualified by PIXCLK. D OUT[9:0] Output Parallel pixel data output. Qualified by PIXCLK. PIXCLK Output Pixel clock. Used to qualify the LV, FV, and D OUT[9:0] outputs. FLASH Output Flash output. Synchronization pulse for externa l light source. Can be left floating if not used. VPP Supply Power supply used to program one-time programmable (OTP) memory. VDD_TX Supply Digital PHY power supply. Digital power supply for the serial interface. VAA Supply Analog power supply. VAA_PIX Supply Analog power supply for the pixel array. AGND Supply Analog ground. VDD Supply Digital core power supply. VDD_IO Supply I/O power supply. DGND Supply Common ground for digital and I/O. VDD_PLL Supply PLL power supply.

AR0542_DS Rev. H Pub. 5/15 EN 12 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Signal Descriptions Table 3: Signal Descriptions (continued) Pad Name Pad Type Description

AR0542_DS Rev. H Pub. 5/15 EN 15 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status regis- ters within the AR0542. This interface is designed to be compatible with the electrical characteristics and transfer protocols of the two-wire serial register interface specifica- tion. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW—the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0542 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0542 for the MIPI configured sensor are 0x6C

AR0542_DS Rev. H Pub. 5/15 EN 16 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface (write address) and 0x6D (read address) in accordance with the MIPI specification. Alter- nate slave addresses of 0x6E(write address) and 0x6F(read address) can be selected by enabling and asserting the S ADDR signal through the GPI pad. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW . As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indi- cates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’ s internal register address is automatically incre- mented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

AR0542_DS Rev. H Pub. 5/15 EN 19 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Registers Sequential WRITE, Start at Random Location This sequence (Figure 13) starts in the same way as the single WRITE to random location (Figure 12). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 13: Sequential WRITE, Start at Random Location Registers The AR0542 provides a 16-bit register address space accessed through a serial interface (“Two-Wire Serial Register Interface” on page 15). See the AR0542 Register Reference for details. Slave Address 0S A Reg Address[15:8] A A Reg Address[7:0] A Previous Reg Address, N Reg Address, M M+1 M+2 M+1 M+3 A A A M+L-2 M+L-1 M+L A A P Write Data Write Data Write Data Write DataWrite Data

AR0542_DS Rev. H Pub. 5/15 EN 20 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Programming Restrictions Programming Restrictions Table 6 shows a list of programming rules that must be adhered to for correct operation of the AR0542. It is recommended that these rules are encoded into the device driver stack—either implicitly or explicitly. Table 5: Definitions for Programming Rules Name Definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3; xskip = 4 if x_odd_inc = 7 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3; yskip = 4 if y_odd_inc = 7 Table 6: Programming Rules Parameter Minimum Value Maximum Value coarse_integration_time 4* frame_length_lines - coarse_integration_time_max_margin fine_integration_time fine_integration_time_min line_length_pck - fine_integration_time_max_margin digital_gain_* digital_gain_* is an integer multiple of digital_gain_step_size digital_gain_min digital_gain_max frame_length_lines min_frame_leng th_lines max_frame_length_lines line_length_pck min_line_length_pck max_line_length_pck ((x_addr_end - x_addr_start + x_odd_inc)/xskip) + min_line_blanking_pck frame_length_lines ((y_addr_end - y_addr_start + y_odd_inc)/yskip) + min_frame_blanking_lines x_addr_start (must be an even number) x_addr_min x_addr_max x_addr_end (must be an odd number) x_addr_start x_addr_max (x_addr_end – x_addr_start + x_odd_inc) must be positive must be positive y_addr_start (must be an even number) y_addr_min y_addr_max y_addr_end (must be an odd number) y_addr_start y_addr_max (y_addr_end – y_addr_start + y_odd_inc) must be positive must be positive x_even_inc (must be an even number) min_even_inc max_even_inc y_even_inc (must be an even number) min_even_inc max_even_inc x_odd_inc (must be an odd number) min_odd_inc max_odd_inc y_odd_inc (must be an odd number) min_odd_inc max_odd_inc scale_m scaler_m_min scaler_m_max scale_n scaler_n_min scaler_n_max

AR0542: 1/4-Inch CMOS Digital Image Sensor Programming Restrictions AR0542_DS Rev. H Pub. 5/15 EN 21 ©Semiconductor Components Industries, LLC, 2015. Note: *8 is recommended. Output Size Restrictions When the parallel pixel data path is in use, the only restriction on x_output_size is that it must be even (x_output_size[0] = 0), and this restriction is enforced in hardware. When the serial pixel data path is in use, there is an additional restriction that x_out- put_size must be small enough such that the output row time (set by x_output_size, the framing and CRC overhead of 12 bytes and the output clock rate) must be less than the row time of the video array (set by line_length_pck and the video timing clock rate). Effect of Scaler on Legal Range of Output Sizes When the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size generated by the scaler. The AR0542 will operate incorrectly if the x_output_size and y_output_size are significantly larger than the output image. To understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). This situation is shown in Figure 14 on page 21. Figure 14: Effect of Limiter on the Data Path x_output_size (must be even number – this is enforced in hardware) 256 2608 y_output_size (must be even number – this is enforced in hardware) 2 frame_length_lines With subsampling, start and end pixels must be addressed (impact on x/y start/end addresses, function of image orientation bits) Table 6: Programming Rules (continued) Parameter Minimum Value Maximum Value Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 LINE_VALID Scaler output: scaled to half size LINE_VALID PIXEL_VALID Limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 LINE_VALID PIXEL_VALID PIXEL_VALID

AR0542: 1/4-Inch CMOS Digital Image Sensor Programming Restrictions AR0542_DS Rev. H Pub. 5/15 EN 23 ©Semiconductor Components Industries, LLC, 2015. When the scaler is disabled, the data rate in the VT clock domain is constant and uniform during the active period of each pixel array row readout. When the scaler is enabled, the data rate in the VT clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. A key constraint when configuring the clock for the output FIFO is that the frame rate out of the FIFO must exactly match the frame rate into the FIFO. When the scaler is disabled, this constraint can be met by imposing the rule that the row time on the serial data stream must be greater than or equal to the row time at the pixel array. The row time on the serial data stream is calculated from the x_output_size and the data_format (8 or 10 bits per pixel), and must include the time taken in the serial data stream for start of frame/row, end of row/frame and checksum symbols. Caution If this constraint is not met, the FIFO will either underrun or overrun. FIFO underrun or over- run is a fatal error condition that is signaled through the data path_status register (R0x306A). Changing Registers while Streaming The following registers should only be reprogrammed while the sensor is in software standby:  ccp_channel_identifier  ccp_data_format  ccp_signaling_mode v t _ p i x _ c l k _ d i v  vt_sys_clk_div  pre_pll_clk_div  pll_multiplier  op_pix_clk_div o p _ s y s _ c l k _ d i v s c a l e _ m Programming Restrictions when Using Global Reset Interactions between the registers that control the global reset imposes some program- ming restrictions on the way in which they are used; these are discussed in "Analog Gain" on page 51.

AR0542_DS Rev. H Pub. 5/15 EN 24 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface Control of the Signal Interface This section describes the operation of the signal interface in all functional modes. Serial Register Interface The serial register interface uses these signals: S CLK S DATA S ADDR (through the GPI pad) SCLK is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place this signal in High-Z, an external pull-up resistor should be connected on this signal. SDATA is a bidirectional signal. An external pull-up resistor should be connected on this signal. SADDR is a signal, which can be optionally enabled and controlled by a GPI pad, to select an alternate slave address. These slave addresses can also be programmed through R0x31FC. This interface is described in detail in "Two-Wire Serial Register Interface" on page 69. Default Power-Up State The AR0542 sensor can provide two separate interfaces for pixel data: the MIPI serial interface and a parallel data interface. At powerup and after a hard or soft reset, the reset state of the sensor is to enable serial interface when available. The serial pixel data interface uses the following output-only signal pairs: D A T A 0 _ P D A T A 0 _ N C L K _ P C L K _ N The signal pairs are driven differentially using sub-LVDS switching levels. The serial pixel data interface is enabled by default at power up and after reset. The DATA0_P , DATA0_N, CLK_P , and CLK_N pads are turned off if the SMIA serial disable bit is asserted (R0x301A-B[12]=1) or when the sensor is in the soft standby state. In data/clock mode the clock remains HIGH when no data is being transmitted. In data/ strobe mode before frame start, clock is LOW and data is HIGH. When the serial pixel data interface is used, the LINE_VALID, FRAME_VALID, PIXCLK and D OUT[9:0] signals (if present) can be left unconnected.

AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface AR0542_DS Rev. H Pub. 5/15 EN 25 ©Semiconductor Components Industries, LLC, 2015. MIPI Serial Pixel Data Interface The serial pixel data interface uses the following output-only signal pairs: D A T A 0 _ P D A T A 0 _ N D A T A 1 _ P D A T A 1 _ N C L K _ P C L K _ N The signal pairs use both single-ended and differential signaling, in accordance with the MIPI specification. The serial pixel data interface is enabled by default at power up and after reset. The DATA0_P , DATA0_N, DATA1_P , DATA1_N, CLK_P and CLK_N pads are set to the Ultra Low Power State (ULPS) if the SMIA serial disable bit is asserted (R0x301A-B[12]=1) or when the sensor is in the hardware standby or soft standby system states. When the serial pixel data interface is used, the LINE_VALID, FRAME_VALID, PIXCLK and D OUT[9:0] signals (if present) can be left unconnected. The ccp_data_format (R0x0112-3) register can be programmed to any of the following data format settings that are supported:  0x0A0A – Sensor supports RAW10 uncompressed data format. This mode is supported by discarding all but the upper 10 bits of a pixel value.  0x0808 – Sensor supports RAW8 uncompress ed data format. This mode is supported by discarding all but the upper 8 bits of a pixel value.  0x0A08 – Sensor suppor ts RAW8 data format in which an adaptive compression algo- rithm is used to perform 10-bit to 8-bit compression on the upper 10 bits of each pixel value The serial_format register (R0x31AE) register controls which serial interface is in use when the serial interface is enabled (reset_register[12] = 0). The following serial formats are supported:  0x0201 – Sensor supports single-lane MIPI operation  0x0202 – Sensor supports dual-lane MIPI operation Parallel Pixel Data Interface The parallel pixel data interface uses these output-only signals: F V L V P I X C L K OUT[9:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 8 on page 26 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals (DATA0_P , DATA0_N, DATA1_P , DATA1_N, CLK_P , and CLK_N) can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. To use the parallel interface, the V DD_TX pad must be tied to a 1.8V supply. For MIPI sensor, the VDD_IO supply can be set at 1.8V or 2.8V (nominal).

AR0542_DS Rev. H Pub. 5/15 EN 26 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchro- nously between the driven and High-Z under pin or register control, as shown in Table 7. Selection of a pin to use for the OE_N function is described in "General Purpose Inputs" on page 29. Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 8. Table 7: Output Enable Control OE_N Pin Drive Signals R0x301A–B[6] Description Disabled 0 Interface High-Z Disabled 1 Interface driven 1 0 Interface High-Z X1 I n t e r f a c e d r i v e n 0X I n t e r f a c e d r i v e n Table 8: Configuration of the Pixel Data Interface Serializer Disable R0x301 A–B[12] Parallel Enable R0x301A–B[7] Standby End-of-Frame R0x301A–B[4] Description 0 0 1 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.

AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface AR0542_DS Rev. H Pub. 5/15 EN 27 ©Semiconductor Components Industries, LLC, 2015. System States The system states of the AR0542 are represented as a state diagram in Figure 16 and described in subsequent sections. The effect of RESET_BAR on the system state and the configuration of the PLL in the different states are shown in Table 9 on page 28. The sensor’ s operation is broken down into three separate states: hardware standby, software standby, and streaming. The transition between these states might take a certain amount of clock cycles as outlined in Table 9 on page 28. Figure 16: AR0542 System States Powered Off POR active (only if POR is on sensor ) Hardware Standby Internal Initialization Software Standby Streaming Wait For Frame End Powered On POR =0 POR =1 RESET_BAR or XSHUTDOWN transition 1-> 0 (asynchronous from any state) Power supplies turned off (asynchronous from any state) RESET_BAR = 0 or XSHUTDOWN = 0 RESET_BAR = 1 or XSHUTDOWN = 12400 EXTCLK Cycles Initialization TimeoutTwo-wire Serial Interface Write: software_reset = 1 Two-wire Serial Interface Write : mode _select = 1 Two -wire Serial Interface Write: mode_select = 0 Frame in progress PLL Lock PLL not locked PLL locked Software reset initiated (synchronous from any state)

AR0542_DS Rev. H Pub. 5/15 EN 28 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface Power-On Reset Sequence When power is applied to the AR0542, it enters a low-power hardware standby state. Exit from this state is controlled by the later of two events:  The negation of the XSHUTDOWN input.  A timeout of the internal power-on reset circuit. When XSHUTDOWN is asserted it asynchronously resets the sensor, truncating any frame that is in progress. While XSHUTDOWN is asserted (or the internal power-on reset circuit is active) the AR0542 is in its lowest-powered, powered-up state; the internal PLL is disabled, the seri- alizer is disabled and internal clocks are gated off. When the sensor leaves the hardware standby state it performs an internal initialization sequence that takes 2400 EXTCLK cycles. After this, it enters a low-power software standby state. While the initialization sequence is in progress, the AR0542 will not respond to read transactions on its two-wire serial interface. Therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, R0x0000. While the initialization sequence is in progress, the sensor will not respond to its device address and reads from the sensor will result in a NACK on the two- wire serial interface bus. When the sequence has completed, reads will return the opera- tional value for the register (0x4800 if R0x0000 is read). When the sensor leaves software standby mode and enables the VCO, an internal delay will keep the PLL disconnected for up to 1ms so that the PLL can lock. The VCO lock time is 200s (typical), 1ms (maximum). Soft Reset Sequence The AR0542 can be reset under software control by writing “1” to software_reset (R0x0103). A software reset asynchronously resets the sensor, truncating any frame that is in progress. The sensor starts the internal initialization sequence, while the PLL and analog blocks are turned off. At this point, the behavior is exactly the same as for the power-on reset sequence. Signal State During Reset Table 10 shows the state of the signal interface during hardware standby (RESET_BAR asserted) and the default state during software standby (after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values). Table 9: XSHUTDOWN and PLL in System States State XSHUTDOWN PLL Powered off x VCO powered down POR active x Hardware standby 0 Internal initialization Software standby PLL Lock VCO powering up and locking, PLL output bypassed Streaming VCO running, PLL output active Wait for frame end

AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface AR0542_DS Rev. H Pub. 5/15 EN 29 ©Semiconductor Components Industries, LLC, 2015. General Purpose Inputs The AR0542 provides four general purpose inputs. After reset, the input pads associated with these signals are powered down by default, allowing the pads to be left discon- nected/floating. The general purpose inputs are enabled by setting reset_register[8] (R0x301A). Once enabled, all four inputs must be driven to valid logic levels by external signals. The state of the general purpose inputs can be read through gpi_status[3:0] (R0x3026). In addition, each of the following functions can be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input:  Output enable (see “Output Enable Control” on page 26)  Trigger (see the sections below)  Standby functions ADDR selection (see “Serial Register Interface” on page 24) The gpi_status register is used to associate a function with a general purpose input. Table 10: Signal State During Reset Pad Name Pad Type Hardware Standby Software Standby EXTCLK Input Enabled. Must be driven to a valid logic level. XSHUTDOWN/RESET_BAR Input Enabled. Must be driven to a valid logic level. LINE_VALID Output High-Z. Can be left disconnected/floating. FRAME_VALID Output DOUT[9:0] Output PIXCLK Output SCLK Input Enabled. Must be pulled up or driven to a valid logic level. SDATA I/O Enabled as an input. Must be pulle d up or driven to a valid logic level. FLASH Output High-Z. Logic 0. DATA0_P Output MIPI: Ultra Low-Power State (ULPS), represented as an LP-00 state on the wire (both wires at 0V). DATA0_N Output DATA1_P Output DATA1_N Output CLK_P Output CLK_N Output GPI[3:0] Input Powered down. Can be left disconnected/floating. TEST Input Enabled. Must be driven to a logic 1 for a serial MIPI-configured sensor.

AR0542_DS Rev. H Pub. 5/15 EN 30 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Control of the Signal Interface Streaming/Standby Control The AR0542 can be switched between its soft standby and streaming states under pin or register control, as shown in Table 11. Selection of a pin to use for the STANDBY function is described in “General Purpose Inputs” on page 29. The state diagram for transitions between soft standby and streaming states is shown in Figure 16 on page 27. Table 11: Streaming/STANDBY STANDBY Streaming R0x301A–B[2] Description Disabled 0 Soft standby Disabled 1 Streaming X0 S o f t s t a n d b y 0 1 Streaming 1X S o f t s t a n d b y

AR0542_DS Rev. H Pub. 5/15 EN 32 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Clocking ment that the output line time (including the necessary blanking) must be output in a time equal to or less than the time defined by line_length_pck. Although the PLL VCO input frequency range is advertised as 4–24 MHz, superior perfor- mance is obtained by keeping the VCO input frequency as high as possible. The usage of the output clocks is shown below:  clk_pixel (vt_pix_clk / row_speed[2:0]) is used by the sensor core to readout and control the timing of the pixel array. The sensor core produces one 10-bit pixel each vt_pix_clk period. The line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the vt_pix_clk period.  clk_op (op_pix_clk / row_speed[10:8]) is used to load parallel pixel data from the output FIFO (see Figure 35 on page 59) to the serializer. The output FIFO generates one pixel each op_pix_clk period. The pixel is either 8-bit or 10-bit, depending upon the output data format, controlled by R0x0112–3 (ccpdata_format).  op_sys_clk is used to generate the serial data stream on the output. The relationship between this clock frequency and the op_pix_clk frequency is dependent upon the output data format. In Profile 1/2, the output clock frequencies can be calculated as: (EQ 1) (EQ 2) (EQ 3) Note: For dual-lane MIPI interface, clk_pixel_divN = 1. For other interfaces (parallel and sin- gle-lane MIPI), clk_pixel_divN = 2. In Profile 0, RAW10 data format is required. As a result, op_pix_clk_div should be set to 10. Also, due to the inherent design of the AR0542 sensor, vt_pix_clk_div should be set to 5 for profile 0 mode. clk_pix_freq_mhz = ext_clk_freq_mhz pll_multiplier clk_pixel_divN clk_op_freq_mhz = ext_clk_freq_mhz pll_multiplier op_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier

AR0542: 1/4-Inch CMOS Digital Image Sensor Clocking AR0542_DS Rev. H Pub. 5/15 EN 33 ©Semiconductor Components Industries, LLC, 2015. PLL Clocking The PLL divisors should be programmed while the AR0542 is in the software standby state. After programming the divisors, it is necessary to wait for the VCO lock time before enabling the PLL. The PLL is enabled by entering the streaming state. An external timer will need to delay the entrance of the streaming mode by 1 millisecond so that the PLL can lock. The effect of programming the PLL divisors while the AR0542 is in the streaming state is undefined. Influence of ccp_data_format R0x0112–3 (ccp_data_format) controls whether the pixel data interface will generate 10 or 8 bits per pixel. When the pixel data interface is generating 8 bits per-pixel, op_pix_clk_div must be programmed with the value 8. When the pixel data interface is generating 10 bits per pixel, op_pix_clk_div must be programmed with the value 10. Influence of ccp2_signalling_mode R0x0111 (ccp2_signalling_mode) controls whether the serial pixel data interface uses data/strobe signaling or data/clock signaling. When data/clock signaling is selected, the pll_multiplier supports both odd and even values. When data/strobe signaling is selected, the pll_multiplier only supports even values; the least significant bit of the programmed value is ignored and treated as “0.” This behavior is a result of the implementation of the CCP serializer and the PLL. When the serializer is using data and strobe signaling, it uses both edges of the op_sys_clk, and therefore that clock runs at one half of the bit rate. All of the programmed divisors are set up to make this behavior invisible. For example, when the divisors are programmed to generate a PLL output of 640 MHz, the actual PLL output is 320MHz, but both edges are used. When the serializer is using data and clock signaling, it uses a single edge on the op_sys- _clk, and therefore that clock runs at the bit rate. To disguise this behavior from the programmer, the actual PLL multiplier is right-shifted by one bit relative to the programmed value when ccp2_signalling_mode selects data/strobe signaling. Clock Control The AR0542 uses an aggressive clock-gating methodology to reduce power consump- tion. The clocked logic is divided into a number of separate domains, each of which is only clocked when required. When the AR0542 enters a low-power state, almost all of the internal clocks are stopped. The only exception is that a small amount of logic is clocked so that the two-wire serial interface continues to respond to read and write requests.

AR0542_DS Rev. H Pub. 5/15 EN 34 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Shading Correction (SC) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The AR0542 has an embedded shading correction module that can be programmed to counter the shading effects on each individual Red, GreenB, GreenR, and Blue color signal. The Correction Function Color-dependent solutions are calibrated using the sensor, lens system and an image of an evenly illuminated, featureless gray calibration field. From the resulting image, register values for the color correction function (coefficients) can be derived. The correction functions can then be applied to each pixel value to equalize the response across the image as follows: (EQ 4) where P are the pixel values and f is the color dependent correction functions for each color channel. Each function includes a set of color-dependent coefficients defined by registers R0x3600–3726. The function's origin is the center point of the function used in the calcu- lation of the coefficients. Using an origin near the central point of symmetry of the sensor response provides the best results. The center point of the function is determined by ORIGIN_C (R0x3782) and ORIGIN_R (R0x3784) and can be used to counter an offset in the system lens from the center of the sensor array. Pcorrected row, col = Psensor(row,col) * f(row,col)

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 35 ©Semiconductor Components Industries, LLC, 2015. One-Time Programmable Memory (OTPM) The AR0542 features 7.7Kb of one-time programmable memory (OTPM) for storing shading correction coefficients, individual module ID, and sensor specific information. It takes roughly 5Kb (102 registers x 16-bits x 3 sets = 4896 bits) to store three sets of illu- mination-dependent shading coefficients. The OTPM array has a total of 201 accessible row-addresses, with each row having two 20-bit words per row. In each word, 16 bits are used for data storage, while the remaining 4 bits are used by the error detection and correction scheme. OTP memory can be accessed through two-wire serial interface. The AR0542 uses the auto mode for fast OTPM programming and read operations. During the programming process, a dedicated high voltage pin (V PP) needs to be supplied with a 6.5V +3% voltage to perform the anti-fusing operation, and a slew rate of 1 V/s or slower is recommended for VPP supply. Instantaneous VPP cannot exceed 9V at any time. The completion of the programming process will be communicated by a register through the two-wire serial interface. Because this programming pin needs to sustain a higher voltage than other input/ output pins, having a dedicated high voltage pin (V PP) minimizes the design risk. If the module manufacturing process can probe the sensor at the die or PCB level (that is, supply all the power rails, clocks, and two-wire serial interface signals), then this dedi- cated high voltage pin does not need to be assigned to the module connector pinout. However, if the V PP pin needs to be bonded out as a pin on the module, the trace for VPP needs to carry a maximum of 1mA – for programming only. This pin should be left floating once the module is integrated to a design. If the VPP pin does not need to be bonded-out as a pin on the module, it should be left floating inside the module. The programming of the OTPM requires the sensor to be fully powered and remain in software standby with its clock input applied. The information will be programmed through the use of the two-wire serial interface, and once the data is written to an internal register, the programming host machine will apply a high voltage to the programming pin, and send a program command to initiate the anti-fusing process. After the sensor has finished programming the OTPM, a status bit will be set to indicate the end of the programming cycle, and the host machine can poll the setting of the status bit through the two-wire serial interface. Only one programming cycle for the 16- bit word can be performed. Reading the OTPM data requires the sensor to be fully powered and operational with its clock input applied. The data can be read through a register from the two-wire serial interface. Programming the OTPM Program the AR0542 OTPM as follows: 1. Apply power to all the power rails of the sensor (V DD_IO, VAA, VAA_PIX, and Digital 1.8V). – Aptina recommends setting V AA to 3.1V during the programming process. All other supplies must be at their nominal voltage. – Ensure that the V PP pin is floating during sensor power-up. 2. Provide an EXTCLK clock input (12 MHz is recommended). 3. Set R0x301A = 0x10D8, to put sensor in the soft standby mode. 4. Set R0x3064[9] =1 to bypass PLL. 5. Set R0x3054[8]=1 6. Write data (102 words for one set of LSC coefficients) into the OTPM data registers (R0x3800–R0x38CA for one set of LSC coefficients).

AR0542_DS Rev. H Pub. 5/15 EN 36 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor

1. Set OTPM start address register R0x3050[15:8] = 0 to program the array with the first batch of data. Note: When programming the second batch of data, set the start address to 128 (consider- ing that all the previous 0–127 locations are already written to by the data registers 0– 255), otherwise the start address should be set accordingly. 8. Set R0x3054[9] = 0 to ensure that the error checking and correction is enabled. 9. Set the length register (R0x304C [7:0]) ac cordingly, depending on the number of OTM data registers that are filled in (0x66 for 102 words). It may take about 500ms for one set of LSC (102 words). 10. Set R0x3052 = 0x2504 (OTPM_CONFIG) 11. Ramp up V PP to 6.5V . The recommended slew rate for VPP is 1 V/s or slower. 12. Set the otpm_control_auto_wr_start bi t in the otpm_manual_control register R0x304A[0] = 1, to initiate the auto program sequence. The sensor will now program the data into the OTPM starting with the location specified by the start address. 13. Poll OTPM_Control_Auto_WR_end (R0x304A [1 ]) to determine when the sensor is fin- ished programming the word. 14. Repeat steps 13 and 14. 15. Remove the high voltage (V PP) and float the VPP pin. Reading the OTPM Read the AR0542 OTPM as follows: 1. Perform the proper reset sequence to the sensor by setting R0x0103 = 1. 2. Set OTPM_CONFIG register R0x3052 = 0x2704. 3. Set R0x3054[8] = 1. 4. Program R0x3050[15:8] with the appropriate value to specify the start address (0x0 for address 0). 5. Program R0x304C [7:0] with the appropriate value to specify the length (number of data registers to be read back, starting from the specified start address – 0x66 for 102 words). 6. Initiate the auto read sequence by se tting the otpm_control_auto_read_start bit R0x304A[4] = 1. 7. Poll the otpm_control_auto_rd_end bit (R0x 304A[5]) to determine when the sensor is finished reading the word(s). Data can now be read back from the otpm_data registers (R0x3800–R0x39FE). 8. Verify that the read data from the OTPM_DATA registers are the expected data.

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 37 ©Semiconductor Components Industries, LLC, 2015. Image Acquisition Mode The AR0542 supports the electronic rolling shutter (ERS) mode. This is the normal mode of operation. When the AR0542 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (expo- sure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0542 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See “Changes to Integration time” in the AR0542 Register Reference. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. For both parallel and serial MIPI interfaces, the output image size is controlled by the x_output_size and y_output_size registers. Pixel Border The default settings of the sensor provide a 2592H x 1944V image. A border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_output_size, and y_output_size registers accordingly. Readout Modes Horizontal Mirror When the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end and ends at x_addr_start. Figure 18 on page 37 shows a sequence of 6 pixels being read out with hori- zontal_mirror = 0 and horizontal_mirror = 1. Changing horizontal_mirror causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. Figure 18: Effect of horizontal_mirror on Readout Order LINE_VALID horizontal_mirror = 0 DOUT[9:0] horizontal_mirror = 1 DOUT[9:0]

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 41 ©Semiconductor Components Industries, LLC, 2015. Programming Restrictions when Subsampling When subsampling is enabled as a viewfinder mode and the sensor is switched back and forth between full resolution and subsampling, Aptina recommends that line_length_pck be kept constant between the two modes. This allows the same integra- tion times to be used in each mode. When subsampling is enabled, it may be necessary to adjust the x_addr_end, x_ad- dr_star, y_addr_start, and y_addr_end settings: the values for these registers are required to correspond with rows/columns that form part of the subsampling sequence. The adjustment should be made in accordance with these rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2  x_addr_start should be a multiple of x_skip_factor * 4  (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor * 4  (y_addr_end - y_addr_start + y_odd_inc) sh ould be a multiple of y_skip_factor * 4 The number of columns/rows read out with subsampling can be found from the equa- tion below:  columns/rows = (addr_end - addr_start + odd_inc) / skip_factor Example: The sensor is set up to give out a full resolution 2592 x 1944 image: [full resolution starting address with (8,8)] To halve the resolution in each direction (1296 x 972), the registers need to be repro- grammed as follows: REG = 0x0104, 1 / /GROUPED_PARAMETER_HOLD REG = 0x0382, 1 / /X_ODD_INC REG = 0x0386, 1 / /Y_ODD_INC REG = 0x0344, 8 / /X_ADDR_START REG = 0x0346, 8 / /Y_ADDR_START REG = 0x0348, 2599 / /X_ADDR_END REG = 0x034A, 1951 / /Y_ADDR_END REG = 0x034C, 2592 / /X_OUTPUT_SIZE REG = 0x034E, 1944 / /Y_OUTPUT_SIZE REG = 0x0104, 0 / /GROUPED_PARAMETER_HOLD

AR0542_DS Rev. H Pub. 5/15 EN 42 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor [2 x 2 skipping starting address with (8,8)] To quarter the resolution in each direction (648 x 486), the registers need to be repro- grammed as follows: [4 x 4 skipping starting address with (8,8)] Table 12 shows the row or column address sequencing for normal and subsampled readout. In the 2X skip case, there are two possible subsampling sequences (because the subsampling sequence only reads half of the pixels) depending upon the alignment of the start address. Similarly, there will be four possible subsampling sequences in the 4X skip case (though only the first two are shown in Table 12). REG = 0x0104, 1 / /GROUPED_PARAMETER_HOLD REG = 0x0382, 3 / /X_ODD_INC REG = 0x0386, 3 / /Y_ODD_INC REG = 0x0344, 8 / /X_ADDR_START REG = 0x0346, 8 / /Y_ADDR_START REG = 0x0348, 2597 / /X_ADDR_END REG = 0x034A, 1949 / /Y_ADDR_END REG = 0x034C, 1296 / /X_OUTPUT_SIZE REG = 0x034E, 972 / /Y_OUTPUT_SIZE REG = 0x0104, 0 / /GROUPED_PARAMETER_HOLD REG = 0x0104, 1 / /GROUPED_PARAMETER_HOLD REG = 0x0382, 7 / /X_ODD_INC REG = 0x0386, 7 / /Y_ODD_INC REG = 0x0344, 8 / /X_ADDR_START REG = 0x0346, 8 / /Y_ADDR_START REG = 0x0348, 2593 / /X_ADDR_END REG = 0x034A, 1945 / /Y_ADDR_END REG = 0x034C, 648 / /X_OUTPUT_SIZE REG = 0x034E, 486 / /Y_OUTPUT_SIZE REG = 0x0104, 0 / /GROUPED_PARAMETER_HOLD Table 12: Row Address Sequencing During Subsampling odd_inc = 1—Normal odd_inc = 3, 2X Skip odd_inc = 7, 4X Skip start = 0 start = 0 start = 0 00 0 11 1 88 8 99 9

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 45 ©Semiconductor Components Industries, LLC, 2015. For a given column n, there is only one other column, n_bin, that can be binned with, because of physical limitations in the column readout circuitry. The possible address sequences are shown in Table 13. There are no physical limitations on what can be binned together in the row direction. A given row n will always be binned with row n+2 in 2X subsampling mode and with row n+4 in 4X subsampling mode. Therefore, which rows get binned together depends upon the alignment of y_addr_start. The possible sequences are shown in Table 14. Table 13: Column Address Sequencing During Binning odd_inc = 1—Normal odd_inc = 3, 2X Bin odd_inc = 7, 2X Skip + 2XBin x_addr_start = 0 x_addr_start = 0 x_addr_start = 0 00 / 2 0 / 4 11 / 3 1 / 5 8 8/10 8/12 9 9/11 9/13 12 12/14 13 13/15 Table 14: Row Address Sequencing During Binning odd_inc = 1—Normal odd_inc = 3, 2X Bin odd_inc = 7, 2X Skip + 2X Bin x_addr_start = 0 x_addr_start = 0 x_addr_start = 0 00 / 2 0 / 4 11 / 3 1 / 5 8 8/10 8/12 9 9/11 9/13 12 12/14 13 13/15

AR0542_DS Rev. H Pub. 5/15 EN 46 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Programming Restrictions when Binning Binning requires different sequencing of the pixel array and imposes different timing limits on the operation of the sensor. In particular, xy-binning requires two read opera- tions from the pixel array for each line of output data, which has the effect of increasing the minimum line blanking time. The SMIA specification cannot accommodate this variation because its parameter limit registers are defined as being static. As a result, when xy-binning is enabled, some of the programming limits declared in the parameter limit registers are no longer valid. In addition, the default values for some of the manufacturer-specific registers need to be reprogrammed. See section "Minimum Frame Time" on page 48, section "Minimum Row Time" on page 48, and section "Fine Integration Time Limits" on page 49. Scaler Scaling is a “zoom out” operation to reduce the size of the output image while covering the same extent as the original image. Each scaled output pixel is calculated by taking a weighted average of a group of input pixels which is composed of neighboring pixels. The input and output of the scaler is in Bayer format. When compared to skipping, scaling is advantageous because it uses all pixel values to calculate the output image which helps avoid aliasing. Also, it is also more convenient than binning because the scale factor varies smoothly and the user is not limited to certain ratios of size reduction. The AR0542 sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. (Scale Factor = Scale_n/ scale_m = 16/scale_m) (EQ 5) The scaling factor, programmable in 1/16 steps, is used for horizontal and vertical scalers. The scale factor is determined by:  n, which is fixed at 16  m, which is adjustable with register R0x0404  Legal values for m are 16 through 256, giving the user the ability to scale from For example, when horizontal and vertical scaling is enabled for a 1:2 scale factor, an image is reduced by half in both the horizontal and vertical directions. This results in an output image that is one-fourth of the original image size. This can be achieved with the following register settings: R0x0400 = 0x0002 // horizontal and vertical scaling mode R0x0402 = 0x0020 // scale factor m = 32 Table 15: Readout Modes Readout Modes x_odd_inc, y_odd_inc xy_bin 2x skip 3 0 2x bin 3 1 4x skip 7 0 2x skip + 2x bin 7 1

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 47 ©Semiconductor Components Industries, LLC, 2015. Frame Rate Control The formulas for calculating the frame rate of the AR0542 are shown below. The line length is programmed directly in pixel clock periods through register line_length_pck. For a specific window size, the minimum line length can be found from in Equation 6: (EQ 6) Note that line_length_pck also needs to meet the minimum line length requirement set in register min_line_length_pck. The row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in “Minimum Row Time” on page 48. The frame length is programmed directly in number of lines in the register frame_line_length. For a specific window size, the minimum frame length can be found in Equation 7: (EQ 7) The frame rate can be calculated from these variables and the pixel clock speed as shown in Equation 8: (EQ 8) If coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. minimum line_length_pck x_addr_end - x_addr_start 1+ = minimum frame_length_lines y_addr_end - y_addr_start 1+ = frame rate vt_pixel_clock_mhz x 1 x 10 6

AR0542_DS Rev. H Pub. 5/15 EN 48 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor The minimum row time and blanking values with default register settings are shown in Table 16. In addition, enough time must be given to the output FIFO so it can output all data at the set frequency within one row time. There are therefore three checks that must all be met when programming line_length_pck:  line_length_pck > min_line_length_pck in Table 16.  line_length_pck > (x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck in Table 16.  The row time must allow the FIFO to output all data during each row. That is, line_length_pck > (x_output_size * 2 + 0x005E) * "vt_pix_clk period" / "op_pix_clk period" Minimum Frame Time The minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2).Integration Time The integration (exposure) time of the AR0542 is controlled by the fine_integration_time and coarse_integration_time registers. The limits for the fine integration time are defined by: fine_integration_time_min < fine_integration_time < (line_length_pck – (EQ 9) fine_integration_time_max_margin) The limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (EQ 10) Table 16: Minimum Row Time and Blanking Numbers No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 min_line_blanking_pck 0x044E 0x02B6 0x01E8 0x073C 0x040C 0x0274 min_line_length_pck 0x0590 0x03F8 0x0330 0x0940 0x0550 0x03B8 Table 17: Minimum Frame Time and Blanking Numbers No Row Binning Row Binning min_frame_blanking_lines 0x004D 0x0049 min_frame_length_lines 0x005D 0x0059

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 49 ©Semiconductor Components Industries, LLC, 2015. The actual integration time is given by: (EQ 11) It is required that: coarse_integration_time  (frame_length_lines – coarse_integration_time_max_margin) (EQ 12) If this limit is broken, the frame time will automatically be extended to coarse_integra- tion_time + coarse_integration_time_max_margin to accommodate the larger integra- tion time. In binning mode, frame_length_lines should be set larger than coarse_integration_time by at least 3 to avoid column imbalance artifact. Fine Integration Time Limits The limits for the fine_integration_time can be found from fine_integration_time_min and fine_integration_time_max_margin. Values for different mode combinations are shown in Table 18. fine_correction For the fine_integration_time limits, the fine_correction constant will change with the pixel clock speed and binning mode. It is necessary to change fine_correction (R0x3010) when binning is enabled or the pixel clock divider (row_speed[2:0]) is used. The corre- sponding fine_correction values are shown in Table 19. Table 18: fine_integration_time Limits No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 fine_integration_time_min 0x02CE 0x0178 0x006E 0x0570 0x02C8 0x00C2 fine_integration_time_max_margin 0x0159 0x00AD 0x00AD 0x02B9 0x015D 0x0149Table 19: fine_correction Values No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 fine_correction 0x00A0 0x004A 0x001F 0x0140 0x009A 0x0047 integration_time coarse_integration_time*line_length_pck fine_integration_time+

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 51 ©Semiconductor Components Industries, LLC, 2015. Analog Gain The following sections describe the Aptina gain model for AR0542 and the different gain stages and gain control. Using Per-color or Global Gain Control The read-only analogue_gain_capability register returns a value of “1,” indicating that the AR0542 provides per-color gain control. However, the AR0542 also provides the option of global gain control. Per-color and global gain control can be used interchange- ably. A write to a global gain register is aliased as a write of the same data to the four associated color-dependent gain registers. A read from a global gain register is aliased to a read of the associated greenR gain register. Table 20: Gain Registers Register Bits Default Name Frame Sync'd Bad Frame 12382 R0x305E 15:0 0x1050 global_gain (R/W) NN 15:1 0x0001 digital_gain Digital Gain. Legal values 1-7. 11:1 0x0000 col_gain This is the column gain Valid values for bits[11:10] are: 00: 1x 01: 3x 10: 2x 11: 4x YY 9:8 0x0000 asc1_gain This is the ASC1 gain Valid values for bits[9:8] are: 00: 1x 01: 1.3x 10: 2x 11: 4x 7 0x0000 Reserved YN 6:0 0x0050 initial_gain Initial gain = bits [6:0] * 1/32. Gain = Column Gain*ASC1 Gain* Initial_gain Y Y

AR0542_DS Rev. H Pub. 5/15 EN 52 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor The Aptina gain model uses these registers to set the analog gain:  global_gain g r e e n 1 _ g a i n  red_gain  blue_gain g r e e n 2 _ g a i n The AR0542 uses 11 bits analog gain control. The analog gain is given by: (EQ 13) As a result, the step size varies depending upon which range the gain is in. Many of the possible gain settings can be achieved in different ways. However, the recommended gain setting is to use the Column_gain as much as possible instead of using ASC1_gain and Initial_gain for the desired gain setting, which will result lower noise. for the fine step, the Initial gain should be used with Column_gain and ASC1_gain. The recommended minimum analog gain for AR0542 is 1.6x(R0x305E = 0x1127). Table 21 provides the gain usage table that is a guide to program a specific gain value while optimizing the noise performance from the sensor. Valid Values Column_gain(<color>_gain[11:10]) ASC_gain(<color>_gain[9:8] 2’b00 1X 1X 2’b01 3X 1.3X 2’b10 2X 2X 2’b11 4X – Table 21: Gain Usage Total Gain Column Gain ASC1 Gain Initial Gain 1.0  Gain < 1.33 1 1 1.0  init < 1.33 2.0  Gain < 2.66 2 1 1.0  init < 1.33 3.0  Gain < 4.0 3 1 1.0  init < 1.33 4.0  Gain < 5.3 4 1 1.0 init < 1.33 8.0  Gain < 32.0 4 2 1.0 init < 4.0 Total gain Column_gain ASC1_gain Initial_gain= <color>_gain[11:10] <color>_gain[9:8] <color>_gain[6:0]

AR0542: 1/4-Inch CMOS Digital Image Sensor Sensor Core Digital Data Path AR0542_DS Rev. H Pub. 5/15 EN 53 ©Semiconductor Components Industries, LLC, 2015. Sensor Core Digital Data Path Test Patterns The AR0542 supports a number of test patterns to facilitate system debug. Test patterns are enabled using test_pattern_mode (R0x0600–1). The test patterns are listed in Table 22. Test patterns 0–3 replace pixel data in the output image (the embedded data rows are still present). Test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). For all of the test patterns, the AR0542 registers must be set appropriately to control the frame rate and output timing. This includes: A l l c l o c k d i v i s o r s  x_addr_start  x_addr_end  y_addr_start  y_addr_end  frame_length_lines l i n e _ l e n g t h _ p c k x _ o u t p u t _ s i z e  y_output_size Table 22: Test Patterns test_pattern_mode Description

0 Normal operation: no test pattern

1 Solid color

2 100% color bars 3F a d e - t o - g r a y c o l o r b a r s

4 PN9 link integrity pattern (only on sensors with serial interface)

256 Walking 1s (10-bits)

257 Walking 1s (8-bits)

AR0542_DS Rev. H Pub. 5/15 EN 54 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Sensor Core Digital Data Path Effect of Data Path Processing on Test Patterns Test patterns are introduced early in the pixel data path. As a result, they can be affected by pixel processing that occurs within the data path. This includes:  Noise cancellation  Black pedestal adjustment  Lens and color shading correction These effects can be eliminated by the following register settings:  R0x30C0–1[0] = 1  R0x31E0–1[0] = 0  R0x301A–B[3] = 0 (enable writes to data pedestal)  R0x301E–F = 0x0000 (set data pedestal to “0”)  R0x3780[15] = 0 (turn off lens/color shading correction) Solid Color Test Pattern In this mode, all pixel data is replaced by fixed Bayer pattern test data. The intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenR, test_data_blue, test_data_greenB). 100% Color Bars Test Pattern In this test pattern, shown in Figure 30 on page 55, all pixel data is replaced by a Bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). Each bar is 1/8 of the width of the pixel array (2592/8 = 324 pixels). The pattern repeats after 8 * 324 = 2592 pixels. Each color component of each bar is set to either 0 (fully off) or 0x3FF (fully on for 10-bit data). The pattern occupies the full height of the output image. The image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. The color-bar pattern is discon- nected from the addressing of the pixel array, and will therefore always start on the first visible pixel, regardless of the value of x_addr_start. The number of colors that are visible in the output is dependent upon x_addr_end - x_addr_start and the setting of x_out- put_size: the width of each color bar is fixed at 324 pixels. The effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. Any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. The state of vertical_flip has no effect on this test pattern. The effect of subsampling, binning and scaling of this test pattern is undefined. Test patterns should be analyzed at full resolution only.

AR0542: 1/4-Inch CMOS Digital Image Sensor Sensor Core Digital Data Path AR0542_DS Rev. H Pub. 5/15 EN 55 ©Semiconductor Components Industries, LLC, 2015. Figure 30: 100 Percent Color Bars Test Pattern Fade-to-gray Color Bars Test Pattern In this test pattern, shown in Figure 31 on page 56, all pixel data is replaced by a Bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). Each bar is 1/8 of the width of the pixel array (2592/8 = 324 pixels). The test pattern repeats after 2592 pixels. Each color bar fades vertically from zero or full intensity at the top of the image to 50 percent intensity (mid-gray) on the last row of the pattern. Each color bar is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps. The speed at which each color fades is dependent on the sensor's data width and the height of the pixel array. We want half of the data range (from 100 or 0 to 50 percent) difference between the top and bottom of the pattern. Because of the Bayer pattern, each state must be held for two rows. The rate-of-fade of the Bayer pattern is set so that there is at least one full pattern within a full-sized image for the sensor. Factors that affect this are the resolution of the ADC (10-bit or 12-bit) and the image height. The image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. The color-bar pattern starts at the first column in the image, regardless of the value of x_addr_start. The number of colors that are visible in the output is dependent upon x_addr_end – x_addr_start and the setting of x_output_size: the width of each color bar is fixed at 324 pixels. The effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. Any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. The effect of subsampling, binning, and scaling of this test pattern is undefined. T ST patterns should be analyzed at full resolution only. Horizontal mirror = 0 Horizontal mirror = 1

AR0542_DS Rev. H Pub. 5/15 EN 56 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Sensor Core Digital Data Path Figure 31: Fade-to-Gray Color Bars Test Pattern PN9 Link Integrity Pattern The PN9 link integrity pattern is intended to allow testing of a serial pixel data interface. Unlike the other test patterns, the position of this test pattern at the end of the data path means that it is not affected by other data path corrections (row noise, pixel defect correction and so on). This test pattern provides a 512-bit pseudo-random test sequence to test the integrity of the serial pixel data output stream. The polynomial x9 + x5 + 1 is used. The polynomial is initialized to 0x1FF at the start of each frame. When this test pattern is enabled:  The embedded data rows are disabled an d the value of frame_format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present.  The whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is filled with data from the PN9 sequence.  The output data format is (effectively) fo rced into RAW10 mode regardless of the state of the ccp_data_format register. Before enabling this test pattern the clock divisors must be configured for RAW10 opera- tion (op_pix_clk_div = 10). Horizontal mirror = 0, Vertical flip = 0 Horizontal mirror = 0, Vertical flip = 1 Horizontal mirror = 1, Vertical flip = 0 Horizontal mirror = 1, Vertical flip = 1

AR0542: 1/4-Inch CMOS Digital Image Sensor Digital Data Path AR0542_DS Rev. H Pub. 5/15 EN 59 ©Semiconductor Components Industries, LLC, 2015. Digital Gain Integer digital gains in the range 1–7 can be programmed. Pedestal This block adds the value from R0x0008–9 or (data_pedestal_) to the incoming pixel value. The data_pedestal register is read-only by default but can be made read/write by clearing the lock_reg bit in R0x301A–B. The only way to disable the effect of the pedestal is to set it to 0. Digital Data Path The digital data path after the sensor core is shown in Figure 35. Figure 35: Data Path Embedded Data Format and Control When the serial pixel data path is selected, the first two rows of the output image contain register values that are appropriate for the image. The 12-bit format places the data byte in bits [11:4] and sets bits [3:0] to a constant value of 0101. Some register values are dynamic and may change from frame to frame. Additional information on the format of the embedded data can be located in the SMIA specification. Scaler Serial Framers 2-1 Lane Converter Output BufferLimiter Compression Registers Embedded Data Serial Pixel Data Interface Interface with sensor_core Parallel Pixel Data Interface Includes false synchronization code removal and PN9 test sequence generation

AR0542_DS Rev. H Pub. 5/15 EN 60 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications Timing Specifications Power-Up Sequence Two power-up sequences are recommended for the AR0542 based on the XSHUTDOWN and RESET_BAR one-pin (pin-constrained mode) or two-pin (pin-unconstrained mode) control mode. XSHUTDOWN/RESET_BAR Pin-Constrained Mode 1. Turn on V DD_IO power supply. 2. After 0-10ms, Turn on Digital REG_IN (1.8V) power supply. 3. After 0-10ms, enable EXTCLK. 4. After 0-100ms, assert XSHUTDOWN/RESET_BAR (High). 5. After 1ms - 500ms, turn on V AA/VAA_PIX power supplies. 6. Wait 1ms for internal initialization into soft standby. 7. Configure PLL, output and image settings to desired values. 8. Set mode_select = 1 (R0x0100). 9. Wait 1ms for the PLL to lock before streaming state is reached. Figure 36: Power-Up Sequence with Pin-Constrained Mode Note: If the AR0542 two-wire serial interface is also used for communication with other devices, the sta- tus of SDATA during power-up needs to be considered at the system level due to the sensor's inter- action during this time (t0 to t3) driving it to the low state; if the AR0542 two-wire serial interface is used for a dedicated point-point connection to the host, no additional considerations apply. Table 23: Power-Up Signal Timing with Pin-constrained Mode Parameter Symbol Min Typ Max Unit VDD_IO to Digital REG_IN 1.8V t1 0 - 10 ms Digital REG_IN 1.8V to enable EXTCLK t2 0 - 10 ms Enable EXTCLK to hard reset assertion t3 0 - 100 ms Hard reset to VAA/VAA_PIX t4 1 - 500 ms Internal initialization t5 1 - - ms VAA, VAA_PIX (2.8V) XSHUTDOWN/ RESET_BAR Digital REG_IN (1.8V) t2EXTCLK Operating State Hard Reset Internal INIT Soft Standby PLL Lock Streaming VDD_IO t5 t6

AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications AR0542_DS Rev. H Pub. 5/15 EN 61 ©Semiconductor Components Industries, LLC, 2015. XSHUTDOWN/RESET_BAR Pin-unconstrained Mode 1. Turn on V DD_IO power supply. 2. After 0-10ms, turn on Digital REG_IN power supply. 3. After 1-500ms, turn on V AA/VAA_PIX power supplies and enable EXTCLK. 4. After 1ms, assert XSHUTDOWN (High). 5. After 1ms, assert RESET_BAR (High). 6. Wait 1ms for internal initialization into soft standby. 7. Configure PLL, output and image settings to desired values. 8. Set mode_select = 1 (R0x0100). 9. Wait 1ms for the PLL to lock before streaming state is reached. Figure 37: Power-Up Sequence with Pin-unconstrained Mode Note: If the AR0542 two-wire serial interface is also used for communication with other devices, the sta- tus of SDATA during power-up needs to be considered at the system level due to the sensor's inter- action during this time (t0 to t3) driving it to the low state; if the AR0542 two-wire serial interface is used for a dedicated point-point connection to the host, no additional considerations apply. PLL lock time t6 1 - - ms Table 24: Power-Up Signal Timing with Pin-unconstrained Mode Parameter Symbol Min Typ Max Unit VDD_IO to Digital REG_IN 1.8V t1 0 - 10 ms Digital REG_IN (1.8V) to VAA, VAA_PIX (2.8V) t2 1 - 500 ms Running EXTCLK to XSHUTDOWN assertion t3 1 - - ms XSHUTDOWN high to RESET_BAR assertion t4 1 - - ms Table 23: Power-Up Signal Timing with Pin-constrained Mode Parameter Symbol Min Typ Max Unit VAA, VAA_PIX (2.8V) XSHUTDOWN Digital REG_IN (1.8V) EXTCLK Operating State Hard Reset Internal INIT Soft Standby PLL Lock Streaming VDD_IO t5 t6 RESET_BAR

AR0542_DS Rev. H Pub. 5/15 EN 62 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications Power-Down Sequence The recommended power-down sequence for the AR0542 is shown in Figure 38. The available power supplies—V DD_IO, Digital 1.8V , VAA, VAA_PIX—can be turned off at the same time or have the separation specified below. 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. Assert hard reset by setting XS HUTDOWN/RESET_BAR to a logic “0.” 4. Turn off the V AA/VAA_PIX power supplies. 5. After 0 –500ms, turn off Digital 1.8V power supply. 6. After 0 –500ms, turn off VDD_IO power supply. Figure 38: Power-Down Sequence Internal initialization t5 1 - - ms PLL lock time t6 1 - - ms Table 25: Power-Down Sequence Definition Symbol Min Typ Max Unit XSHUTDOWN/RESET_BAR to VAA/VAA_PIX t10 – 5 0 0 m s VAA/VAA_PIX to Digital 1.8V time t20 – 5 0 0 m s Table 24: Power-Up Signal Timing with Pin-unconstrained Mode Parameter Symbol Min Typ Max Unit Turning Off Power SuppliesHard ResetSoftware StandbyStreaming Not to scale VDD_IO Digital 1.8V VAA, VAA_PIX EXTCLK XSHUTDOWN/RESET_BAR

AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications AR0542_DS Rev. H Pub. 5/15 EN 63 ©Semiconductor Components Industries, LLC, 2015. Hard Standby The hard standby state is reached by the assertion of the XSHUTDOWN pad. There are two hard standby entering and exiting sequences for the AR0542 based on the XSHUT- DOWN and RESET_BAR one-pin (pin-constrained mode) or two-pin (pin-uncon- strained mode) control mode. Register values are not retained by this action, and will be returned to their default values once the sensor enters the hard standby state. The details of the sequence of the sequence for entering hard standby and exiting from hard standby are described below and shown in Figure 40 and 41. XSHUTDOWN/RESET_BAR Pin-constrained Mode < Entering Hard Standby > 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. De-assert XSHUTDOWN/RESET_BAR (L ow) to enter the hard standby. 4. The sensor remains in hard standby state if XSHUTDOWN/RESET_BAR remains in the logic "0" state. < Exiting Hard Standby > 1. Turn off VAA/VAA_PIX power-supplies and enable EXTCLK if it was disabled. 2. After 1ms, assert XSHUTDOWN/RESET/BAR (High). 3. After 1ms, turn on VAA/VAA_PIX power-supplies. 4. Follow the pin-constrained power-up sequence from step6 to 9 for output streaming. Figure 39: Hard Standby with Pin-constrained Mode Digital 1.8V time to VDD_IO t30 – 5 0 0 m s Table 25: Power-Down Sequence Definition Symbol Min Typ Max Unit XSHUTDOWN/ RESET_BAR EXTCLK Operating State Hard Reset PLL Lock Streaming VAA, VAA_PIX (2.8V) Mode_select R0x0100 Streaming Soft Standby Logic “1” Hard Standby Internal INIT Soft Standby Logic “0” Logic “1”

AR0542_DS Rev. H Pub. 5/15 EN 64 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications XSHUTDOWN/RESET_BAR Pin-unconstrained Mode < Entering Hard Standby > 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. De-assert XSHUTDOWN (Low) to enter the hard standby. 4. The sensor remains in hard standby state if XSHUTDOWN remains in the logic "0" state. < Exiting Hard Standby > 1. De-assert RESET_BAR (Low) and enable EXTCLK if it was disabled. 2. After 1ms, assert XSHUTDOWN (High). 3. After 1ms, assert RESET_BAR (High). 4. Follow the pin-unconstrained power-up sequence from step6 to 9 for output stream- ing. Figure 40: Hard Standby with Pin-unconstrained Mode Table 26: Hard Standby with Pin-constrained Mode Parameter Symbol Min Typ Max Unit Enter soft standby to XSHUTDOWN/RESET_BAR de-assertion t1 1 – – ms Turn off VAA/VAA_PIX to XSHUTDOWN/RESET_BAR assertion t2 1 – – ms XSHUTDOWN assertion to turn on VAA/VAA_PIX supplies t3 1 – – ms Table 27: Hard Standby with Pin-unconstrained Mode Parameter Symbol Min Typ Max Unit Enter soft standby to XSHUTDOWN de-assertion t1 1 – – ms RESET_BAR de-assertion to XSHUTDOWN assertion t2 1 – – ms XSHUTDOWN assertion to RESET_BAR assertion t3 1 – – ms XSHUTDOWN EXTCLK Operating State Hard Reset PLL Lock Streaming RESET_BAR Mode_select R0x0100 Streaming Soft Standby Logic “1” Hard Standby Internal INIT Soft Standby Logic “0” Logic “1”

AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications AR0542_DS Rev. H Pub. 5/15 EN 65 ©Semiconductor Components Industries, LLC, 2015. Soft Standby and Soft Reset The AR0542 can reduce power consumption by switching to the soft standby state when the output is not needed. Register values are retained in the soft standby state. Once this state is reached, soft reset can be enabled optionally to return all register values to the default. The details of the sequence are described below and shown in Figure 41. Soft Standby 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. Soft Reset 1. Follow the soft standby sequence list above. 2. Set software_reset = 1 (R0x0103) to start the internal initialization sequence. 3. After 2400 EXTCLKs, the internal initializa tion sequence is completed and the current state returns to soft standby automatically. All registers, including software_reset, return to their default values. Figure 41: Soft Standby and Soft Reset Internal VCM Driver The AR0542 utilizes an internal Voice Coil Motor (VCM) driver. The VCM functions are register-controlled through the serial interface. There are two output ports, VCM_OUT and GNDIO_VCM, which would connect directly to the AF actuator. Take precautions in the design of the power supply routing to provide a low impedance path for the ground return. Appropriate filtering would also be required on the actuator supply. Typical values would be a 0.1F and 10F in parallel. EXTCLK mode_select R0x0100 software_reset R0x0103 Logic “1” Logic “0” Streaming Soft Standby Soft Reset Soft Standby next row/frame

2400 EXTCLKs

AR0542_DS Rev. H Pub. 5/15 EN 66 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Timing Specifications Figure 42: VCM Driver Typical Diagram Table 28: VCM Driver Typical Characteristic Parameter Minimum Typical Maximum Units VCM_OUT Voltage at VCM current sink 2.5 2.8 3.3 V WVCM Voltage at VCM actuator 2.5 2.8 3.3 V INL Relative accuracy - 1.5( ±)4 ( ±)L S B RES Resolution - 8 - bits DNL Differential nonlinearity -1 - 1 LSB IVCM Output current 88 100 110 mA AR0542 VCM_OUT GNDIO_VCM VCM DGND VVCM 10µF 0.1µF

AR0542: 1/4-Inch CMOS Digital Image Sensor Spectral Characteristics AR0542_DS Rev. H Pub. 5/15 EN 67 ©Semiconductor Components Industries, LLC, 2015. Spectral Characteristics Figure 43: Quantum Efficiency Note: Aptina recommends 670 ±5nm IR cut filter for AR0542. Refer to Table 29 for the IRCF specification. Table 29: Recommended IR Cut Limits Wavelength Recommended Limits <400 nm Not specified 400-650 nm > 90% Cut-off wavelength 670 ±5 nm 720-900 nm Equal or less than 2% 900-1000 nm Equal or less than 0.1% 1000-1050 nm Equal or less than 0.03% 1050-1150 nm Equal or less than 0.05% >1150nm Not specified 400 450 500 550 600 650 700 750 800 R Gr Gb B Quantum Efficiency (%) Wavelength (nm)

AR0542_DS Rev. H Pub. 5/15 EN 68 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Spectral Characteristics Figure 44: Chief Ray Angle (CRA) vs. Image Height CRA vs. Image Height Plot Image Height CRA (%) (mm) (deg) 000 5 0.113 2.19 10 0.227 4.33 15 0.340 6.43 20 0.454 8.50 25 0.567 10.55 30 0.680 12.57 35 0.794 14.52 40 0.907 16.39 45 1.021 18.15 50 1.134 19.76 55 1.247 21.20 60 1.361 22.43 65 1.474 23.44 70 1.588 24.21 75 1.701 24.74 80 1.814 25.03 85 1.928 25.11 90 2.041 25.01 95 2.155 24.80 100 2.268 24.55 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 Image Height (% ) CRA (deg) 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 Image Height (% ) CRA (deg)

AR0542: 1/4-Inch CMOS Digital Image Sensor

Electrical Characteristics

AR0542_DS Rev. H Pub. 5/15 EN 69 ©Semiconductor Components Industries, LLC, 2015. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 45 and Table 30, “Two-Wire Serial Interface Electrical Characteristics,” on page 69. The S CLK and SDATA signals feature fail-safe input protection, Schmitt trigger input, and suppression of input pulses of less than 50ns. Figure 45: Two-Wire Serial Bus Timing Parameters Note: Read sequence: For an 8-bit READ, read waveforms start after the WRITE command and register addresses are issued. Table 30: Two-Wire Serial Interface Electrical Characteristics Output load = 68.5pF; TJ = 70°C Symbol Parameter Condition MIN TYP MAX Unit VIL Input LOW voltage 0.85 0.898 0.96 V IIL Input leakage current No pull up resistor; VIN = VDD_IO or DGND 10 14 A VOL Output LOW voltage At specified 2mA 0 0.054 0.58 V IOL Output LOW current At specified V OL 0.1V 6 mA CIN Input pad capacitance 6 pf CLOAD Load capacitance N/A pf Sr S P S tSRTS tSTPS tSDS tSDH tSDV tSRTH tF tR 9th Clock tBUF 1st Clock 9 th Clock SDATA SCLK SDATA SCLK tLOW tHIGH tACV 70% 30% 70% 30% 70% 30% 70% 30% 70% 70% 70% 30% 30% 30% 30% 30% 70% 70% 70% 70% 70% 30%

AR0542_DS Rev. H Pub. 5/15 EN 70 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Note: Maximum t SDH could be 0.9s, but must be less than maximum of tSDV and tACV by a transition time. Figure 46: Parallel Data Output Timing Diagram Note: PLL disabled for tCP . Table 31: Two-Wire Serial Interface Timing Specification Symbol Parameter MIN MAX Unit fSCLK SCLK frequency 0 400 KHz tHIGH SCLK high period 0.6 s tLOW SCLK low period 1.3 s tSRTS Start setup time 0.6 s tSRTH Start hold time 0.6 s tSDS Data setup time 100 ns tSDH Data hold time 0 See note. s tSDV Data valid time 0.9 s tACV Data valid acknowledge time 0.9 s tSTPS Stop setup time 0.6 s tBUF Bus free time between STOP and START 1.3 s tR SCLK and SDATA rise time 300 ns tF SCLK and SDATA fall tim 300 ns EXTCLK PIXCLK tR tFtEXTCLK Data[9:0] FRAME_VALID/ LINE_VALID XXXXXX XXX XXX XXXXXX Note: FRAME_VALID assertion leads LINE_VALID assertion by 6 PIXCLK periods. Note: FRAME_VALID negation trails LINE_VALID negation by 6 PIXCLKs. tCP tPFL tPLL tPD tPD tPFH tPLH Pxl_0 Pxl_1 Pxl_2 Pxl_n

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 71 ©Semiconductor Components Industries, LLC, 2015. EXTCLK The electrical characteristics of the EXTCLK input are shown in Table 32. The EXTCLK input supports an AC-coupled sine-wave input clock or a DC-coupled square-wave input clock. If EXTCLK is AC-coupled to the AR0542 and the clock is stopped, the EXTCLK input to the AR0542 must be driven to ground or to VDD_IO. Failure to do this will result in exces- sive current consumption within the EXTCLK input receiver. Table 32: Electrical Characteristics (EXTCLK) Output load = 68.5pF; TJ = 70°C Note: *Assuming 12 MHz input clock. Symbol Parameter Condition Min Typ Max Unit fEXTCLK1 Input clock frequency PLL enabled 6 27 MHz tEXTCLK1 Input clock period PLL enabled 37 167 ns tR Input clock rise slew rate 2.9 8* ns tF Input clock fall slew rate 2.7 8* ns VIN_AC Input clock minimum voltage swing (AC coupled)

0.5 Vpp

VIN_DC Input clock maximum voltage swing (DC coupled) 2.3 V fCLKMAX(AC) Input clock signaling frequency (low amplitude) VIN = VIN_AC (MIN)

12 MHz

fCLKMAX(DC) Input clock signaling frequency (full amplitude) VIN = VDD_IO 27 MHz Clock duty cycle 35 50 65 % tJITTER Input clock jitter cycle-to-cycle 600 ps tLOCK PLL VCO lock time 0.2 1 ms CIN Input pad capacitance 3 pF IIH Input HIGH leakage current 1.36 1.89 3 A VIH Input HIGH voltage 1.26 2.3 V VIL Input LOW voltage -0.5 0.5 V

AR0542_DS Rev. H Pub. 5/15 EN 72 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Parallel Pixel Data Interface The electrical characteristics of the parallel pixel data interface (FV , LV , DOUT[9:0], PIXCLK, SHUTTER, and FLASH outputs) are shown in Table 33. Table 33: Electrical Characteristics (Parallel Pixel Data Interface) Output load = 68.5pF; TJ = 70°C Symbol Parameter Condition Min Typ Max Unit VOH Output HIGH voltage - V VOL Output LOW voltage - V IOH Output HIGH current - mA IOL Output LOW current - mA IOz Tri-state output leakage current - mA tCP EXTCLK to PIXCLK propagation delay PLL Bypass, EXTCLK = 27 MHz 26.519 ns Output pin slew (rising) C LOAD = 25pF 1.4 V/ns Output pin slew (falling) C LOAD = 250pF 1.5 V/ns tPD PIXCLK to data valid PLL Bypass, EXTCLK = 27 MHz 1 ns fPIXCLK PIXCLK frequency Default 48 MHz tPFH PIXCLK to FV HIGH PLL Bypass, EXTCLK = 27 MHz 1 ns tPLH PIXCLK to LV HIGH PLL Bypass, EXTCLK = 27 MHz 1 ns tPFL PIXCLK to FV LOW PLL Bypass, EXTCLK = 27 MHz 1 ns tPLL PIXCLK to LV LOW PLL Bypass, EXTCLK = 27 MHz 1 ns

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 73 ©Semiconductor Components Industries, LLC, 2015. Serial Pixel Data Interface The electrical characteristics of the serial pixel data interface (CLK_P , CLK_N,DATA0_P , DATA1_P , DATA0_N, and DATA1_N) are shown in Table 34 and Table 35. To operate the serial pixel data interface within the electrical limits of the CSI-2 specifi- cation, VDD_IO (I/O digital voltage) is restricted to operate in the range 1.7–1.9V . All MIPI specifications are with sensor operation using on-chip internal regulator. Notes: 1. Value when driving into load impedance anywhere in the Z ID range. 2. It is recommended that the implementer minimize VOD and VCMTX(1,0)in order to minimize radi- ation and optimize signal integrity. Notes: 1. UI is equal to 1/(2*fh). 2. Excess capacitance not to exceed 4pF on each pin. Notes: 1. Though no maximum value for Z OLP is specified, the LP transmitter output impedance shall ensure the TRLP/TFLP is met. Table 34: HS Transmitter DC Specifications Symbol Parameter Min Nom Max Unit Notes VCMTX HS transmit static common-mode voltage 150 200 250 mV 1 VCMTX(1,0) VCMTX mismatch when output is Differential-1 or Differential-0 5m V2 VOD HS transmit differential voltage 140 200 270 mV 1 VOD VOD mismatch when output is Differential-1 or Differential-0 10 mV 2 VOHHS HS output high voltage 360 mV  ZOS Single ended output impedance 40 50 62.5  |ΔZOS| Single ended ouput impedance mismatch 20 % Table 35: HS Transmitter AC Specifications Symbol Parameter Min Nom Max Unit Notes VCMTX(HF) HS transmit static common-mode voltage 15 mV RMS VCMTX(LF) VCMTX mismatch when output is Differential-1 or Differential-0 25 mV PEAK tR and tF 20%-80% rise time and fall time 0.3 UI 2 150 ps Table 36: LP Transmitter DC Specifications Symbol Parameter Min Nom Max Unit Notes VOH HS transmit static common-mode voltage 1.1 1.2 1.3 V VOL VCMTX mismatch when output is Differential-1 or Differential-0 -50 50 mV ZOLP 20%-80% rise time and fall time 110  1

AR0542_DS Rev. H Pub. 5/15 EN 74 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Notes: 1. C LOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10pF. The disturbed line capacitance can up to 50pF for a trans- mission line with 2ns delay. 2. When the ouput voltage is between 400mV and 930mV. 3. Measured as average across any 50 V se gment of the output signal transition. 4. This parameter value can be lower than T LPX due to differences in the rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn transmitters. ANY LP transmitters. Any LP exclusive- OR pulse observed during HS EoT (transition from HS level to LP-1) is glitch behavior. 5. The rise time of T REOT starts from the HS common-Level at the moment the differential amplitude drops below 70mV, due to stopping the differential drive. 6. With an additional load capacitance C CM between 0 and 60 pF on the termination center tap at RX side of the Lane. 7. This value represents a corner point in a piecewise linear curve. 8. When the output voltage is in the range specified by V PIN(absmax) 9. When the output voltage is between 400mV and700mV 10. When V OINST is the instantaneous output voltage, VDP or VDN in millivolts. 11. When the output voltage is between 700mV and930mV Table 37: LP Transmitter AC Specifications Parameter Description Min Max Unit Notes TRLP/TFLP 15%-80% rise time and fall time 25 ns 1 TREOT 30%-85% rise time and fall time 35 ns 1,5,6 V/tSR Slew rate @ CLOAD = 70pF (Falling edge only) 150 mV/ns 1,3,7,8 Slew rate @ CLOAD = 70pF (Rising edge only) mV/ns 1,2,3

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 75 ©Semiconductor Components Industries, LLC, 2015. High Speed Clock Timing Notes: 1. This value corresponds to a minimum 80Mbps data rate. 2. The minimum UI shall not be violated for any single bit period, for example any DDR half cycle within a data burst. Table 38: DC Electrical Charac teristics (Control Interface) Clock Parameter Symbol Min Typ Max Units Notes UI instantaneous UI INST 12.5 ns 1,2

AR0542_DS Rev. H Pub. 5/15 EN 76 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Data Clock Timing Specification Figure 47: Data Clock Timing Note: Total silicon and package delay of 0.3*UI INST. Table 39: Data-Clock Timing Specifications Clock Parameter Symbol Min Typ Max Units Data to Clock Skew (measured at transmitter) T SKEW[TX] -0.15 0.15 UI INST

AR0542: 1/4-Inch CMOS Digital Image Sensor AR0542_DS Rev. H Pub. 5/15 EN 77 ©Semiconductor Components Industries, LLC, 2015. Control Interfaces The electrical characteristics of the control interface (RESET_BAR, TEST , GPI0, GPI1, GPI2, and GPI3) are shown in Table 40. Operating Voltages VAA and VAA_PIX must be at the same potential for correct operation of the AR0542. Table 40: DC Electrical Charac teristics (Control Interface) Output load = 68.5pF; TJ = 70°C Symbol Parameter Condition Min Typ Max Unit VIH Input HIGH voltage 1.26 2.3 V VIL Input LOW voltage -0.5 0.5 V IIN Input leakage current No pull-up resistor; VIN = VDD_IO or DGND 10 A CIN Input pad capacitance 3 pF Table 41: DC Electrical Defi nitions and Characteristics Output Load = 68.5pF; Using Internal Regulator;TJ = 70°C Symbol Parameter Condition Min Typ Max Unit REG_IN 1.8V supply voltage 1.7 1.8 1.9 VDD_TX PHY digital voltage 1.7 1.8 1.9 V VDD_IO I/O digital voltage Parallel pixel data interface 1.7 1.8 1.9 V 2.4 2.8 3.1 V VAA Analog voltage 2.6 2.8 3.1 V VAA_PIX Pixel supply voltage 2.6 2.8 3.1 V I_REGIN/TX 1.8V digital current Streaming, full resolution Parallel 15 FPS 29 35 44 mA IDD_IO(1.8V ) I/O digital current 20 24 38 IDD_IO(2.8) I/O digital current 30 45 67 IAA/IAA_PIX Analog current 50 65 85 I_REGIN/TX 1.8V digital current Streaming, full resolution MIPI 15 FPS 24 26.5 44 mA IDD_IO I/O digital current 0.007 0.04 0.08 IAA/IAA_PIX Analog current 45 60 85 I_REGIN/TX 1.8V digital current Streaming, 1296x972 (xy_bin) resolution Parallel 30 FPS 21 23.5 30 mA IDD_IO(1.8V ) I/O digital current 12 13.5 16 IDD_IO(2.8) I/O digital current 15 22 31 IAA/IAA_PIX Analog current 50 65 85 I_REGIN/TX 1.8V digital current Streaming, 1296x972 (xy_bin) resolution MIPI 30 FPS 15 18.5 30 mA IDD_IO I/O digital current 0.007 0.03 0.08 IAA/IAA_PIX Analog current 50 65 85

AR0542_DS Rev. H Pub. 5/15 EN 78 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Note: Digital Current includes REG_IN, as the regu lator is still operating in soft standby mode. Absolute Maximum Ratings Caution Stresses greater than those listed in Table 42 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Hard Standby (Clock on at 24 MHz) STANDBY current when asserting XSHUTDOWN signalAnalog Current 0.3 1 4 A Digital current 1.5 2 6 A Hard Standby (Clock off) Analog Current 0.3 1 4 A Digital current 1.5 2 6 A Soft Standby (Clock on at 24 MHz) STANDBY current when asserting R0x100 = 1Analog Current 15 41 90 A Digital current 4 4.8 7.5 mA Soft Standby(Clock off) Analog Current 15 41 90 A Digital current 3.5 4.2 7 mA Table 42: Absolute Maximum Values Symbol Parameter MIN MAX Unit VDD1V8(REG_IN 1.8V digital voltage -0.3 2.1 V VDD_TX PHY digital voltage -0.3 2.1 V VDD_IO I/O digital voltage -0.3 3.5 V VAA Analog supply voltage -0.3 3.5 V VAA_PIX Pixel supply voltage -0.3 3.5 V T_OP Operating temperature measured at junction -30 70 °C T_STG Storage temperature -40 85 °C Table 41: DC Electrical Definition s and Characteristics (continued) Output Load = 68.5pF; Using Internal Regulator;TJ = 70°C Symbol Parameter Condition Min Typ Max Unit

AR0542_DS Rev. H Pub. 5/15 EN 79 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor SMIA and MIPI Specification Reference The sensor design and this documentation is based on the following reference docu- ments:  SMIA Specifications: – SMIA 1.0 Part 1: Functional Specification (Version 1.0 dated 30 June 2004) SMIA 1.0 Part 1: Functional Specification ECR0001 (Version 1.0 dated 11 Feb 2005)  MIPI Specifications: – MIPI Alliance Standard for CSI-2 version 1.0 – MIPI Alliance Specification for D-PHY Version 1.00.00- 14 May 2009

AR0542_DS Rev. H Pub. 5/15 EN 80 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor

Revision History

 Updated “Ordering Information” on page 2  Removed Confidential marking  Updated format of Table of Contents  Updated to ON Semiconductor template  Updated Table 16, “Minimum Row Time and Blanking Numbers,” on page 48  Updated Table 17, “Minim um Frame Time and Blanking Numbers,” on page 48  Updated Figure 42: “VCM Driver Typical Diagram,” on page 66  Updated note for Figure 43: “Quantum Efficiency,” on page 67  Added Table 29, “Recommended IR Cut Limi ts,” on page 67 and renumbered subse- quent tables  Updated Table 32, “Electrical Characteristics (EXTCLK),” on page 71  Updated 1080p frame rate in Table 1, “K ey Performance Parameters,” on page 1  Updated Figure 3: “Typical Configuration: Parallel Pixel Data Interface,” on page 8  Deleted D GNDPLL from Table 3, “Signal Descriptions,” on page 11  Deleted references to CCP2  Updated to Production  Updated Frame Rate in Table 1, “Key Performance Parameters,” on page 1  Replaced Figure 3: “Typical Configuration: Parallel Pixel Data Interface,” on page 8 and updated Note 10  Replaced 15. “The FLASH, which can be us ed for flash control, is not shown in Figure 3.,” on page 9 and updated Note 10  Replaced Figure 4: “Typical Configuration: Serial Dual-Lane MIPI Pixel Data Inter- face,” on page 10 and updated Note 10  Updated VCM_GND in Table 3, “Signal Descriptions,” on page 11  Updated “ Aptina Gain Model” on page 52  Updated Table 21, “Gain Usage,” on page 52  Replaced Figure 45: “Two-Wire Serial Bus Timing Parameters,” on page 69  Replaced Table 27 with Table 30, “Two-Wire Serial Interface Electrical Characteris- tics,” on page 69 and Table 31, “Two-Wire Serial Interface Timing Specification,” on page 70  Updated OTPM size to 7.7 Kb in “One-Time Programmable Memory (OTPM)” on page 35  Updated “ Aptina Gain Model” on page 52

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