AR0331_17 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Superior Low-light Performance
- Latest 2.2 μm Pixel with ON Semiconductor A-Pix™ Technology
- Full HD Support at 1080 P 60 fps for Superior Video Performance
- Linear or High Dynamic Range Capture
- 3.1 M (4:3) and 1080 P Full HD (16:9) Images
- Optional Adaptive Local Tone Mapping (ALTM)
- Interleaved T1/T2 Output
- Support for External Mechanical Shutter
- Support for External LED or Xenon Flash
- Slow-motion Video (VGA 120 fps)
- On-chip Phase-locked Loop (PLL) Oscillator
- Integrated Position-based Color and Lens Shading Correction
- Slave Mode for Precise Frame-rate Control
- Stereo/3D Camera Support
- Statistics Engine www.onsemi.com See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
- Data Interfaces: Four-lane Serial High-speed Pixel Interface (HiSPi) Differential Signaling (SLVS and HiVCM), or Parallel
- Auto Black Level Calibration
- High-speed Context Switching
- Temperature Sensor
Applications
- Video Surveillance
- Stereo Vision
- Smart Vision
- Automation
- Machine Vision
- 1080p60 Video Applications
- High Dynamic Range Imaging IBGA52 9x9 CASE 503AA
www.onsemi.com Table 1. KEY PARAMETERS
74.25 Mp/s (Parallel)
Table 2. AVAILABLE PART NUMBERS
of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1. Block Diagram on-chip to produce a single image at 16-bit per pixel value. value with close to zero loss in image quality.
Figure 2. Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies should be adequately decoupled.
- ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
- The parallel interface output pads can be left unconnected if the serial output interface is used.
- ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply
considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations.
- ON Semiconductor recommends that analog power planes are placed in a manner such that coupling
with the digital power planes is minimized.
- I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
Figure 3. Typical Configuration: Parallel Pixel Data Interface
- All power supplies should be adequately decoupled.
- ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
- The serial interface output pads and V DDSLVS can be left unconnected if the parallel output interface is used.
- ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply are mounted as
to the AR0331 demo headboard schematics for circuit recommendations.
- ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
- I/O signals voltage must be configured to match V DD_IO voltage to minimize any leakage currents.
- The EXTCLK input is limited to 6 −48 MHz.
Figure 4. 48 iLCC Package, Parallel Output Table 3. PIN DESCRIPTION
1 DOUT4 Output Parallel Pixel Data Output
2 DOUT5 Output Parallel Pixel Data Output
3 DOUT6 Output Parallel Pixel Data Output
4 VDD_PLL Power PLL Power
5 EXTCLK Input External Input Clock
6 DGND Power Digital Ground
7 DOUT7 Output Parallel Pixel Data Output
8 DOUT8 Output Parallel Pixel Data Output
9 DOUT9 Output Parallel Pixel Data Output
10 DOUT10 Output Parallel Pixel Data Output
Table 3. PIN DESCRIPTION (continued)
11 DOUT11 Output Parallel Pixel Data Output (MSB)
12 VDD_IO Power I/O Supply Power
14 VDD Power Digital Power
15 SCLK Input Two-wire Serial Clock Input
16 SDATA I/O Two-wire Serial Data I/O
18 VDD_IO Power I/O Supply Power
19 VDD Power Digital Power
23 OE_BAR Input Output Enable (Active LOW)
25 TEST Input Manufacturing Test Enable Pin (Connect to DGND)
26 FLASH Output Flash Output Control
27 TRIGGER Input Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to
28 FRAME_VALID Output Asserted when DOUT Frame Data is Valid
29 LINE_VALID Output Asserted when DOUT Line Data is Valid.
30 DGND Power Digital Ground
31 Reserved
33 Reserved
34 VAA Power Analog Power
35 AGND Power Analog Ground
36 VAA Power Analog Power
37 VAA_PIX Power Pixel Power
38 VAA_PIX Power Pixel Power
39 AGND Power Analog Ground
40 VAA Power Analog Power
44 DGND Power Digital Ground
45 DOUT0 Output Parallel Pixel Data Output (LSB)
46 DOUT1 Output Parallel Pixel Data Output
47 DOUT2 Output Parallel Pixel Data Output
48 DOUT3 Output Parallel Pixel Data Output
Figure 5. 48 iLCC Package, HiSPi Output Table 4. PIN DESCRIPTION, 48 ILCC
1 SLVSC_N Output HiSPi Serial DDR Clock Differential N
2 SLVS1_P Output HiSPi Serial Data, Lane 1, Differential P
3 SLVS1_N Output HiSPi Serial Data, Lane 1, Differential N
4 SLVS0_P Output HiSPi Serial Data, Lane 0, Differential P
5 SLVS0_N Output HiSPi Serial Data, Lane 0, Differential N
8 VDD_IO Power I/O Supply Power
9 DGND Power Digital Ground
10 VDD Power Digital Power
Table 4. PIN DESCRIPTION, 48 ILCC (continued)
11 EXTCLK Input External Input Clock
12 VDD Power Digital Power
13 DGND Digital Ground
14 VDD_IO Power I/O Supply Power
15 SDATA I/O Two-wire Serial Data I/O
16 SCLK Input Two-wire Serial Clock Input
17 TEST Manufacturing Test Enable Pin (Connect to DGND)
20 DGND Power Digital Ground
21 VDD_IO Power I/O Supply Power
25 OE_BAR Output Enable (active LOW)
26 TRIGGER Input Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to
27 FLASH Output Flash Output Control
28 DGND Power
29 VDD_PLL Power PLL Power
30 Reserved
31 AGND Power Analog Ground
32 VAA Power Analog Power
35 VAA_PIX Power Pixel Power
36 VAA_PIX Power Pixel Power
38 VAA Power Analog Power
41 VAA Power Analog Power
42 AGND Power Analog Ground
43 DGND Power Digital Ground
44 SLVS3_P Output HiSPi Serial Data, Lane 3, Differential P
45 SLVS3_N Output HiSPi Serial Data, Lane 3, Differential N
46 SLVS2_P Output HiSPi Serial Data, Lane 2, Differential P
47 SLVS2_N Output HiSPi Serial Data, Lane 2, Differential N
48 SLVSC_P Output HiSPi Serial DDR Clock Differential P
Figure 6. 9.5 x 9.5 mm 63−Ball IBGA Package Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA EXTCLK C1 Input External Input Clock.
Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA (continued) FRAME_VALID E2 Output Asserted when DOUT Frame Data is Valid. PIXCLK E3 Output Pixel Clock Out. DOUT is Valid on Rising Edge of this Clock.
rows and columns sequenced as shown in Figure 9. Figure 9. Imaging a Scene
- FRAME_V ALID
- LINE_V ALID
- PIXCLK
- DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 7 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 6.
Table 6. OUTPUT ENABLE CONTROL
0 X Interface Driven
Table 7. CONFIGURATION OF THE PIXEL DATA INTERFACE data lanes and one clock as output.
- SLVSC_P
- SLVSC_N
- SLVS0_P
- SLVS0_N
- SLVS1_P
- SLVS1_N
- SLVS2_P
- SLVS2_N
- SLVS3_P
- SLVS3_N The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.50.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver.
Figure 13. Delaying the Clock with Respect to Data Figure 14. Delaying Data with Respect to the Clock
1 UItDLLSTEP
The serial format should be configured using R0x31AC. detail regarding this register.
- 0x0304 − Sensor supports quad-lane HiSPi operation
- 0x0302 − Sensor supports dual-lane HiSPi operation
- 0x0301 − Sensor supports single-lane HiSPi operation
Table 8. RECOMMENDED SENSOR GAIN disabled by setting R0x30BA[5] to 0. The default value is 1. be adjusted at the end of the datapath. pedestal be set to 16 when ALTM is enabled. value by adjusting register R0x301E. of the datapath. The ALTM pedestal default offset is 0.
a linearized 16-bit value for each pixel’s response. between the brightest and the darkest objects in a scene. HDR image having a contrast ratio of around 250000:1. increase the local contrast and the visibility of the images. should be set to 1 for proper display. Figure 19. HDR Data Compression
Table 9. COMPANDING TABLE four colored segments in Figure 19. Table 10. KNEE POINTS FOR COMPRESSION FROM 16 BITS TO 12 BITS should occur to the data after linearization. Table 11. BIT OPERATION AFTER LINEARIZATION
- The sensor will calculate the ratio internally, enabling the
would still use the 16x relinearization formulas. exposure lines in relation to the frame_length_lines register. integration time is frame_length_lines − 71.
potentially be visible and might look like a ghosting effect. (active LOW) or the reset register. register. Bit 0 is used to reset the digital logic of the sensor. Figure 20. PLL Dividers Affecting VCO Frequency
Table 13. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE Figure 23. PLL for the Serial Interface The PLL must be enabled when HiSPi mode is selected. number of lanes, refer to “Serial Configuration”. Table 14. PLL PARAMETERS FOR THE SERIAL INTERFACE
- The maximum data-rate per lane (FSERIAL) is 700 Mbps/lane (HiSPi).
- Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate matches the peak pixel rate (2 x CLK_PIX). ♦ 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s) ♦ 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s) ♦ 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 37.125 Mpixel/s)
Table 15. EXAMPLE PLL CONFIGURATIONS FOR THE SERIAL INTERFACE writes and other operations. occur if the Trigger pin is held high.
- Set R0x301A[12] = 1 if serial mode was used
- Set R0x301A[2] = 0 and drive Trigger pin low.
- Turn off external clock to further minimize power
- Enable external clock if it was turned off
- Set R0x301A[2] = 1 or drive Trigger pin high.
- Set R0x301A[12] = 0 if serial mode is used
2x or 3x adjacent pixels within the same color plane. Figure 27. Vertical Row Binning in the AR0331 Sensor
Table 16. MINIMUM VERTICAL BLANKING CONFIGURATION
- min_vertical_blanking includes the default number (4) of idle rows.
“Slave Mode Active State and Vertical Blanking,” . precise control of frame rate and register change updates. and must be at least 3 PIXCLK cycles wide. Figure 29. Slave Mode Active State and Vertical Blanking after the extra delay period is finished. time plus 16 clock periods (T FRAME + (16 / CLK_PIX)). and will respond to the VD signal.
updated to the new value until the readout of frame n+2. to context A the sensor will reference the context A registers. changing from context B to context A. Table 18. LIST OF CONFIGURABLE REGISTERS FOR CONTEXT A AND CONTEXT B
Figure 34. Example of Changing the Sensor from Context A to Context B enabled, Combi Mode loads a single (HDR) sequencer. enabled by setting R0x31D0 from “0” to “1”. Table 19. A−LAW COMPRESSION TABLE FOR 12−10 BITS capable of measuring die junction temperature.
Figure 36. Format of Embedded Statistics Output within a Frame
- 0x0B0 − identifier
- Register 0x303A − frame_count
- Register 0x31D2 − frame ID
- Histogram data − histogram bins 0−243 Line 2:
- 0x0B0 (TAG)
- Mean
- Histogram Begin
- Histogram End
- Low End Histogram Mean
- Percentage of Pixels Below Low End Mean
- Normal Absolute Deviation Test Patterns The AR0331 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 20. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels.
Table 20. TEST PATTERN MODES
0 No Test Pattern (Normal Operation)
1 Solid Color Test Pattern
3 Fade-to-Gray Vertical Color Bars Test Pattern
256 Walking 1s Test Pattern (12-bit)
color bar pattern will be sent through the digital pipeline.
www.onsemi.com TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0331. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 k Ω resistor. Either the slave or master device can drive S DATA LOW—the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLKLOW; the AR0331 uses S CLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on S DATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on S DATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when S CLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0331 are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the S ADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving S DATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Figure 43. Quantum Efficiency
- VDD = 1.8 V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ±0.3 V;
- VDD_SLVS = 0.4 V – 0.1/+0.2; TA = −30°C to +85°C; output load = 10 pF;
- frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 44 and Table 21.
Figure 44. Two-Wire Serial Bus Timing Parameters Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 21. TWO−WIRE SERIAL BUS CHARACTERISTICS
- This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.
- Two-wire control is I 2C-compatible.
- A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
- The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
- A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This
I2C-bus specification) before the SCLK line is released.
- Cb = total capacitance of one bus line in pF.
Figure 45. I/O Timing Diagram LINE_VALID FRAME_VALID leads LINE_VALID by 6 PIXCLKs. Table 22. I/O TIMING CHARACTERISTICS
Table 22. I/O TIMING CHARACTERISTICS (continued)
- I/O timing characteristics are measured under the following conditions:
Table 23. DC ELECTRICAL CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 24. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. Table 25. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND LINEAR MODE
- Operating currents are measured at the following conditions:
Table 26. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND HDR MODE
- Operating currents are measured at the following conditions:
Table 27. OPERATING CURRENT IN HiSPi (HIVCM) OUTPUT AND LINEAR MODE
- Operating currents are measured at the following conditions:
Table 28. OPERATING CURRENT IN HiSPi (HIVCM) OUTPUT AND HDR MODE
- Operating currents are measured at the following conditions:
Table 29. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE
Table 29. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE (continued)
- Operating currents are measured at the following conditions:
Table 30. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND HDR MODE
- Operating currents are measured at the following conditions:
equivalent to VDD_HiSPi as referenced in the specification. specification as described in this section. Table 31. CHANNEL SKEW Table 32. CLOCK DLL STEPS
- The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0331.
Table 33. DATA DLL STEPS
- The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0331.
- Turn on VDD_PLL power supply
- After 100 μs, turn on VAA and VAA_PIX power
- After 100 μs, turn on VDD_IO power supply
- After 100 μs, turn on VDD power supply
- After 100 μs, turn on VDD_SLVS power supply
- After the last power supply is stable, enable
- Assert RESET_BAR for at least 1 ms. The parallel
- Wait 150000 EXTCLKs (for internal initialization
- Configure PLL, output, and image settings to
- Wait 1ms for the PLL to lock
- Set streaming mode (R0x301a[2] = 1)
Figure 46. Power Up
Table 34. POWER UP SEQUENCE
- Xtal settling time is component-dependent, usually taking about 10 – 100 mS.
- Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
- It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
current draw on this supply. must have the separation specified below.
- Disable streaming if output is active by setting
- The soft standby state is reached after the current
Figure 47. Power Down
Table 35. POWER DOWN SEQUENCE
- t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
www.onsemi.com ILCC48 10 x 10 CASE 847AG ISSUE O
www.onsemi.com IBGA63 9.5 x 9.5 CASE 503AM ISSUE O
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