AR0330CM ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • 2.2 /C0109m Pixel with A−Pix/C0116 Technology
  • Full HD support at 60 fps (2304 (H) × 1296 (V)) for Maximum Video Performance
  • Superior Low-light Performance
  • 3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
  • Support for External Mechanical Shutter
  • Support for External LED or Xenon Flash
  • Data Interfaces: Four-lane Serial High-speed Pixel Interface (HiSPi) Differential Signaling (SLVS), Four-lane Serial MIPI Interface, or Parallel
  • On-chip Phase-locked Loop (PLL) Oscillator
  • Simple Two-wire Serial Interface
  • Auto Black Level Calibration
  • 12-to-10 Bit Output A−Law Compression
  • Slave Mode for Precise Frame-rate Control and for Synchronizing Two Sensors

Applications

  • 1080p High-definition Digital Video Camcorder
  • Web Cameras and Video Conferencing Cameras
  • Security See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

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196 Mp/s using a 4-lane HiSPi or MIPI serial interface and

98 Mp/s using the parallel interface. Figure 1. Block Diagram the ADC is a 12-bit value for each pixel in the array.

Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330 SENSOR Table 4. AVAILABLE WORKING MODES IN THE AR0330 SENSOR The HiSPi interface requires two power supplies. supply is a nominal 1.8 V and ranges from 1.7 to 1.9 V . R0x306E[9] must be set to “0”.

  1. Digital logic supply was named VDD_SLVS while

the driver supply was named VDD_SLVS_TX.

  1. Digital logic supply was named VDD_PHY while

the driver supply was named VDD_SLVS.

Figure 2. Serial 4-lane HiSPi Interface

  1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 /C0109F and 0.1 /C0109F decoupling capacitors for

every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations.

  1. To allow for space constraints, ONSemiconductor recommends having 0.1/C0109F decoupling capacitor inside the module as close to the pads

as possible. In addition, place a 10 /C0109F capacitor for each supply off-module but close to each supply.

  1. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
  2. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
  3. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s
  4. TEST pin should be tied to D GND.
  5. Set High_VCM (R0x306E[9]) to 0 (default) to use the V DD_HiSPi_TX in the range of 0.4–0.8 V. Set High_VCM to 1 to use a range of
  6. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must be left floating.
  7. The V DD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as VDD_MIPI is tied to the VDD_PLL supply both

in the package routing and also within the sensor die itself. 10.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

  1. If the TRIGGER pin or pad is not used then it should be tied to D

12.The GND_SLVS pad must be tied to DGND. It is connected this way in the CLCC and CSP packages.

Figure 3. Serial MIPI

  1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 /C0109F and 0.1 /C0109F decoupling capacitors for

and VDD. Actual values and results may vary depending on layout and design considerations.

  1. To allow for space constraints, ONSemiconductor recommends having 0.1/C0109F decoupling capacitor inside the module as close to the pads

as possible. In addition, place a 10 /C0109F capacitor for each supply off-module but close to each supply.

  1. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
  2. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
  3. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s
  4. TEST pin must be tied to D GND for the MIPI configuration.
  5. ON Semiconductor recommends that GND_MIPI be tied to D GND.
  6. V DD_MIPI is tied to VDD_PLL in both the CLCC and the CSP package. ON Semiconductor strongly recommends that VDD_MIPI must be

connected to a VDD_PLL in a module design since VDD_PLL and VDD_MIPI are tied together in the die.

  1. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must be left floating.

DD_HISPI and VDD_HISPI_TX) can be tied to ground.

  1. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

Figure 4. Parallel Pixel Data Interface

  1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 /C0109F and 0.1 /C0109F decoupling capacitors for

every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD. Actual values and results may vary depending on layout and design considerations.

  1. To allow for space constraints, ONSemiconductor recommends having 0.1/C0109F decoupling capacitor inside the module as close to the pads

as possible. In addition, place a 10 /C0109F capacitor for each supply off-module but close to each supply.

  1. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
  2. This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
  3. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s
  4. TEST pin should be tied to the ground.
  5. The data and clock package pins or die pads used for the HiSPi and MIPI interface must be left floating.

package routing and also within the sensor die itself. HiSPi Power Supplies (VDD_HISPI and VDD_HISPI_TX) can be tied to ground.

  1. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.

Table 5. PIN DESCRIPTIONS RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default. EXTCLK Input Master input clock, range 6−27 MHz. OE_BAR Input Output enable (active LOW). Only available on bare die version. TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame. SADDR Input Two-wire serial address select. SCLK Input Two-wire serial clock input. SDATA I/O Two-wire serial data I/O. PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. DOUT[11:0] Output Parallel pixel data output. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. FRAME_VALID Output Asserted when DOUT data is valid. LINE_VALID Output Asserted when DOUT data is valid. VDD_IO Power IO supply power. VDD_PLL Power PLL power supply. The MIPI power supply (VDD_MIPI) is tied to VDD_PLL in both packages. TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation. SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. SLVS0_P Output HiSPi serial data, lane 0, differential P. SLVS0_N Output HiSPi serial data, lane 0, differential N. SLVS1_P Output HiSPi serial data, lane 1, differential P. SLVS1_N Output HiSPi serial data, lane 1, differential N. SLVS2_P Output HiSPi serial data, lane 2, differential P. SLVS2_N Output HiSPi serial data, lane 2, differential N. SLVS3_P Output HiSPi serial data, lane 3, differential P. SLVS3_N Output HiSPi serial data, lane 3, differential N. SLVSC_P Output HiSPi serial DDR clock differential P. SLVSC_N Output HiSPi serial DDR clock differential N. DATA1_P Output MIPI serial data, lane 1, differential P. DATA1_N Output MIPI serial data, lane 1, differential N. DATA2_P Output MIPI serial data, lane 2, differential P. DATA2_N Output MIPI serial data, lane 2, differential N. DATA3_P Output MIPI serial data, lane 3, differential P. DATA3_N Output MIPI serial data, lane 3, differential N. DATA4_P Output MIPI serial data, lane 4, differential P. DATA4_N Output MIPI serial data, lane 4, differential N.

Table 5. PIN DESCRIPTIONS (continued) CLK_P Output Output MIPI serial clock, differential P. CLK_N Output Output MIPI serial clock, differential N. VDD_HiSPi Power 1.8 V power port to HiSPi digital logic. VAA_HV_NPIX Power Power supply pin used to program the sensor OTPM (one-time programmable memory). This pin should be open if OTPM is not used. Table 6. CSP (HiSPi/MIPI) PACKAGE PINOUT Figure 5. CLCC Package Pin Descriptions NOTE: Pins labeled NC (Not Connected) should be tied to ground.

have the separation specified below.

  1. Turn on VDD_PLL and VDD_MIPI power supplies.
  2. After 100 /C0109s, turn on VAA and VAA_PIX power
  3. After 100 /C0109s, turn on VDD power supply.
  4. After 100 /C0109s, turn on VDD_IO power supply.
  5. After the last power supply is stable, enable
  6. Assert RESET_BAR for at least 1 ms.
  7. Wait 150,000 EXTCLK periods (for internal

initialization into software standby.

  1. Write R0x3152 = 0xA114 to configure the internal

register initialization process.

  1. Write R0x304A = 0x0070 to start the internal

register initialization process.

  1. Wait 150,000 EXTCLK periods.
  2. Configure PLL, output, and image settings to
  3. Wait 1ms for the PLL to lock.
  4. Set streaming mode (R0x301A[2] = 1).

Figure 6. Power Up

  1. A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers

a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above.

  1. The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal initialization

should be ignored in the general power up sequence. Table 7. POWER-UP SEQUENCE

  1. External clock settling time is component-dependent, usually taking about 10–100 ms.
  2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the

RC time must include the all power rail settle time and Xtal settle time.

  1. It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the

current draw on this supply.

  1. V DD_MIPI is tied to VDD_PLL in the both the CLCC and CSP packages and must be powered to 2.8 V. The VDD_HiSPi and VDD_HiSPi_TX

supplies do not need to be turned on if the sensor is configured to use the MIPI or parallel interface.

  1. Disable streaming if output is active by setting
  2. The soft standby state is reached after the current
  3. Turn off VDD and VDD_HiSPi.
  4. Turn off VDD_PLL, VDD_MIPI.

Figure 7. Power Down Table 8. POWER-DOWN SEQUENCE NOTE: t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.

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ELECTRICAL CHARACTERISTICS

Table 9. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (MIPI MODE) Table 10. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (HiSPi MODE)

Table 11. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS (PARALLEL MODE) Table 12. STANDBY POWER operational sections of this specification is not implied. Table 13. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

Figure 8. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 14. TWO-WIRE SERIAL BUS CHARACTERISTICS

  1. This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.
  2. Two-wire control is I 2C-compatible.
  3. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
  4. The maximum t HD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
  5. A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

I2C-bus specification) before the SCLK line is released.

  1. Cb = total capacitance of one bus line in pF.

Figure 9. I/O Timing Diagram NOTE: PLL disabled for t CP. Table 15. I/O PARAMETERS Table 16. I/O TIMING

Table 17. PARALLEL I/O RISE SLEW RATE HiSPi transmitter specification. Table 18. POWER SUPPLY AND OPERATING TEMPERATURE

  1. Where ‘n’ is the number of PHYs.
  2. Specification values may be exceeded when outside this temperature range.

Table 19. SLVS ELECTRICAL DC SPECIFICATION (TJ = 25°C)

Table 20. SLVS ELECTRICAL TIMING SPECIFICATION

  1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
  2. Taken from the 0 V crossing point with the DLL off.
  3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

  1. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
  2. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
  3. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

complementary edges at mean VCM point. Note that differential skew also is related to the /C0068VCM_AC spec which also must not be exceeded. Table 21. HiVCM POWER SUPPLY AND OPERATING TEMPERATURES

  1. Where ‘n’ is the number of PHYs.
  2. Specification values may be exceeded when outside this temperature range.

Table 22. HiVCM ELECTRICAL VOLTAGE AND IMPEDANCE SPECIFICATION (TJ = 25°C) Table 23. HiVCM ELECTRICAL AC SPECIFICATION

  1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
  2. Taken from the 0 V crossing point with the DLL off.
  3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

  1. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
  2. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
  3. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

CM point. Note that differential skew also is related to the /C0068VCM_AC spec which also must not be exceeded.

  1. Timing measurements are to be taken using the
  2. Rise and fall times are measured between 20% to
  3. Mean Clock-to-Data skew should be measured

0.5 UI with the difference being the Clock-to-Data

Figure 12. Clock-to-Data Skew Timing Diagram

  1. The differential skew is measured on the two

Figure 13. Differential Skew

Table 27. PLL PARAMETERS FOR THE SERIAL INTERFACE

  • The maximum data-rate per lane (FSERIAL) is 768 Mbps/lane (MIPI) and 700 Mbps/lane (HiSPi).
  • The output pixel rate per lane (CLK_OP) should be configured so that the sensor output pixel rate matches the peak pixel rate (2 × CLK_PIX): ♦ 4-lane: 4 × CLK_OP = 2 × CLK_PIX = Pixel Rate (max: 196 Mpixel/s) ♦ 2-lane: 2 × CLK_OP = 2 × CLK_PIX = Pixel Rate (max: 98 Mpixel/s) ♦ 1-lane: 1 × CLK_OP = 2 × CLK_PIX = Pixel Rate (max: 76 Mpixel/s)

Table 28. EXAMPLE PLL CONFIGURATIONS FOR THE SERIAL INTERFACE

  • FV
  • LV
  • PIXCLK
  • DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 30 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High −Z under pin or register control, as shown in

Table 29. OE_BAR pin is only available on the bare die Table 29. OUTPUT ENABLE CONTROL

0 X Interface Driven

Table 30. CONFIGURATION OF THE PIXEL DATA INTERFACE 0 0 1 Power up default. Serial pixel data interface and its clocks are enabled. serial pixel data interface. are synchronized to the end of frames in the parallel pixel data interface.

  • SLVSC_P
  • SLVSC_N
  • SLVS0_P
  • SLVS0_N
  • SLVS1_P
  • SLVS1_N
  • SLVS2_P
  • SLVS2_N
  • SLVS3_P
  • SLVS3_N The HiSPi interface supports three protocols, Streaming S, Streaming SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.00.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 21 shows the configuration between the HiSPi transmitter and the receiver.

www.onsemi.com HiSPi Streaming Mode Protocol Layer The HiSPi protocol is described HiSPi Protocol V1.00.00 MIPI Interface The serial pixel data interface uses the following output-only signal pairs:

  • DATA1_P
  • DATA1_N
  • DATA2_P
  • DATA2_N
  • DATA3_P
  • DATA3_N
  • DATA4_P
  • DATA4_N
  • CLK_P
  • CLK_N The signal pairs use both single-ended and differential signaling, in accordance with the the MIPI Alliance Specification for D −PHY v1.00.00. The serial pixel data interface is enabled by default at power up and after reset. The DATA0_P, DATA0_N, DATA1_P, DATA1_N, CLK_P and CLK_N pads are set to the Ultra Low Power State (ULPS) if the serial disable bit is asserted (R0x301A−B[12] = 1) or when the sensor is in the hardware standby or soft standby system states. When the serial pixel data interface is used, the LINE_V ALID, FRAME_V ALID, PIXCLK and D OUT[11:0] signals (if present) can be left unconnected. Serial Configuration The serial format should be configured using R0x31AC. This register should be programmed to 0x0C0C when using the parallel interface. The R0x0112−3 register can be programmed to any of the following data format settings that are supported:
  • 0x0C0C – Sensor supports RAW12 uncompressed data format
  • 0x0C0A – The sensor supports RAW12 compressed format (10-bit words) using 12−10 bit A−LAW Compression. See “Compression” section
  • 0x0A0A – Sensor supports RAW10 uncompressed data format. This mode is supported by discarding all but the upper 10 bits of a pixel value
  • 0x0808 – Sensor supports RAW8 uncompressed data format. This mode is supported by discarding all but the upper 8 bits of a pixel value (MIPI only). The serial_format register (R0x31AE) register controls which serial interface is in use when the serial interface is enabled (reset_register[12] = 0). The following serial formats are supported:
  • 0x0201 – Sensor supports single-lane MIPI operation
  • 0x0202 – Sensor supports dual-lane MIPI operation
  • 0x0204 – Sensor supports quad-lane MIPI operation
  • 0x0304 − Sensor supports quad-lane HiSPi operation The MIPI timing registers must be configured differently for 10-bit or 12-bit modes. These modes should be configured when the sensor streaming is disabled. See Table 31.

Table 31. RECOMMENDED MIPI TIMING CONFIGURATION

Description

10-bit, 490 Mbps/Lane 12-bit, 588 Mbps/Lane Clocking: Continuous 0x31B0 40 36 Frame Preamble 0x31B2 14 12 Line Preamble 0x31B4 0x2743 0x2643 MIPI Timing 0 0x31B6 0x114E 0x114E MIPI Timing 1 0x31B8 0x2049 0x2048 MIPI Timing 2 0x31BA 0x0186 0x0186 MIPI Timing 3 0x31BC 0x8005 0x8005 MIPI Timing 4 0x31BE 0x2003 0x2003 MIPI Config Status

Figure 29. The Row Integration Time is Greater than the Frame Readout Time equal to or greater than the frame_length_lines. time by setting R0x30CE[5] to 1.

will apply the same analog gain to each color channel. Figure 30. Gain Stages in AR0330 Sensor Table 32. RECOMMENDED SENSOR ANALOG GAIN TABLES

used by the corrections in the digital readout path.

  • Electronic Rolling Shutter (ERS) Mode: This is the normal mode of operation. When the AR0330 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0330 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See “Changes to Integration Time” in the AR0330 Register Reference.
  • Global Reset Mode: This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0330 provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. The x_addr_start equal to 6 is the minimum setting value. The y_addr_start equal to 6 is the minimum setting value. Please refer to Table 33 and Table 34 for details.

Table 33. PIXEL COLUMN CONFIGURATION Table 34. PIXEL ROW CONFIGURATION order is reflected in the value of the pixel_order register.

Table 35. CONFIGURATION FOR HORIZONTAL SUBSAMPLING Table 36. CONFIGURATION FOR VERTICAL SUBSAMPLING

precise control of frame rate and register change updates. must be set to “1” to enable the slave mode. Figure 36. Slave Mode Active State and Vertical Blanking after the extra delay period is finished. time minus 16 clock periods (TFRAME − (16 / CLK_PIX)). and will respond to the VD signal.

www.onsemi.com When the slave mode becomes active, the sensor will pause both row read and row reset operations. NOTE: The row integration period is defined as the period from row reset to row read. When the AR0330 is working in slave mode, the external trigger signal VD must have accurately controlled timing to avoid uneven exposure in the output image. The VD timing control should make the slave mode “wait period” less than 32 pixel clocks. To avoid uneven exposure, programmed integration time cannot be larger than VD period. To increase integration time more than current VD period, the AR0330 must be configured to work at a lower frame rate and read out image with new VD to match the new timing. The period between slave mode pulses must also be greater than the frame period. If the rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be ignored and will wait until the next VD pulse has arrived.

Figure 40. Example of the Sensor Output of a 2304 /C0121 1296 Frame at 30 fps (The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor.

includes writes to the sensor gain and integration registers. when changing from context B to context A. Table 39. LIST OF CONFIGURABLE REGISTERS FOR CONTEXT A AND CONTEXT B NOTE: ON Semiconductor recommends leaving fine_integration_time at 0.

Figure 41. Example of Changing the Sensor from Context A to Context B

the data pedestal has been added to the data. See Figure 1. enabled by setting R0x31D0 from “0” to “1”. Table 40. A-LAW COMPRESSION TABLE FOR 12−10 BITS Table 41. TEST PATTERN MODES

0 No Test Pattern (Normal Operation)

1 Solid Color

3 Fade-to-Gray Vertical Color Bars

256 Walking 1s Test Pattern (12-bit)

color bar pattern will be sent through the digital pipeline.

www.onsemi.com TWO-WIRE SERIAL REGISTER INTERFACE The two-wire serial interface bus enables read/write access to control and status registers within the AR0330. This interface is designed to be compatible with the electrical characteristics and transfer protocols of the I specification. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (S CLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). S DATA is pulled up to VDD_IO off-chip by a 1.5 k /C0087 resistor. Either the slave or master device can drive SDATA LOW − the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0330 uses S CLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on S DATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on S DATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for both the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0330 sensor are 0x20 (write address) and 0x21 (read address). Alternate slave addresses of 0x30 (WRITE address) and 0x31 (READ address) can be selected by asserting the SADDR signal (tie HIGH). Alternate slave addresses can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving S DATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

  1. Set the register bit field R0x301A[5] = 1.
  2. Read the register bit fields R0x31FA[11:9].
  3. Determine the CRA value according to Table 42.

Table 42. CRA VALUE

www.onsemi.com PACKAGES The AR0330 comes in two packages:

  • CLCC Package
  • CSP HiSPi/MIPI Package PACKAGE DIMENSIONS CLCC48 CASE 848AU ISSUE O

Table 43. CSP (MIPI/HISPI) PACKAGE DIMENSIONS