AR0237CS ONSEMI | Alldatasheet
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Features
AR0237CS/D Rev. 4, 6/16 EN 1 ©Semiconductor Components Industries, LLC 2016, 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor AR0237/D, Rev. 4 For the latest datasheet, please visit www.onsemi.com
- Superior low-light performance Latest 3.0 m pixel with ON Semiconductor DR-Pix™ technology with Dual Conversion Gain Full HD support at up to 1080P 60 fps for superior video performance Linear or high dynamic range capture Supports line interleaved T1/T2 readout to enable HDR processing in ISP chip Support for external mechanical shutter On-chip phase-locked loop (PLL) oscillator Integrated position-based color and lens shading correction Slave mode for precise frame-rate control Stereo/3D camera support Statistics engine Data interfaces: four-lane serial high-speed pixel interface (HiSPi) differential signaling (SLVS and HiV CM), or parallel Auto black level calibration High-speed configurable context switching Temperature sensor
Applications
Video surveillance 1080p60 (Surveillance) video applications High dynamic range imaging General Description ON Semiconductor's AR0237 is a 1/2.7-inch CMOS digital image sensor with an active-pixel array of 1928Hx1088V. It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. It is designed for both low light and high dynamic range scene performance. It is programmable through a simple two-wire serial inter- face. The AR0237 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continu- ous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. Table 1: Key Parameters Parameter Typical Value Optical format 1/2.7-inch (6.6 mm) Active pixels 1928(H) x 1088(V) (16:9 mode) Pixel size 3.0 m x 3.0m Color filter array RGB Bayer, RGB-IR Shutter type Electronic rolling shutter and GRR Input clock range 6 – 48 MHz Output clock maximum
148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output Serial HiSPi 10-, 12-, 14-, 16-, or 20-bit Parallel 10-, 12-bit Frame rate 1080p 60 fps Linear HiSPi 30 fps Linear Parallel 30 fps Line Interleaved HiSPi 15 fps Line Interleaved Parallel Responsivity 4.0 V/lux-sec SNR MAX 41 dB Max Dynamic range Up to 96 dB Supply voltage I/O 1.8 or 2.8 V Digital 1.8 V Analog 2.8 V HiSPi 0.3 V - 0.6 V (SLVS), 1.7 V - 1.9 V (HiVcm) Power consumption (typical) < 300mW Line interleaved 1080p30 <190mW 1080p30 Linear Mode Operating temperature –30°C to +85°C ambient Package options 10x10 mm 80-pin iBGA 11.43x11.43 mm 48-pin mPLCC
AR0237CS/D Rev. 4, 6/16 EN 2 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Ordering Information
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documenta- tion, including information on evaluation kits, please visit our web site at www.onsemi.com. Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0237CSSC00SUEA0-DR 2Mp 1/2.7" Image Sensor, RGB, 0 deg CRA, iBGA package, multi output Drypack AR0237CSSC00SHRA0-DR 2Mp 1/2.7" Image Sensor, RGB, 0 deg CRA, mPLCC package, HiSPi output Drypack AR0237CSSC00SPRA0-DR 2Mp 1/2.7" Image Sensor, RGB, 0 deg CRA, mPLCC package, Parallel output Drypack AR0237CSSC12SHRA0-DR 2Mp 1/2.7" Image Sensor, RGB, 12 deg CRA, mPLCC package, HiSPi output Drypack AR0237CSSC12SPRA0-DR 2Mp 1/2.7" Image Sensor, RGB, 12 deg CRA, mPLCC package, Parallel output Drypack AR0237IRSH12SHRA0-DR-E 2Mp 1/2.7" Image Sensor, RGB-IR, 12 deg CRA, mPLCC package, HiSPi output Drypack AR0237IRSH12SPRA0-DR-E 2Mp 1/2.7" Image Sensor, RGB-IR, 12 deg CRA, mPLCC package, Parallel output Drypack AR0237CSSC00SUEAH3-GEVB RGB, 0 deg CRA, iBGA package, multi output, Headboard Headboard AR0237CSSC00SHRAH3-GEVB RGB, 0 deg CRA, mPLCC package, HiSPi output, Headboard Headboard AR0237CSSC00SPRAH3-GEVB RGB, 0 deg CRA, mPLCC package, Parallel output, Headboard Headboard AR0237CSSC12SHRAH3-GEVB RGB, 12 deg CRA, mPLCC package, HiSPi output, Headboard Headboard AR0237CSSC12SPRAH3-GEVB RGB, 12 deg CRA, mPLCC package, Parallel output, Headboard Headboard AR0237IRSH12SHRAH3-GEVB RGB-IR, 12 deg CRA, mPLCC package, HiSPi output, Headboard Headboard AR0237IRSH12SPRAH3-GEVB RGB-IR, 12 deg CRA, mPLCC package, Parallel output, Headboard Headboard
AR0237CS/D Rev. 4, 6/16 EN 3 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
AR0237CS/D Rev. 4, 6/16 EN 4 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Table of Contents Table of Contents
AR0237CS/D Rev. 4, 6/16 EN 5 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor General Description General Description The ON Semiconductor AR0237 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080p- resolution image at 60 frames per second (fps) through the HiSPi port. In linear mode, it outputs 12-bit or 10-bit A-Law compressed raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs two exposure values that the ISP will combine into an HDR image. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0237 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. The AR0237 is designed to operate over a wide temperature range of -30°C to +85°C ambient.
AR0237CS/D Rev. 4, 6/16 EN 6 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Functional Overview The AR0237 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor configured in linear mode, and in HDR mode. Figure 1: Block Diagram of AR0237 User interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 2.1 Mp Active- Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog- to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a Row Noise Correction Black Level Correction Test Pattern Generator Pixel Defect Correction Digital Gain and Pedestal A-Law Compression Parallel HiSPi 12 bit s 10 bits ADC Data
AR0237CS/D Rev. 4, 6/16 EN 7 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview high dynamic range mode of operation where two images and taken using different exposures. These images are output in from the sensor and the ISP must combine them into one high dynamic range image. Figure 2: Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies mu st be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two-wire speed. 3. The parallel interface output pads can be left unco nnected if the serial output interface is used. 4. ON Semiconductor recommends that 0.1 F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR0237 demo headboard schematics for circuit recom- mendations. 5. ON Semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match V DD_IO voltage to minimize any leakage currents. VDD_IO V DD_SLVS V DD_PLLVDD VAA VDD VAA VAA_PIX Master clock (6–48 MHz) SDATA SCLK RESET_BAR TEST EXTCLK DGND AGND Digital ground Analog ground Digital Core power1 HiSPi power1 Analog power1 To controller From controller VDD_IO VDD_PLL PLL power1 Digital I/O power1 1.5k:2 1.5k:2 Analog power1 VAA_PIX SLVSC_N SLVSC_P SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SLVS3_P SLVS3_N VDD_SLVS TRIGGER OE_BAR SADDR SHUTTER FLASH
AR0237CS/D Rev. 4, 6/16 EN 8 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Figure 3: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies mu st be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two-wire speed. 3. The serial interface output pads and V DDSLVS can be left unconnected if the parallel output inter- face is used. 4. ON Semiconductor recommends that 0.1 F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR0237 demo headboard schematics for circuit recom- mendations. 5. ON Semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match V DD_IO voltage to minimize any leakage currents. 7. The EXTCLK input is limited to 6-48 MHz. VDD Master clock (6-48 MHz) SDATA SCLK TEST FRAME_VALID DOUT [11:0]EXTCLK DGND Digital ground Analog ground Digital core power1 To controller From Controller LINE_VALID PIXCLK RESET_BAR VDD_IO Digital I/O power1 1.5kΩ2 1.5kΩ2, VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1 VAA_PIXVDD_IO V DD_PLLVDD VAA TRIGGER OE_BAR AGND SADDR SHUTTER FLASH
AR0237CS/D Rev. 4, 6/16 EN 9 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Figure 4: 80-Ball IBGA Package A B C D E F G H J Top View (Ball Down) SLVS0_P SLVS1_P SLVSC_P SLVS2_P SLVS3_P VDD_PLL SLVS0_N SLVS1_N SLVSC_N SLVS2_N SLVS3_N EXTCLK VDD_ SLVSDGND DGND VDD DGND SADDR SCLKSDATA AGND DGND VDD_IO VAA_PIX LINE_ VALID FRAME_ VALID PIXCLK FLASH DOUT7 DOUT1 DOUT11 D OUT10 DOUT9 TESTDOUT4D OUT3 DOUT6DOUT8 DGND TRIGGER OE_BARDOUT0DOUT2 DOUT5 RESET_ BAR 12 3 567 8 4 VDD DGND SHUTTER Reserved DGND VAA VAA VAA VAA VDD VDD VDD VDD VDD Reserved DGND DGND DGND DGND DGND DGND DGND DGND AGND AGND AGND VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO AGNDDGND DGND VDD_IO
AR0237CS/D Rev. 4, 6/16 EN 10 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Table 3: Pin Descriptions, 80-ball iBGA Name iBGA Pin Type Description SLVS0_P A2 Output HiSPi serial data, lane 0, differential P. SLVS1_P A3 Output HiSPi serial data, lane 1, differential P. SLVSC_P A4 Output HiSPi serial DDR clock differential P. SLVS2_P A5 Output HiSPi serial data, lane 2, differential P. SLVS3_P A6 Output HiSPi serial data, lane 3, differential P. VDD_PLL B1 Power PLL power. SLVS0_N B2 Output HiSPi serial data, lane 0, differential N. SLVS1_N B3 Output HiSPi serial data, lane 1, differential N. SLVSC_N B4 Output HiSPi serial DDR clock differential N. SLVS2_N B5 Output HiSPi serial data, lane 2, differential N. SLVS3_N B6 Output HiSPi serial data, lane 3, differential N. SHUTTER B9 Output Control for external mechanical shutte r. Can be left floating if not used. VAA C1, G1, D9, F9 Power Analog power. AGND C2, G2, D8, E8, F8 Power Analog ground. VDD_SLVS C4 Power SLVS Power VDD C5, J5, A9, H9, A7, D1, F1 Power Digital power. Reserved C9, F7 DGND B7, C7, D7, E7, G7, B8, C8, G8, D2, E2, F2, H2, C3, G3, H3, C6, Power Digital ground. EXTCLK D3 Input External input clock. PIXCLK D4 Output Pixel clock out. Dout is valid on rising edge of this clock. SADDR D5 Input Two-Wire Serial address select. 0: 0x20. 1: 0x30 TRIGGER D6 Input Exposure synchronization input. VAA_PIX E9 Power Pixel power. VDD_IO E1, H1, J2, J7, A8, G9, J9 Power I/O supply power. SDATA E3 I/O Two-Wire Serial data I/O. FLASH E4 Output Flash control output. FRAME_VALID E5 Output Asserted when Dout frame data is valid. SCLK E6 Input Two-Wire Serial clock input. DOUT11 F3 Output Parallel pixel data output (MSB) DOUT10 F4 Output Parallel pixel data output. DOUT9F 5 Output Parallel pixel data output. LINE_VALID F6 Output Asserted when Do ut line data is valid. DOUT8G 4 Output Parallel pixel data output. DOUT7G 5 Output Parallel pixel data output. DOUT6G 6 Output Parallel pixel data output. DOUT5H 4 Output Parallel pixel data output. DOUT4H 5 Output Parallel pixel data output. DOUT3H 6 Output Parallel pixel data output. RESET_BAR H7 Input Asynchronous reset (active LOW). All settings are restored to factory default. TEST H8 Input. Manufacturing test enable pin (connect to Dgnd).
AR0237CS/D Rev. 4, 6/16 EN 11 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Figure 5: 48 Pin mPLCC Package HiSPi DOUT2J 1 Output Parallel pixel data output. DOUT1J 3 Output Parallel pixel data output. DOUT0J 4 Output Parallel pixel data output (LSB) OE_BAR J8 Input Output enable (active LOW). Table 3: Pin Descriptions, 80-ball iBGA Name iBGA Pin Type Description
AR0237CS/D Rev. 4, 6/16 EN 12 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Table 4: mPLCC HiSPi Pin Out Pin Name Type Description
1 SLVSCN Output HiSPi serial DDR clock differential N
2 SLVS1P Output HiSPi serial data, lane 1, differential P
3 SLVS1N Output HiSPi serial data, lane 1, differential N
4 SLVS0P Output HiSPi serial data, lane 0, differential P
5 SLVS0N Output HiSPi serial data, lane 0, differential N
6 VDD_SLVS Power SLVS Power 0.3 V-0.6 V
7 DGND Power Digital ground
8 VDD_PLL Power PLL power
9 EXTCLK Input External input clock
10 VAA Power Analog Power
11 AGND Power Analog Ground
12 VDD_IO Power I/O Power Supply
13 VDD Power Digital Power
14 DGND Power Digital ground
15 Reserved
16 VAA Power Analog Power
17 AGND Power Analog Ground
18 DGND Power Digital ground
19 VDD Power Digital Power
20 VDD_IO Power I/O Power Supply
21 FLASH Output Flash control output
22 TEST Input Manufacturing test enable pin (connect to DGNG)
23 SDATA I/O Two-Wire Serial data I/O
24 SADDR Input Two-Wire Serial address select. 0: 0x20, 1: 0x30
25 SCLK Input Two-Wire Serial clock input
26 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
27 OE_BAR Input Output enable (active LOW)
28 TRIGGER Input Exposure synchronization input
29 SHUTTER Output Control for external mechanica l shutter. Can be left floating if not used.
30 VDD_IO Power I/O Power Supply
31 VDD Power Digital Power
32 DGND Power Digital ground
33 AGND Power Analog Ground
34 VAA_PIX Power Pixel Power
35 VAA Power Analog Power
36 Reserved
37 VAA Power Analog Power
38 VAA_PIX Power Pixel Power
39 AGND Power Analog Ground
AR0237CS/D Rev. 4, 6/16 EN 13 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview
40 DGND Power Digital ground
41 VDD Power Digital Power
42 VDD_IO Power I/O Power Supply
43 VDD 1V8_PHY Power 1.8 V supply for HiVcm mode
44 SLSV3P Output HiSPi serial data, lane 3, differential P
45 SLVS3N Output HiSPi serial data, lane 3, differential N
46 SLVS2P Output HiSPi serial data, lane 2, differential P
47 SLVS2N Output HiSPi serial data, lane 2, differential N
48 SLVSLCP Output HiSPi serial DDR clock differential P
Table 4: mPLCC HiSPi Pin Out
AR0237CS/D Rev. 4, 6/16 EN 14 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview Figure 6: 48 Pin mPLCC Package Parallel Table 5: mPLCC Parallel Pin Out Pin Name Type Description
1 DOUT6 Output Data output 6
2 DOUT7 Output Data output 7
3 DOUT8 Output Data output 8
4 DOUT9 Output Data output 9
5 DOUT10 Output Data output 10
6 DOUT11 Power Data output 11
18 VDD Power Digital Power
19 VDD_IO Power I/O Power Supply
20 FLASH Power Flash control output
21 PIXCLK Output Pixel Clock
22 FRAME_VALID Output Frame Valid
23 TEST Input Manufacturing test enable pin (connect to DGNG)
24 DGND Power Digital Ground
AR0237CS/D Rev. 4, 6/16 EN 15 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Functional Overview
25 SDATA I/O Two-Wire Serial data I/O
26 LINE_VALID Output Line Valid
27 SADDR Input Two-Wire Serial address select. 0: 0x20, 1: 0x30
28 SCLK Input Two-Wire Serial clock input
29 VDD_IO Power I/O Power Supply
30 VDD Power Digital Power
31 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
32 OE_BAR Input Output enable (active LOW)
33 TRIGGER Input Exposure synchronization input
34 SHUTTER Output Control for external mechanical s hutter. Can be left floating if not used.
35 RESERVED Input Reserved
36 AGND Power Analog Ground
37 VAA_2V8 Power Analog Power
43 DOUT0 Output Data Output 0
44 DOUT1 Output Data Output 1
45 DOUT2 Output Data Output 2
46 DOUT3 Output Data Output 3
47 DOUT4 Output Data Output 4
48 DOUT5 Output Data Output 5
Table 5: mPLCC Parallel Pin Out
AR0237CS/D Rev. 4, 6/16 EN 16 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure While the sensor's format is 1928 x1088, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for mono- chrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. Figure 7: Pixel Array Description 10 barrier + 4 border pixels Light dummy pixel Active pixel 10 barrier + 4 border pixels 1944 2 barrier + 6 border pixels 2 barrier + 6 border pixels 1116 19281 x 1088 5.78 mm x 3.26 mm
AR0237CS/D Rev. 4, 6/16 EN 19 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Features Overview For a complete description, recommendations, and usage guidelines for product features, refer to the AR0237 Developer Guide. 3.0m Dual Conversion Gain Pixel To improve the low light performance and keep the high dynamic range, a large (3.0um) dual conversion gain pixel is implemented for better image optimization. With a dual conversion gain pixel, the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene. HDR By default, the sensor powers up in Linear Mode. One can change to HDR Mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle up to 96 dB of dynamic range. In HDR mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. The exposure ratio may be set to 4x, 8x, 16x, or 32x. Sensor also provides flexibility to choose any exposure ratio by setting number of t2 exposure rows indepen- dent of the t1 exposure. The data will be output as line interleaved data as described in the T1/T2 Line Interleaved Mode section. There is also an option to output either T1 only or T2 only. Resolution The active array supports a maximum of 1928x1088 pixels to support 1080p resolution. Utilizing a 3.0um pixel will result in an optical format of 1/2.7-inch (approximately 6.6mm diagonal). Frame Rate At full (1080p) resolution, the AR0237 is capable of running up to 60 fps in linear mode and 30 fps in line interleaved mode. Image Acquisition Mode The AR0237 supports two image acquisition modes: Electronic rolling shutter (ERS) mode This is the normal mode of operation. When the AR0237 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When ERS mode is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between reset- ting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0237 switches cleanly from the old integration time to the new while only generating frames with uniform inte- gration. See “Changes to Integration Time” in the AR0237 Register Reference.
AR0237CS/D Rev. 4, 6/16 EN 20 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Global reset mode. This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0237 provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Embedded Data and Statistics The AR0237 has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout. Embedded Data: If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. E m b e d d e d S t a t i s t i c s : If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. Multi-Camera Synchronization The AR0237 supports advanced line synchronization controls for multi-camera (stereo) support. Slave Mode The slave mode feature of the AR0237 supports triggering the start of a frame readout from an input signal that is supplied from an external ASIC. The slave mode signal allows for precise control of frame rate and register change updates. Context Switching and Register Updates The user has the option of using the highly configurable context memory, or a simplified implementation in which only a subset of registers is available for switching. The AR0237 supports a highly configurable context switching RAM of size 256 x 16. Within this Context Memory, changes to any register may be stored. The register set for each context must be the same, but the number of contexts and registers per context are limited only by the size of the context memory. Alternatively, the user may switch between two predefined register sets A and B by writing to a context switch change bit. When the context switch is configured to context A the sensor will reference the context A registers. If the context switch is changed from A to B during the readout of frame n, the sensor will then reference the context B coarse_integration_time registers in frame n+1 and all other context B registers at the beginning of reading frame n+2. The sensor will show the same behavior when changing from context B to context A. The registers listed in Table 6 are context-switchable:
AR0237CS/D Rev. 4, 6/16 EN 21 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Table 6: List of Configurable Registers for Context A and Context B Analog/Digital Gains A programmable analog gain of 1.0x to 16x (linear and HDR) applied simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis. Note that with the RGB IR sensor digital gain should only be applied to all color channels equally since with the 4x4 kernel the gains will not be applied to the proper color channel. Analog gain can be applied per exposure in line interleaved mode. Skipping/Binning Modes The AR0237 supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. Horizontal binning is achieved in the digital readout. The sensor will sample the combined 2x adjacent pixels within the same color plane. Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x rows within the same color plane. Pixel skipping can be configured up to 2x in both the x-direction and y- Context A Context B Register Description Register Description coarse_integration_time coarse_integration_time_cb line_length_pck line_length_pck_cb frame_length_lines frame_length_lines_cb row_bin row_bin_cb col_bin col_bin_cb fine_gain fine_gain_cb coarse_gain coarse_gain_cb coarse_integration_time2 co arse_integration_time2_cb dcg_manual_set dcg_manual_set_cb dcg_manual_set_t1 dcg_manual_set_t1_cb bypass_pix_comb bypass_pix_cb coarse_gain_t1 coarse_gain_t1_cb fine_gain_t1 fine_gain_t1_cb x_addr_start x_addr_start_cb y_addr_start y_addr_start_cb green1_gain green1_gain_cb blue_gain blue_gain_cb red_gain red_gain_cb green2_gain green2_gain_cb global_gain global_gain_cb operation_mode_ctrl ope ration_mode_ctrl_cb bypass_pix_comb bypass_pix_comb_cb
AR0237CS/D Rev. 4, 6/16 EN 22 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in the y direction will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. The AR0237 supports row wise vertical binning. Row wise vertical summing is only supported in monochrome sensors. Binning and summing is not supported with RGB IR sensors. Clocking Options The sensor contains a phase-locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre-PLL clock divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an even multiplier value. The multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Use of the PLL is required when using the HiSPi interface. Temperature Sensor The AR0237 sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device char- acteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to convert the ADC output value to the final tempera- ture in degrees Celsius. A single reference point will be made available via register read as well as a slope for back-calculating the junction temperature value. An error of +/-5% or better over the full specified operating range of the sensor is to be expected. Silicon / Firmware / Sequencer Revision Information A revision register will be provided to read out (via I2C) silicon and sequencer/OTPM revision information. This will be helpful to distinguish among different lots of material if there are future OTPM or sequencer revisions. Lens Shading Correction The latest lens shading correction algorithm will be included for potential low Z height applications. Compression When the AR0237 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using A-law compression. The A-law compression is disabled by default. Packaging The AR0237 will be offered in a 10x10 80-iBGA package (parallel and HiSPi) and a 11.43x1143 48 pin mPLCC (HiSSPi) package.
AR0237CS/D Rev. 4, 6/16 EN 23 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Parallel Interface The parallel pixel data interface uses these output-only signals: F R A M E _ V A L I D L I N E _ V A L I D P I X C L K OUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. High Speed Serial Pixel (HiSPi) Interface The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. The AR0237 supports serial data widths of 10 or 12 bits on one, two, or four lanes. The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x0000 to reduce jitter, skew, and power dissipation. Sensor Control Interface The two-wire serial interface bus enables read/write access to control and status regis- ters within the AR0237. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (S CLK) that is an input to the sensor and is used to synchronize trans- fers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW-the interface protocol determines which device is allowed to drive SDATA at any given time. The two-wire serial interface can run at 100 kHz or 400 kHz. T1/T2 Line Interleaved Mode The AR0237 outputs the T1 and T2 exposures separately, in a line interleaved format. The purpose of this is to enable off chip HDR linear combination and processing. See the AR0237 Developer Guide for more information.
AR0237CS/D Rev. 4, 6/16 EN 24 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Figure 11: Quantum Efficiency - RGB 350 450 550 650 750 850 950 1050 1150 Quantum Efficiency (%) Wavelength (nm) Red Green Blue
AR0237CS/D Rev. 4, 6/16 EN 25 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Features Overview Figure 12: Quantum Efficiency - RGB - IR 0 200 400 600 800 1000 1200 Quantum Efficiency (%) Wavelength (nm) Red (%) Green (R) (%) Green (B) (%) Blue (%) IR (%)
AR0237CS/D Rev. 4, 6/16 EN 26 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Electrical Specifications Unless otherwise stated, the following specifications apply under the following condi- VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +85°C-40°C to +105°C; output load = 10pF; frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 13 and Table 7. Figure 13: Two-Wire Serial Bus Timing Parameters Note: Read sequence: For an 8-bit READ, read wa veforms start after WRITE command and register address are issued. Table 7: Two-Wire Serial Bus Characteristics Parameter Symbol Standard Mode Fast Mode UnitMin Max Min Max SCLK Clock Frequency fSCL 0 100 0 400 KHz Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 4.0 - 0.6 - s LOW period of the SCLK clock tLOW 4.7 - 1.3 - s HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - s Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - s Data hold time tHD;DAT 0 4 3.455 06 0.95 s Data set-up time tSU;DAT 250 - 100 6 -n s Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb 7 300 ns Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb 7 300 ns Set-up time for STOP condition tSU;STO 4.0 - 0.6 - s Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - s Capacitive load for each bus line Cb - 400 - 400 pF S Sr tSU;STOtSU;STAtHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDATA SCLK P S tBUFtr tftr tHD;STA
AR0237CS/D Rev. 4, 6/16 EN 27 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Notes: 1. This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor. 2. Two-wire control is I 2C-compatible. 4. A device must internally provide a ho ld time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. I/O Timing By default, the AR0237 launches pixel data, FV, and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of PIXCLK. See Figure 14 below and Table 8 on page 28 for I/O timing (AC) characteristics. Figure 14: I/O Timing Diagram Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF SDATA max load capacitance CLOAD_SD - 30 - 30 pF SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 K Table 7: Two-Wire Serial Bu s Characteristics (continued) Parameter Symbol Standard Mode Fast Mode UnitMin Max Min Max Data[11:0] LINE_VALID/ PIXCLK EXTCLK tR tEXTCLK tF FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. tPLH tPFH tPFL tPLL tPD Pxl _0 Pxl _1 Pxl _2 Pxl _n 90% 10% tRP tFP 90% 10% FRAME_VALID
AR0237CS/D Rev. 4, 6/16 EN 28 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Note: I/O timing characteristics are me asured under the following conditions: - Temperature is 25°C ambient - 10 pF load - 1.8V I/O supply voltage Table 8: I/O Timing Characteristics Symbol Definition Condition Min Typ Max Unit fEXTCLK1s Input clock frequency 6 – 48 MHz tEXTCLK1 Input clock period 20.8 – 166 ns tR Input clock rise time – 3 – ns tF Input clock fall time – 3 – ns tRP Pixclk rise time 2 3.5 5 ns tFP Pixclk fall time 2 3.5 5 ns Clock duty cycle 45 50 55 % tCP EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled 10 14 18 ns fPIXCLK PIXCLK frequency Default, Nominal Voltages 6– 7 4 . 2 5 M H z tPD PIXCLK to data valid Default, Nominal Voltages –3 – n s tPFH PIXCLK to FV HIGH Default, Nominal Voltages –3 – n s tPLH PIXCLK to LV HIGH Default, Nominal Voltages –3 – n s tPFL PIXCLK to FV LOW Default, Nominal Voltages –3 – n s tPLL PIXCLK to LV LOW Default, Nominal Voltages –3 – n s CLOAD Output load capacitance – <10 – pF CIN Input pin capacitance – 2.5 – pF
AR0237CS/D Rev. 4, 6/16 EN 29 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications The DC electrical characteristics are shown in the tables below. Caution Stresses greater than those listed in Table 10 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. Note: Exposure to ab solute maximum rating conditions for extended periods may affect reliability. Table 9: DC Electrical Characteristics Symbol Definition Condition Min Typ Max Unit VDD Core digital voltage 1.7 1.8 1.95 V VAA Analog voltage 2.5 2.8 3.1 V VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V VDD_PLL PLL supply voltage 2.5 2.8 3.1 V VDD_SLVS HiSPi supply voltage 0.3 0.4 0.6 V VIH Input HIGH voltage V DD_IO*0.7 – – V VIL Input LOW voltage – – V DD_IO*0.3 V IIN Input leakage current No pull-up resistor; VIN = VDD_IO or DGND 20 – – A VOH Output HIGH voltage V DD_IO-0.3 – – V VOL Output LOW voltage – – 0.4 V IOH Output HIGH current At specified V OH -22 – – mA IOL Output LOW current At specified V OL ––2 2 m A Table 10: Absolute Maximum Ratings Symbol Definition Condition Min Max Unit VDD_MAX Core digital voltage –0.3 2.4 V VDD_IO_MAX I/O digital voltage –0.3 4 V VAA_MAX Analog voltage –0.3 4 V VAA_PIX Pixel supply voltage –0.3 4 V VDD_PLL PLL supply voltage –0.3 4 V VDD_SLVS_MAX HiSPi I/O digital voltage –0.3 2.4 V tST Storage temperature –40 85 °C
AR0237CS/D Rev. 4, 6/16 EN 30 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL = VDD_IO =2.8 V - VDD= 1.8 V - PLL Enabled and PIXCLK = 74.25 MHz - Low power mode enabled - TA = 25°C Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL =2.8 V - VDD = VDD_IO= 1.8 V - PLL Enabled and PIXCLK = 74.25 MHz - Low power mode enabled - T A = 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time Table 11: 1080p30 Linear 74 MHz Parallel 2.8V Definition Condition Symbol Voltage Min Typ Max Unit Digital operating current Streaming 1080p30 IDD 1.8 20 34 50 mA I/O digital operating current Streaming 1080p30 IDD_IO 2.8 15 28 50 mA Analog operating current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel supply current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL supply current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA Power 138.2 238.72 409.2 mW Table 12: 1080p30 Linear 74 MHz Parallel 1.8V Definition Condition Symbol Voltage Min Typ Max Unit Digital operating current Streaming 1080p30 IDD 1.8 20 34 50 mA I/O digital operating current Streaming 1080p30 IDD_IO 1.8 10 14 30 mA Analog operating current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel supply current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL supply current Streaming 1080p30 IDD_PLL 2.8 5.5 6.4 7 mA Power 114.2 185.52 323.2 mW
AR0237CS/D Rev. 4, 6/16 EN 31 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL =2.8 V - VDD = VDD_IO= 1.8 V - VDD_SLVS= 0.4V - PLL Enabled and PIXCLK = 74.25 MHz - 4-lane HiSPi mode - Low power mode enabled - T A = 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL =2.8 V - VDD = VDD_IO = VDD_SLVS= 1.8 V - PLL Enabled and PIXCLK = 74.25 MHz - 4-lane HiSPi mode - Low power mode enabled - T A = 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time Table 13: 1080p30 Linear 74 MHz HiSPi SLVS Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 25 44 65 mA Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA Power 109 185.2 306 mW Table 14: 1080p30 Linear 74 MHz HiSPi HiVcm Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 25 44 65 mA Analog Operating Current Streaming 1080p30 IAA 2.8 15 26 50 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 3 7 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 6 7.5 8.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA Power 128.2 217.4 363.4 mW
AR0237CS/D Rev. 4, 6/16 EN 32 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Electrical Specifications Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL =2.8 V - VDD = VDD_IO= 1.8 V - VDD_SLVS= 0.4V - PLL Enabled and PIXCLK = 74.25 MHz - 4-lane HiSPi mode - T A= 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time Note: Operating currents are measured in mA at the following conditions: - VAA = VAA_PIX = VDD_PLL = 2.8 V - VDD= VDD_IO = 1.8 V - VDD_SLVS = 1.8 V - PLL Enabled and PIXCLK = 74.25 MHz - 4-lane HiSPi mode - TA = 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time HiSPi Electrical Specifications The ON Semiconductor AR0237 sensor supports both SLVS and HiVCM HiSPi modes. Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specifica- tion. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The DLL as implemented on AR0237 is limited in the number of available delay steps and differs from the HiSPi specification as described in this section. Table 15: 1080p30 74 MHz Line Interleaved SLVS Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 0.4 6 9.5 14 mA Power 170.8 298 442.6 mW Table 16: 1080p30 74 MHz Line Interleaved HiVcm Definition Condition Symbol Voltage Min Typ Max Unit Digital Operating Current Streaming 1080p30 IDD 1.8 50 88 130 mA Analog Operating Current Streaming 1080p30 IAA 2.8 20 36 60 mA Pixel Supply Current Streaming 1080p30 IAA_PIX 2.8 1 4 8 mA PLL Supply Current Streaming 1080p30 IDD_PLL 2.8 7 8.5 9.5 mA SLVS Supply Current Streaming 1080p30 IDD_SLVS 1.8 12 20 35 mA Power 190 330.2 500 mW Table 17: Channel Skew Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.4V; Data Rate =480 Mbps; DLL set to 0 Data Lane Skew in Reference to Clock tCHSKEW1PHY -150 ps
AR0237CS/D Rev. 4, 6/16 EN 33 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the AR0237 is shown in Figure 15. The avail- able power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on V DD_PLL power supply. 2. After 100 s, turn on VAA and VAA_PIX power supply. 3. After 100 s, turn on VDD_IO power supply. 4. After 100 s, turn on VDD power supply. 5. After 100 s, turn on VDD_SLVS power supply. 6. After the last power supply is stable, enable EXTCLK. 7. Assert RESET_BAR for at least 1ms. The parall el interface will be tri-stated during this time. 8. Wait 150000 EXTCLKs (for internal initialization into software standby. 9. Configure PLL, output, and imag e settings to desired values. 10. Wait 1ms for the PLL to lock. 11. Set streaming mode (R0x301a[2] = 1). Figure 15: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) VDD_IO (1.8/2.8) VDD (1.8) VDD_SLVS (0.4) EXTCLK RESET_BAR tx t5 t6 Hard Reset Internal Initialization Software Standby PLL Lock Streaming
AR0237CS/D Rev. 4, 6/16 EN 34 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Notes: 1. Xtal settling time is component-de pendent, usually taking about 10 – 100 ms. 2. Hard reset time is the minimum time required af ter power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. Table 18: Power-Up Sequence Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX3 t0 0 100 – s VAA/VAA_PIX to VDD_IO t1 0 100 – s VDD_IO to VDD t2 0 100 – s VDD to VDD_SLVS t3 0 100 – s Xtal settle time tx – 30 1 –m s Hard Reset t4 1 2 –– m s Internal Initialization t5 150000 – – EXTCLKs PLL Lock Time t6 1 – – ms
AR0237CS/D Rev. 4, 6/16 EN 35 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Power-Down Sequence The recommended power-down sequence for the AR0237 is shown in Figure 16. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is re ached after the current row or frame, depending on config- uration, has ended. 3. Turn off V DD_SLVS. 4. Turn off V DD. 5. Turn off V DD_IO. 6. Turn off V AA/VAA_PIX. 7. Turn off V DD_PLL. Figure 16: Power Down t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. Table 19: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD t0 0 – – s VDD to VDD_IO t1 0 – – s VDD_IO to VAA/VAA_PIX t2 0 – – s VAA/VAA_PIX to VDD_PLL t3 0 – – s Power Down until Next Power Up Time t4 100 – – ms V DD_IO (1.8/2.8) t 0 EXTCLK VDD_SLVS (0.4) VDD (1.8) VAA_PIX VAA (2.8) VDD_PLL (2.8) Power Down until next Power up cycle
AR0237CS/D Rev. 4, 6/16 EN 36 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Package Diagrams Figure 17: PLCC 48 11.43 x 11.43 Package Diagram (Case 776AQ) PLCC48 11.43x11.43 CASE 776AQ ISSUE A DATE 20 NOV 2015
AR0237CS/D Rev. 4, 6/16 EN 37 ©Semiconductor Components Industries, LLC, 2016. AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Figure 18: 80iBGA 10x10 Package Diagram (Case 503BA) IBGA80 10x10 CASE 503BA ISSUE O DATE 07 JUL 2015
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